请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

5T9304

型号：

5T9304

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

180 K

下载PDF手册
LVDS, 1:4 Clock Buffer Terabuffer™  
5T9304  
DATA SHEET  
General Description  
Features  
The 5T9304 differential clock buffer has a user-selectable differential  
input to four LVDS outputs. The fanout from a differential input to four  
LVDS outputs reduces loading on the preceding driver and provides  
an efficient clock distribution network. The 5T9304 can act as a  
translator from a differential HSTL, eHSTL, LVEPECL (2.5V),  
LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A  
single-ended 3.3V / 2.5V LVTTL input can also be used to translate  
to LVDS outputs. The redundant input capability allows for an  
asynchronous change-over from a primary clock source to a  
secondary clock source. Selectable reference inputs are controlled  
by SEL.  
• Guaranteed low skew: 50ps (maximum)  
• Very low duty cycle distortion: 125ps (maximum)  
• Propagation delay: 1.75ns (maximum)  
• Up to 450MHz operation  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V),  
LVPECL (3.3V), CML or LVDS input interface  
• Selectable differential inputs to four LVDS outputs  
• 2.5V VDD  
• 0°C to 70°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
The 5T9304 outputs can be asynchronously enabled/disabled.  
When disabled, the outputs will drive to the value selected by the GL  
pin. Multiple power and grounds reduce noise.  
•
Applications  
• Clock distribution  
Pin Assignment  
A2  
A2  
GND  
PD  
1
2
24  
23  
GND  
VDD  
RESERVED  
VDD  
3
4
22  
21  
5
6
7
8
20  
19  
18  
17  
Q3  
Q3  
Q4  
Q1  
Q1  
Q2  
Q4  
Q2  
VDD  
SEL  
G
VDD  
GL  
A1  
9
16  
15  
14  
13  
10  
11  
12  
GND  
A1  
5T9304  
24-Lead TSSOP  
4.4mm x 7.8mm x 1.0mm package body  
G Package  
Top View  
5T9304 Rev A 5/13/15  
1
©2015 Integrated Device Technology, Inc.  
5T9304 DATA SHEET  
Block Diagram  
GL  
G
Q1  
Q1  
OUTPUT  
CONTROL  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
A1  
1
0
Q3  
Q3  
OUTPUT  
CONTROL  
A2  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
SEL  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
2
Rev A 5/13/15  
5T9304 DATA SHEET  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1, 12, 22  
GND  
Power  
LVTTL  
Power supply return for all power.  
Power-down control. Shuts off entire chip. If LOW, the device goes into low  
power mode. Inputs and outputs are disabled. Both Qx and Qx outputs will  
pull to VDD. Set HIGH for normal operation.(3)  
2
PD  
Input  
3
RESERVED  
VDD  
Reserved  
Reserved pin.  
4, 9, 16, 21  
Power  
LVDS  
Power supply for the device core and inputs.  
5, 7,  
18, 20  
Q1, Q2,  
Q4, Q3  
Output  
Output  
Input  
Complementary differential clock outputs.  
Differential clock outputs.  
6, 8,  
17, 19  
Q1, Q2,  
Q4, Q3  
LVDS  
Reference clock select. When LOW, selects A2 and A2. When HIGH,  
selects A1 and A1.  
10  
SEL  
LVTTL  
Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G  
is LOW, the differential outputs are active. When G is HIGH, the differential  
11  
G
Input  
Input  
LVTTL  
outputs are asynchronously driven to the level designated by GL(2)  
.
13, 24  
A1, A2  
Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.  
Complementary clock inputs. A[1:2] is the complementary side of A[1:2].  
For LVTTL single-ended operation, A[1:2] should be set to the desired  
14, 23  
A1, A2  
GL  
Input  
Input  
Adjustable (1, 4) toggle voltage for A[1:2]:  
3.3V LVTTL VREF = 1650mV  
2.5V LVTTL VREF = 1250mV  
Specifies output disable level. If HIGH, Qx outputs disable HIGH and Qx  
outputs disable LOW. If LOW, Qx outputs disable LOW and Qx outputs  
disable HIGH.  
15  
LVTTL  
NOTES:  
1.  
Inputs are capable of translating the following interface standards:  
Single-ended 3.3V and 2.5V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels  
Differential LVDS levels  
Differential CML levels  
2.  
3.  
4.  
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control  
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.  
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting PD.  
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is  
no input signal.  
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz))  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input Capacitance  
3
pF  
NOTE: This parameter is measured at characterization but not tested.  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
3
Rev A 5/13/15  
5T9304 DATA SHEET  
Function Tables  
Table 3A. Gate Control Output Table  
Control Output  
Outputs  
GL  
0
G
0
1
0
1
Q[1:4]  
Toggling  
LOW  
Q[1:4]  
Toggling  
HIGH  
0
1
Toggling  
HIGH  
Toggling  
LOW  
1
Table 3B. Input Selection Table  
Selection SEL pin  
Inputs  
A2, A2  
A1, A1  
0
1
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC  
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Power Supply Voltage, VDD  
Input Voltage, VI  
-0.5V to +3.6V  
-0.5V to +3.6V  
Output Voltage, VO  
Not to exceed 3.6V  
-0.5 to VDD +0.5V  
Storage Temperature, TSTG  
Junction Temperature, TJ  
-65C to 150C  
150C  
Recommended Operating Range  
Symbol  
TA  
Description  
Minimum  
Typical  
25  
Maximum  
Units  
C  
Ambient Operating Temperature  
Internal Power Supply Voltage  
0
70  
VDD  
2.3  
2.5  
2.7  
V
Rev A 5/13/15  
4
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5T9304 DATA SHEET  
DC Electrical Characteristics  
Table 4A. LVDS Power Supply DC Characteristics(1), VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
VDD = Max.,  
All Input Clocks = LOW(2)  
Output enabled  
IDDQ  
Quiescent VDD Power Supply Current  
;
240  
mA  
V
DD = 2.7V;  
ITOT  
IPD  
Total Power VDD Supply Current  
Total Power Down Supply Current  
250  
5
mA  
mA  
FREFERENCE Clock = 450MHz  
PD = LOW  
NOTE 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.  
NOTE 2. The true input is held LOW and the complementary input is held HIGH.  
Table 4B. LVCMOS/LVTTL DC Characteristics(1), VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
IIH  
Input High Current  
5
5
IIL  
Input Low Current  
VDD = 2.7V  
VIK  
VIN  
VIH  
VIL  
VTHI  
Clamp Diode Voltage  
DC Input Voltage  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
-0.3  
1.7  
V
DC Input High Voltage  
DC Input Low Voltage  
DC Input Threshold Crossing Voltage  
V
0.7  
V
VDD/2  
1.65  
V
3.3V LVTTL  
2.5V LVTTL  
V
VREF  
Single-Ended Reference Voltage (3)  
1.25  
V
NOTE 1. See Recommended Operating Range table.  
NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.  
Table 4C. Differential DC Characteristics(1), VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
IIH  
Parameter  
Test Conditions  
VDD = 2.7V  
Minimum  
Typical(2)  
Maximum  
Units  
µA  
µA  
V
Input High Current  
5
5
IIL  
Input Low Current  
VDD = 2.7V  
VIK  
Clamp Diode Voltage  
DC Input Voltage  
DC Differential Voltage(3)  
DC Common Mode Input Voltage(4)  
VDD = 2.3V, IIN = -18mA  
-0.7  
-1.2  
3.6  
VIN  
-0.3  
0.1  
V
VDIF  
VCM  
V
0.05  
VDD  
V
NOTE 1. See Recommended Operating Range table.  
NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient.  
NOTE 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is  
the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC  
differential voltage must be achieved to guarantee switching to a new state.  
NOTE 4. VCM specifies the maximum allowable range of (VTR + VCP) /2.  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5
Rev A 5/13/15  
5T9304 DATA SHEET  
Table 4D. LVDS DC Characteristics(1), VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical(2)  
Maximum  
Units  
Differential Output Voltage for the  
True Binary State  
VOT(+)  
247  
454  
454  
50  
mV  
Differential Output Voltage for the  
False Binary State  
VOT(–)  
VOT  
VOS  
247  
mV  
mV  
V
Change in VOT Between Complementary  
Output States  
Output Common Mode Voltage  
(Offset Voltage)  
1.125  
1.2  
1.375  
50  
Change in VOS Between Complementary  
Output States  
VOS  
mV  
IOS  
Outputs Short Circuit Current  
VOUT+ and VOUT– = 0V  
VOUT+ = VOUT–  
12  
6
24  
12  
mA  
mA  
IOSD  
Differential Outputs Short Circuit Current  
NOTE 1. See Recommended Operating Range table.  
NOTE 2. Typical values are at VDD = 2.5V, +25°C ambient.  
AC Electrical Characteristics  
Table 5A. HSTL Differential Input AC Characteristics, VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
1
V
mV  
%
750  
50  
DH  
Duty Cycle  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5B. eHSTL AC Differential Input Characteristics, VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Signal Crossing Point(2)  
Value  
Units  
V
1
900  
mV  
%
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Rev A 5/13/15  
6
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5T9304 DATA SHEET  
Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
Parameter  
Input Signal Swing(1)  
Maximum  
Units  
mV  
mV  
mV  
%
VDIF  
732  
LVEPECL  
LVPECL  
1082  
VX  
Differential Input Cross Point Voltage(2)  
1880  
DH  
Duty Cycle  
50  
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an  
automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5D. LVDS Differential Input AC Characteristics, TA = 0°C to 70°C  
Symbol  
VDIF  
VX  
Parameter  
Input Signal Swing(1)  
Differential Input Cross Point Voltage(2)  
Maximum  
Units  
mV  
V
400  
1.2  
DH  
Duty Cycle  
50  
%
VTHI  
tR / tF  
Input Timing Measurement Reference Level(3)  
Input Signal Edge Rate(4)  
Crossing Point  
2
V
V/ns  
NOTE 1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)  
environment. This device meets the VDIF (AC) specification under actual use conditions.  
NOTE 2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This  
device meets the VX specification under actual use conditions.  
NOTE 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
NOTE 4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
Table 5E. AC Differential Input Characteristics(1), VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
VDIF  
VX  
Parameter  
Minimum  
0.1  
Typical  
Maximum  
3.6  
Units  
AC Differential Voltage(2)  
Differential Input Cross Point Voltage  
Common Mode Input Voltage Range(3)  
Input Voltage  
V
V
V
V
0.05  
VDD  
VCM  
VIN  
0.05  
VDD  
-0.3  
3.6  
NOTE 1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been  
met or exceeded.  
NOTE 2. VDIF specifies the minimum input voltage (VTR – VCP) required for switching where VTR is the “true” input level and VCP is the  
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.  
NOTE 3. VCM specified the maximum allowable range of (VTR + VCP) /2.  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
7
Rev A 5/13/15  
5T9304 DATA SHEET  
Table 5F. AC Characteristics(1,5), VDD = 2.5V 0.2V, TA = 0°C to 70°C  
Symbol  
tsk(o)  
tsk(p)  
tsk(pp)  
tpLH  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
ps  
Same Device Output Pin-to-Pin Skew (2)  
Pulse Skew(3)  
Part-to-Part Skew(4)  
50  
125  
300  
1.75  
1.75  
450  
ps  
ps  
Propagation Delay, Low-to-High  
Propagation Delay, High-to-Low  
Frequency Range(6)  
1.25  
1.25  
ns  
A Crosspoint to Qn, Qn  
Crosspoint  
tpHL  
ns  
fo  
MHz  
Output Gate Enable Crossing  
VTHI-to-Qn/Qn Crosspoint  
tPGE  
3.5  
3.5  
ns  
ns  
Output Gate Enable Crossing  
VTHI-to-Qn/Qn Crosspoint Driven to  
Designated Level  
tPGD  
tPWRDN  
tPWRUP  
tR / tF  
PD Crossing VTHI-to-Qn = VDD, Qn = VDD  
100  
100  
600  
µS  
µS  
ps  
Output Gate Disable Crossing VTHI to  
Qn/Qn Driven to Designated Level  
Output Rise/Fall Time(6)  
20% to 80%  
125  
NOTE. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.  
NOTE 2. Skew measured between Crosspoint of all differential output pairs under identical input and output interfaces, transitions and load  
conditions on any one device.  
NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any differential output pair under identical input  
and output interfaces, transitions and load conditions on any one device.  
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,  
given identical transitions and load conditions at identical VDD levels and temperature.  
NOTE 5. All parameters are tested with a 50% input duty cycle.  
NOTE 6. Guaranteed by design but not production tested.  
Rev A 5/13/15  
8
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5T9304 DATA SHEET  
Differential AC Timing Waveforms  
Output Propagation and Skew Waveforms  
1/fo  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - A[1:2]  
tPHL  
tPLH  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
tSK(O)  
tSK(O)  
+ VDIF  
VDIF = 0  
- VDIF  
Qm - Qm  
NOTE 1: Pulse skew is calculated using the following expression:  
tsk(p) = |tpHL – tpLH|  
Note that the tpHL and tpLH shown above ae not valid measurements for this calculation because they are not taken from the same pulse.  
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.  
Differential Gate Disabled/Endable Showing Runt Pulse Generation  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - A[1:2]  
VIH  
VTHI  
VIL  
GL  
G
tPLH  
VIH  
VTHI  
VIL  
tPGD  
tPGE  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G  
signal to avoid this problem.  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
9
Rev A 5/13/15  
5T9304 DATA SHEET  
Power Down Timing  
+VDIF  
VDIF=0  
-VDIF  
A1 - A1  
+VDIF  
VDIF=0  
-VDIF  
A2 - A2  
VIH  
VTHI  
VIL  
G
VIH  
VTHI  
VIL  
PD  
+VDIF  
VDIF=0  
-VDIF  
Qn - Qn  
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain  
disabled until the device completes power-up after asserting PD.  
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.  
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is  
shown when Qn/Qn goes to VDIF = 0.  
Rev A 5/13/15  
10  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5T9304 DATA SHEET  
Test Circuit for Differential Input  
~50Ω  
Transmission Line  
VIN  
VDD/2  
A
A
D.U.T.  
Pulse  
Generator  
~50Ω  
Transmission Line  
VIN  
-VDD/2  
Scope  
50Ω  
50Ω  
Table 6A. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
VTHI  
Crossing of A and A  
V
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
11  
Rev A 5/13/15  
5T9304 DATA SHEET  
Test Circuit for DC Outputs and Power Down Tests  
VDD  
A
A
Qn  
Qn  
Pulse  
Generator  
RL  
RL  
D.U.T.  
VOS  
VOD  
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing  
VDD/2  
SCOPE  
CL  
Z = 50Ω  
A
A
Qn  
Qn  
Pulse  
Generator  
50Ω  
50Ω  
D.U.T.  
Z = 50Ω  
CL  
-VDD/2  
Table 6B. Differential Input Test Conditions  
Symbol  
VDD = 2.5V 0.2V  
Unit  
pF  
pF  
0(1)  
8(1,2)  
50  
CL  
RL  
NOTE 1: Specifications only apply to “Normal Operations” test condition. The TIA/EIA specification load is for reference only.  
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA – 644 specifies 5pF between the output pair.  
With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.  
Rev A 5/13/15  
12  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5T9304 DATA SHEET  
Package Outline and Package Dimensions  
Package Outline - G Suffix for 24 Lead TSSOP  
Table 7. Package Dimensions  
All Dimensions in Millimeters  
Symbol  
Minimum  
Maximum  
N
A
24  
1.20  
0.15  
1.05  
0.30  
0.20  
7.90  
A1  
A2  
b
0.5  
0.80  
0.19  
0.09  
7.70  
c
D
E
6.40 Basic  
E1  
e
4.30  
4.50  
0.65 Basic  
L
0.45  
0°  
0.75  
8°  
aaa  
0.10  
Reference Document: JEDEC Publication 95, MO-153  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
13  
Rev A 5/13/15  
5T9304 DATA SHEET  
Ordering Information  
Table 8. Ordering Information  
XXXXX  
XX  
X
Device Type  
Package  
Process  
0°C to + 70°C (Commercial)  
TSSOP - Green  
PGG  
2.5V LVDS 1:4 Glitchless Clock Buffer  
5T9304  
Terabuffer™ II  
Rev A 5/13/15  
14  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
5T9304 DATA SHEET  
Revision History Sheet  
Rev  
Table  
Page  
1
Description of Change  
Date  
A
Not Recommended For New Designs  
5/16/13  
T8  
T8  
14  
Ordering Information - Removed Leaded Devices PDN N-13-11  
Updated data sheet format  
A
A
3/11/15  
5/13/15  
14  
Ordering Information - Corrected Commercial temperature.  
Removed NRND from the data sheet.  
LVDS, 1:4 CLOCK BUFFER TERABUFFER™  
15  
Rev A 5/13/15  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Tech Support  
email: clocks@idt.com  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or  
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as  
those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any  
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.  
厂商 型号 描述 页数 下载

IDT

 		5T9010BBGI8 [ PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, LEAD FREE, PLASTIC, BGA-144 ] 25 页

IDT

 		5T9050PGI [ Low Skew Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, TSSOP-28 ] 7 页

IDT

 		5T905PGI [ Low Skew Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, TSSOP-28 ] 17 页

IDT

 		5T9070PAGI8 [ Low Skew Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, GREEN, TSSOP-48 ] 9 页

IDT

 		5T9070PAI [ Clock Driver, CMOS, PDSO48 ] 9 页

IDT

 		5T9070PAI8 [ Clock Driver, CMOS, PDSO48 ] 9 页

IDT

 		5T907PAI [ Clock Driver, 5T Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO48, TSSOP-48 ] 19 页

IDT

 		5T907PAI8 [ Clock Driver, PDSO48 ] 19 页

IDT

 		5T9110BBGI8 [ PLL Based Clock Driver, 5T Series, 5 True Output(s), 0 Inverted Output(s), PBGA144, GREEN, PLASTIC, BGA-144 ] 23 页

IDT

 		5T915PAI [ Clock Driver, CMOS, PDSO48 ] 19 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.243304s