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5T9110BBGI8

型号：

5T9110BBGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

23 页

PDF大小：

171 K

下载PDF手册
IDT5T9110  
2.5V PROGRAMMABLE SKEW  
PLL DIFFERENTIAL CLOCK  
DRIVER TERACLOCK™  
FEATURES:  
DESCRIPTION:  
• 2.5VDD  
The IDT5T9110is a 2.5VPLLdifferentialclockdriverintendedforhigh  
performance computing and data-communications applications. A key  
featureoftheprogrammableskewis theabilityofoutputs toleadorlagthe  
REFinputsignal.TheIDT5T9110has sixdifferentialprogrammableskew  
outputs insixbanks,includinga dedicateddifferentialfeedback.Skewis  
controlledby3-levelinputsignals thatmaybe hard-wiredtoappropriate  
high-mid-lowlevels. The redundantinputcapabilityallows fora smooth  
change overtoa secondaryclocksource whenthe primaryclocksource  
isabsent.  
• 6 pairs of programmable skew outputs  
• Low skew: 100ps all outputs  
• Selectable positive or negative edge synchronization  
• Tolerant to spread spectrum input clock  
• Synchronous output enable  
• Selectable reference input  
• Input frequency: 4.17MHz to 250MHz  
• Output frequency: 12.5MHz to 250MHz  
• 1.8V / 2.5V LVTTL: up to 250MHz  
• HSTL / eHSTL: up to 250MHz  
• Hot insertable and over-voltage tolerant inputs  
• 3-level inputs for skew control  
• 3-level inputs for selectable interface  
• 3-level inputs for divide selection multiply/divide ratios of (1-6, 8,  
10, 12) / (2, 4)  
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input  
interface  
• Selectable differential or single-ended inputs and six differential  
outputs  
The feedbackbankallows divide-by-functionalityfrom1to12through  
the use of the DS[1:0] inputs. This provides the user with frequency  
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput  
bank also allows for a divide-by functionality of 2 or 4.  
The IDT5T9110 features a user-selectable, single-ended or differential  
input to six differential outputs. The differential clock driver also acts as a  
translatorfromadifferentialHSTL,eHSTL,1.8V/2.5VLVTTL,LVEPECL,or  
single-ended1.8V/2.5VLVTTLinputtoHSTL,eHSTL,or1.8V/2.5VLVTTL  
outputs. Selectableinterfaceiscontrolledby3-levelinputsignalsthatmaybe  
hard-wiredtoappropriatehigh-mid-lowlevels. Thedifferentialoutputscanbe  
synchronouslyenabled/disabled.  
• PLL bypass for DC testing  
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith  
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs  
are synchronized with the negative edge of REF.  
• External differential feedback, internal loop filter  
• Low Jitter: <75ps cycle-to-cycle  
• Power-down mode  
• Lock indicator  
• Available in BGA package  
TxS  
FUNCTIONALBLOCKDIAGRAM  
1sOE  
1Q  
OMODE  
Skew  
Select  
1Q  
3
3
3
3
3
1F2:0  
2sOE  
3sOE  
2Q  
2Q  
PD PE FS LOCK  
Skew  
Select  
PLL_EN  
3
FB  
/N  
2F2:0  
3
3
FB/  
VREF2  
3Q  
3Q  
DS1:0  
Skew  
Select  
PLL  
3
3
3
3
3
3
3
0
1
REF0  
3F2:0  
4sOE  
5sOE  
REF0/  
VREF0  
0
1
4Q  
4Q  
Skew  
Select  
RxS  
3
4F2:0  
REF1  
REF1/  
VREF1  
REF_SEL  
Skew  
Select  
5Q  
5Q  
3
5F2:0  
QFB  
QFB  
Skew  
Select  
3
3
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
FBF2:0  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC 5975/23  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
2
4
6
8
11  
1
3
5
7
9
10  
12  
1Q  
GND  
GND  
2Q  
2Q  
2sOE  
2F2  
VDD  
1F2  
1sOE  
1Q  
VDDQ  
A
B
A
B
VDD  
VDD  
VDD  
1F0  
1F1  
GND  
GND  
2F1  
2F0  
VDDQ  
VDDQ  
VDDQ  
3F2  
OMODE VDD  
VDD  
VDD  
VDD  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
3F0  
3sOE  
3Q  
C
D
E
F
C
D
E
F
REF_  
VDD  
VDD  
VDD  
VDD  
GND  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
SEL  
REF1  
REF1  
NC  
3F1  
3Q  
/VREF1  
REF0  
REF0  
VDD  
VDDQ  
VDDQ  
/VREF0  
FB  
FB  
VDD  
VDD  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
4Q  
G
H
G
H
/VREF2  
PLL_  
PD  
EN  
PE  
VDD  
VDD  
FS  
VDD  
VDD  
GND  
GND  
GND  
FBF1  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
5F0  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
4F1  
4F0  
GND  
GND  
GND  
5F1  
RxS  
LOCK  
VDD  
TxS  
VDD  
VDD  
4Q  
J
J
K
K
VDD  
VDDQ  
VDDQ  
4sOE  
4F2  
L
FBF0  
L
DS1  
FBF2  
QFB  
QFB  
GND  
GND  
5Q  
5Q  
5sOE  
5F2  
VDDQ  
M
DS0  
M
1
3
4
5
6
7
8
9
10  
11  
12  
2
2
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
ABSOLUTEMAXIMUMRATINGS(1)  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
Parameter Description  
Min.  
2.5  
Typ. Max.  
Unit  
pF  
Symbol  
Description  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDDQ +0.5  
–0.5 to +3.6  
150  
Unit  
V
VDDQ, VDD Power Supply Voltage(2)  
CIN  
InputCapacitance  
OutputCapacitance  
3
3.5  
7
VI  
Input Voltage  
V
COUT  
—
6.3  
pF  
VO  
Output Voltage  
V
NOTE:  
1. Capacitance applies to all inputs except RxS, TxS, nF[2:0], FBF[2:0].and DS[1:0].  
VREF  
TJ  
Reference Voltage(3)  
Junction Temperature  
Storage Temperature  
V
° C  
° C  
TSTG  
–65 to +165  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. VDDQ and VDD internally operate independently. No power sequencing requirements  
need to be met.  
3. Not to exceed 3.6V.  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
2.3  
Typ.  
+25  
2.5  
Max.  
+85  
2.7  
Unit  
° C  
V
TA  
AmbientOperatingTemperature  
InternalPowerSupplyVoltage  
(1)  
VDD  
HSTLOutputPowerSupplyVoltage  
ExtendedHSTLand1.8VLVTTLOutputPowerSupplyVoltage  
1.4  
1.65  
1.5  
1.8  
1.6  
1.95  
V
V
(1)  
VDDQ  
2.5VLVTTLOutputPowerSupplyVoltage  
TerminationVoltage  
VDD  
V
V
VT  
VDDQ / 2  
NOTE:  
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.  
PINDESCRIPTION  
Symbol  
I/O  
Type  
Description  
REF[1:0]  
I
I
Adjustable(1) Clockinput. REF[1:0] is the"true"sideofthedifferentialclockinput. Ifoperatinginsingle-endedmode,REF[1:0] is theclockinput.  
Adjustable(1)  
REF[1:0]/  
VREF[1:0]  
Complementaryclockinput. REF[1:0]/VREF[1:0]isthe"complementary"sideofREF[1:0] iftheinputisindifferentialmode. Ifoperating  
insingle-endedmode,REF[1:0]/VREF[1:0]isleftfloating. Forsingle-endedoperationindifferentialmode,REF[1:0]/VREF[1:0]shouldbeset  
tothedesiredtogglevoltageforREF[1:0]:  
2.5VLVTTL  
1.8VLVTTL,eHSTL  
HSTL  
VREF =1250mV(SSTL2compatible)  
VREF = 900mV  
VREF = 750mV  
LVEPECL  
VREF = 1082mV  
FB  
I
I
Adjustable(1) Clockinput. FBisthe"true"sideofthedifferentialfeedbackclockinput. Ifoperatinginsingle-endedmode,FBisthedifferentialfeedback  
clockinput.  
FB/VREF2  
Adjustable(1) Complementaryfeedbackclockinput. FB/VREF2isthe"complementary"sideofFBiftheinputisindifferentialmode. Ifoperatinginsingle-  
endedmode,FB/VREF2isleftfloating. Forsingle-endedoperationindifferentialmode, FB/VREF2shouldbesettothedesiredtogglevoltage  
for FB:  
2.5VLVTTL  
1.8VLVTTL,eHSTL  
HSTL  
VREF =1250mV(SSTL2compatible)  
VREF = 900mV  
VREF = 750mV  
LVEPECL  
VREF = 1082mV  
NOTE:  
1. Inputs are capable of translating the following interface standards. User can select between:  
Single-ended 2.5V LVTTL levels  
Single-ended 1.8V LVTTL levels  
or  
Differential 2.5V/1.8V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL levels  
3
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
PINDESCRIPTION,CONTINUED  
Symbol  
REF_SEL  
nsOE  
I/O  
Type  
Description  
(1)  
I
I
LVTTL  
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.  
(1)  
LVTTL  
Synchronousoutputenable. WhennsOEisHIGH,nQandnQaresynchronouslystopped. OMODEselectswhethertheoutputsare  
gatedLOW/HIGHortri-stated. WhenOMODEisHIGH,PEdeterminesthelevelatwhichtheoutputsstop. WhenPEisLOW/HIGH,  
the nQ is stopped in a HIGH/LOW state, while the nQ is stopped at a LOW/HIGH state. When OMODE is LOW, the outputs are tri-  
stated. SetnsOELOWfornormaloperation.  
QFB  
QFB  
nQ  
O
O
O
O
I
Adjustable(2) Feedbackclockoutput  
Adjustable(2) Complementaryfeedbackclockoutput  
Adjustable(2) Clockoutputs  
nQ  
RxS  
Adjustable(2) Complementaryclockoutputs  
(3)  
3-Level  
Selects single-ended2.5VLVTTL(HIGH), 1.8VLVTTL(MID)REFclockinputordifferential(LOW)REFclockinput  
(3)  
TxS  
I
3-Level  
Setsthedrivestrengthoftheoutputdriversandfeedbackinputstobe2.5VLVTTL(HIGH),1.8VLVTTL(MID)oreHSTL/HSTL(LOW)  
compatible. UsedinconjuctionwithVDDQ tosettheinterfacelevels.  
(1)  
PE  
I
LVTTL  
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference  
clock(hasinternalpull-up).  
(3)  
nF[2:0]  
FBF[2:0]  
FS  
I
I
I
I
I
I
3-Level  
3-levelinputsforselecting1of18skewtapsorfrequencyfunctions(SeeControlSummarytable)  
3-levelinputsforselecting1of18skewtapsorfrequencyfunctions(SeeControlSummarytable)  
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange(SeeProgrammableSkewRangetable)  
3-levelinputsforfeedbackinputdividerselection(SeeDivideSelectiontable)  
(3)  
3-Level  
LVTTL  
(3)  
DS[1:0]  
PLL_EN  
PD  
3-Level  
(1)  
LVTTL  
PLLenable/disablecontrol. SetLOWfornormaloperation. WhenPLL_ENisHIGH,thePLLisdisabledandREF[1:0]goestoalloutputs.  
(1)  
LVTTL  
Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs  
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/  
HIGH,thenQandQFBarestoppedinaHIGH/LOWstate,whilethenQandQFBarestoppedinaLOW/HIGHstate. WhenOMODE  
is LOW, the outputs are tri-stated. SetPD HIGHfornormaloperation.  
LOCK  
OMODE  
VDDQ  
O
I
LVTTL  
PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtothe  
inputs. (FormoreinformationonapplicationspecificuseoftheLOCKpin,pleaseseeAN237.)  
Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/Disableand  
Powerdowntables.)  
(1)  
LVTTL  
PWR  
Powersupplyforoutputbuffers. Whenusing2.5VLVTTL,VDDQshouldbeconnectedtoVDD.  
VDD  
GND  
PWR  
PWR  
Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry  
Ground  
NOTES:  
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept the 1.8V LVTTL signals as  
well.  
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.  
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.  
OUTPUTENABLE/DISABLE  
POWERDOWN  
nsOE  
L
OMODE  
Output  
NormalOperation  
Tri-State  
PD  
H
L
OMODE  
Output  
NormalOperation  
Tri-State  
X
L
X
L
H
(1)  
H
H
Gated  
L
H
Gated(1)  
NOTE:  
NOTE:  
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ 1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ  
is stopped in a HIGH/LOW state while the nQ is stopped at a LOW/HIGH state.  
and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a  
LOW/HIGH state.  
4
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
PROGRAMMABLESKEW  
Output skew with respect to the REF[1:0] and REF[1:0]/VREF[1:0] input is nF[2:0]/FBF[2:0] control pins. In order to minimize the number of control  
adjustable to compensate for PCB trace delays, backplane propagation pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for  
delays or to accommodate requirements for special timing relationships but not restricted to hard-wiring. Undriven 3-level inputs default to the  
between clocked components. Skew is selectable as a multiple of a time MID level. The Control Summary Table shows how to select specific  
unit (tU) which ranges from 250ps to 1.25ns (see Programmable Skew skew taps by using the nF[2:0]/FBF[2:0] control pins.  
Range and Resolution Table). There are 18 skew/divide configurations  
available for each output pair. These configurations are chosen by the  
EXTERNALDIFFERENTIALFEEDBACK  
By providing a dedicated external differential feedback, the IDT5T9110  
gives users flexibility with regard to skew adjustment. The FB and FB/  
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]  
signals at the phase detector in order to drive the VCO. Phase differ-  
ences cause the VCO of the PLL to adjust upwards or downwards  
accordingly.  
An internal loop filter moderates the response of the VCO to the  
phase detector. The loop filter transfer function has been chosen to  
provide minimal jitter (or frequency variation) while still providing accu-  
rate responses to input frequency changes.  
PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE  
FS = LOW  
1/(16 x FNOM)  
50 to 125MHz  
FS = HIGH  
1/(16 x FNOM)  
100 to 250MHz  
Comments  
TimingUnitCalculation(tU)  
VCOFrequencyRange(FNOM)(1,2)  
SkewAdjustmentRange(3)  
MaxAdjustment:  
±8.75ns  
±157.5°  
±43.75%  
tU =1.25ns  
tU =0.833ns  
tU =0.625ns  
—
±4.375ns  
±157.5°  
ns  
PhaseDegrees  
% of Cycle Time  
±43.75%  
—
Example 1, FNOM = 50MHz  
Example 2, FNOM = 75MHz  
Example 3, FNOM = 100MHz  
Example 4, FNOM = 150MHz  
Example 5, FNOM = 200MHz  
Example 6, FNOM = 250MHz  
—
tU =0.625ns  
tU =0.417ns  
tU =0.313ns  
tU =0.25ns  
—
—
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at nQ and nQ outputs  
when they are operated in their undivided modes. The frequency appearing at the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and  
QFB are undivided and DS[1:0] = MM. The frequency of the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM /2 or FNOM /4 when the part is configured  
for frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM. Using the DS[1:0] inputs allows a different method for frequency multiplication (see Divide  
Selection Table).  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed QFB and QFB output is used for feedback, then adjustment range will be greater.  
For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’  
range applies to all output pairs where ±7tU skew adjustment is possible and at the lowest FNOM value.  
5
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DIVIDESELECTIONTABLE  
(1)  
DS[1:0]  
LL  
Divide-by-n  
Permitted Output Divide-by-n connected to FB and FB/VREF2  
2
3
1, 2  
1
LM  
LH  
4
1, 2  
1, 2  
1, 2, 4  
1, 2  
1
ML  
5
MM  
MH  
HL  
1
6
8
HM  
HH  
10  
12  
1
1
NOTE:  
1. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF[1:0]/VREF[1:0] inputs will be FNOM/N when the parts are configured for  
frequency multiplication by using an undivided output for FB and FB/VREF2 and setting DS[1:0] to N (N = 1-6, 8, 10, 12).  
CONTROLSUMMARYTABLEFORALLOUTPUTS(1)  
nF2/FBF2  
nF1/FBF1  
nF0/FBF0  
Output Skew  
Divide by 2  
+7tU  
L
L
L
L
L
M
H
L
L
L
+6tU  
L
M
M
M
H
H
H
L
+5tU  
L
M
H
L
+4tU  
L
+3tU  
L
+2tU  
L
M
H
L
+1tU  
L
ZeroSkew  
Inverted  
-1tU  
H
H
H
H
H
H
H
H
H
L
M
H
L
L
-2tU  
M
M
M
H
H
H
-3tU  
M
H
L
-4tU  
-5tU  
-6tU  
M
H
-7tU  
Divide by 4  
NOTE:  
1. When PLL_EN is HIGH, the PLL is disabled and the device is put into test mode. In test mode, 5F[2:0] must be set to MHL, the REF[1:0]/REF[1:0] input frequency must be set  
to 1MHz or less, and nF[2:0]/FBF[2:0] pins should be set to LHH.  
6
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INPUT/OUTPUTSELECTION(1)  
Input  
Output  
Input  
Output  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
eHSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
2.5VLVTTL  
HSTL DSE  
HSTL DSE  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
HSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
1.8VLVTTL  
HSTL DSE  
HSTL DSE  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
2.5VLVTTLDIF  
1.8VLVTTLDIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
NOTE:  
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the  
REF[1:0]/VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2. Differential  
(DIF) inputs are used only in differential mode.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIHH  
Parameter  
Test Conditions  
Min.  
Max  
Unit  
V
(1)  
Input HIGH Voltage Level  
3-Level Inputs Only  
3-Level Inputs Only  
3-Level Inputs Only  
VIN = VDD  
VDD – 0.4  
—
(1)  
VIMM  
InputMIDVoltage Level  
VDD/2 – 0.2 VDD/2 + 0.2  
V
(1)  
VILL  
InputLOWVoltageLevel  
—
—
0.4  
200  
+50  
—
V
HIGH Level  
MID Level  
LOW Level  
I3  
3-LevelInputDCCurrent  
VIN = VDD/2  
–50  
–200  
μA  
μA  
(RxS, TxS, nF[2:0], FBF[2:0], DS[1:0])  
VIN = GND  
IPU  
Input Pull-Up Current (PE)  
VDD = Max., VIN = GND  
–100  
—
NOTE:  
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,  
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.  
7
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORHSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
VIK  
ClampDiodeVoltage  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
V
680  
750  
750  
900  
mV  
mV  
mV  
mV  
(4,5,8)  
DC Input HIGH  
VREF + 100  
—
—
(4,6,8)  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(4,8)  
—
OutputCharacteristics  
VOH  
VOL  
VOX  
OutputHIGHVoltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
V
V
—
0.4  
OutputLOWVoltage  
IOL = 100μA  
—
0.1  
FB/FB OutputCrossingPoint  
VDDQ/2 - 150  
VDDQ/2  
VDDQ/2 + 150  
mV  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
0.75  
50  
μA  
IDDPD  
Power Down Current  
1.7  
19  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
18  
30  
μA/MHz  
mA  
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF  
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF  
115  
150  
45  
170  
225  
70  
(4)  
ITOTQ  
Total Power VDDQ Supply Current  
mA  
100  
150  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
8
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
V
InputSignalSwing(1)  
1
VX  
DifferentialInputSignalCrossingPoint(2)  
750  
CrossingPoint  
1
mV  
V
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
tR,tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOReHSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
VIK  
VIN  
VDIF  
VCM  
VIH  
VIL  
ClampDiodeVoltage  
DCInputVoltage  
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
—
V
- 0.3  
0.2  
V
V
800  
900  
900  
1000  
—
mV  
mV  
mV  
mV  
(4,5,8)  
DC Input HIGH  
VREF + 100  
—
(4,6,8)  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(4,8)  
—
OutputCharacteristics  
VOH  
VOL  
VOX  
OutputHIGHVoltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
V
V
—
0.4  
OutputLOWVoltage  
V
IOL = 100μA  
—
0.1  
V
FB/FB OutputCrossingPoint  
VDDQ/2 - 150  
VDDQ/2  
VDDQ/2 + 150  
mV  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
9
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
(3)  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
1.8  
50  
μA  
IDDPD  
Power Down Current  
1.7  
19  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
20  
30  
μA/MHz  
mA  
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF  
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF  
115  
150  
55  
170  
225  
80  
ITOTQ  
Total Power VDDQ Supply Current(4)  
mA  
140  
210  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
InputSignalSwing(1)  
1
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
900  
CrossingPoint  
1
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
tR,tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
10  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR  
LVEPECL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
VIK  
VIN  
VCM  
VREF  
VIH  
VIL  
ClampDiodeVoltage  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
—
- 1.2  
3.6  
V
DCInputVoltage  
- 0.3  
915  
—
V
DC Common Mode Input Voltage(3,5)  
Single-EndedReferenceVoltage(4,5)  
DC Input HIGH  
1082  
1082  
—
1248  
—
mV  
mV  
mV  
mV  
1275  
555  
1620  
875  
DC Input LOW  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, +25°C ambient.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
DIFFERENTIALINPUTACTESTCONDITIONSFORLVEPECL  
Symbol  
VDIF  
Parameter  
Value  
Units  
mV  
mV  
V
InputSignalSwing(1)  
732  
(2)  
VX  
DifferentialInputSignalCrossingPoint  
1082  
CrossingPoint  
1
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
tR,tF  
V/ns  
NOTES:  
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
11  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR2.5V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
InputLOWCurrent  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
V
V
- 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.7  
—
—
V
V
VIL  
0.7  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
0.2  
1150  
—
1350  
V
1250  
1250  
mV  
mV  
mV  
mV  
(5,6,9)  
DC Input HIGH  
VREF + 100  
—
—
(5,7,9)  
VIL  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(5,9)  
—
OutputCharacteristics  
VOH  
VOL  
OutputHIGHVoltage  
IOH = -12mA  
IOH = -100μA  
IOL = 12mA  
IOL = 100μA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
0.4  
0.1  
V
V
V
V
OutputLOWVoltage  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and REF[1:0]/VREF[1:0] is left floating. If TxS is HIGH, FB/VREF2 should be left floating.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
12  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
POWERSUPPLYCHARACTERISTICSFOR2.5VLVTTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
10  
50  
μA  
IDDPD  
Power Down Current  
1.7  
21  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
33  
40  
μA/MHz  
mA  
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF  
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF  
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF  
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF  
115  
155  
80  
170  
230  
120  
350  
(4)  
ITOTQ  
Total Power VDDQ Supply Current  
mA  
235  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDD  
Units  
InputSignalSwing(1)  
V
V
(2)  
VX  
DifferentialInputSignalCrossingPoint  
VDD/2  
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
CrossingPoint  
2.5  
V
tR,tF  
V/ns  
NOTES:  
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF  
(AC) specification under actual use conditions.  
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDD  
0
Units  
V
Input HIGH Voltage  
InputLOWVoltage  
VIL  
V
(1)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(2)  
VDD/2  
2
V
tR,tF  
V/ns  
NOTES:  
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
13  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR1.8V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
InputLOWCurrent  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
V
V
- 0.3  
VDDQ + 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.073(10)  
—
—
0.683(11)  
V
V
VIL  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
0.2  
825  
—
975  
V
900  
900  
mV  
mV  
mV  
mV  
(5,6,9)  
DC Input HIGH  
VREF + 100  
—
—
(5,7,9)  
VIL  
DC Input LOW  
VREF - 100  
—
VREF  
Single-EndedReferenceVoltage(5,9)  
—
OutputCharacteristics  
VOH  
VOL  
OutputHIGHVoltage  
IOH = -6mA  
IOH = -100μA  
IOL = 6mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
0.4  
0.1  
V
V
V
V
OutputLOWVoltage  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and REF[1:0]/VREF[1:0] is left floating. If TxS is MID, FB/VREF2 should be left floating.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]  
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range  
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.  
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.  
14  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
POWERSUPPLYCHARACTERISTICSFOR1.8VLVTTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
1.8  
50  
μA  
IDDPD  
Power Down Current  
1.7  
22  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
23  
30  
μA/MHz  
mA  
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF  
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF  
120  
160  
55  
180  
240  
80  
ITOTQ  
Total Power VDDQ Supply Current(4)  
mA  
165  
250  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDDI  
Units  
InputSignalSwing(1)  
V
mV  
V
(2)  
VX  
DifferentialInputSignalCrossingPoint  
VDDI/2  
(3)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(4)  
CrossingPoint  
1.8  
tR,tF  
V/ns  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable  
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.  
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDDI  
0
Units  
V
Input HIGH Voltage(1)  
VIL  
InputLOWVoltage  
V
(2)  
VTHI  
InputTimingMeasurementReferenceLevel  
InputSignalEdgeRate(3)  
VDDI/2  
2
mV  
V/ns  
tR,tF  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.  
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
15  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
FNOM  
tRPW  
Parameter  
Min.  
Typ.  
Max  
Unit  
VCO Frequency Range  
seeProgrammableSkewandResolutionTable  
Reference Clock Pulse Width HIGH or LOW  
Feedback Input Pulse Width HIGH or LOW  
ProgrammableSkewTimeUnit  
1
1
—
—
—
—
ns  
ns  
tFPW  
tU  
seeControlSummaryTable  
tSK(O)  
tSK1(ω)  
tSK2(ω)  
tSK1(INV)  
tSK2(INV)  
tSK(PR)  
t(φ)  
OutputSkew(Rise-Rise,Fall-Fall,Nominal)(1,2)  
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,2,3)  
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,2,3)  
InvertingSkew(Nominal-Inverted)(1,2)  
—
—
—
—
—
—
-100  
-375  
-275  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50  
100  
100  
300  
300  
300  
300  
100  
375  
275  
1.2  
1
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,2,3)  
(1,2,4)  
Process Skew  
REFInputtoFBStaticPhase Offset(5)  
(11,12)  
tODCV  
Output Duty Cycle Variation from 50%  
1.8VLVTTL  
2.5VLVTTL  
tORISE  
tOFALL  
OutputRiseTime(6)  
HSTL / eHSTL / 1.8V LVTTL  
2.5VLVTTL  
ns  
ns  
OutputFallTime(6)  
HSTL / eHSTL / 1.8V LVTTL  
2.5VLVTTL  
1.2  
1
tL  
Power-upPLLLockTime(7)  
1
ms  
ms  
ms  
μs  
ms  
ps  
tL(ω)  
tL(PD)  
PLLLockTimeAfterInputFrequencyChange(7)  
PLL Lock Time After Asserting PD Pin(7)  
1
1
(7,9)  
tL(REFSEL1)  
tL(REFSEL2)  
tJIT(CC)  
tJIT(PER)  
PLL Lock Time After Change in REF_SEL  
100  
1
PLLLockTimeAfterChangeinREF_SEL(REF1 andREF0aredifferentfrequency)(7)  
Cycle-to-CycleOutputJitter(peak-to-peak)(2,8)  
75  
(2,8)  
PeriodJitter(peak-to-peak)  
—
—
—
75  
ps  
tJIT(HP)  
tJIT(DUTY)  
VOX  
HalfPeriodJitter(peak-to-peak)(2,8,10)  
DutyCycleJitter(peak-to-peak)(2,8)  
125  
100  
ps  
ps  
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel  
VDDQ/2 - 150 VDDQ/2 VDDQ/2 + 150 mV  
NOTES:  
1. Skew is the time between the earliest and latest output transition among all outputs for which the same tU delay has been selected, when all outputs are loaded with the specified  
load.  
2. For differential LVTTL outputs, the measurement is made at VDDQ/2, where the true outputs are only compared with other true outputs and the complementary outputs are only  
compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (VOX) of the true and complementary signals.  
3. There are three classes of outputs: nominal (multiple of tU delay), inverted, and divided (divide-by-2 or divide-by-4 mode).  
4. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.).  
5. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken from VTHI on REF to VTHI on  
FB. For TxS/RxS = LOW, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to 0tU, FB input divider is set to divide-  
by-one, and FS = HIGH.  
6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.  
7. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQ is stable and  
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified  
limits.  
8. The jitter parameters are measured with all outputs selected for 0tU, FB input divider is set to divide-by-one, and FS = HIGH.  
9. Both REF inputs must be the same frequency, but up to ±180° out of phase.  
10. For HSTL/eHSTL outputs only.  
11. For LVTTL outputs only.  
12. tODCV is measured with all outputs selected for zero delay.  
16  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
ACDIFFERENTIALINPUTSPECIFICATIONS(1)  
Symbol  
Parameter  
Min.  
1
Typ.  
—
Max  
—
Unit  
(2)  
tW  
Reference/FeedbackInputClockPulseWidthHIGHorLOW(HSTL/eHSTLoutputs)  
Reference/FeedbackInputClockPulse WidthHIGHorLOW(2.5V/1.8VLVTTLoutputs)  
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL  
ns  
(2)  
1
—
—
VDIF  
VIH  
ACDifferentialVoltage(3)  
400  
Vx + 200  
—
—
—
—
—
—
mV  
mV  
mV  
(4,5)  
AC Input HIGH  
(4,6)  
VIL  
AC Input LOW  
Vx - 200  
LVEPECL  
VDIF  
ACDifferentialVoltage(3)  
400  
1275  
—
—
—
—
—
—
mV  
mV  
mV  
(4)  
VIH  
AC Input HIGH  
(4)  
VIL  
AC Input LOW  
875  
NOTES:  
1. For differential input mode, RxS is tied to GND.  
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined  
by VDIF has been met or exceeded.  
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.  
The AC differential voltage must be achieved to guarantee switching to a new state.  
4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range.  
5. Voltage required to switch to a logic HIGH, single-ended operation only.  
6. Voltage required to switch to a logic LOW, single-ended operation only.  
17  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
AC TIMING DIAGRAM  
tRPWL  
tRPWH  
REF  
REF  
tFPWH  
tFPWL  
FB  
FB  
tODCV  
tODCV  
Q
Q
tSK(O)  
tSK(O)  
OTHER Q  
OTHER Q  
tSK1(INV)  
tSK1(INV)  
INVERTED Q  
INVERTED Q  
tSK2(ω),  
tSK2(INV)  
tSK2(INV)  
tSK2(ω)  
tSK1(ω)  
Q DIVIDED BY 2  
Q DIVIDED BY 2  
tSK1(ω),  
tSK2(INV)  
Q DIVIDED BY 4  
Q DIVIDED BY 4  
NOTE:  
1. The AC TIMING DIAGRAM applies to PE = VDD. For PE = GND, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative  
edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align.  
18  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
JITTERANDOFFSETTIMINGWAVEFORMS  
nQ, QFB  
nQ, QFB  
tcycle n  
tcycle n + 1  
=
tjit(cc) tcycle n  
tcycle n+1  
Cycle-to-Cycle jitter  
REF[1:0]  
REF[1:0]  
FB  
FB  
t(Ø)n + 1  
t(Ø)n  
(N is a large number of samples)  
n = N  
1
∑
t(Ø)n  
=
t(Ø)  
N
Static Phase Offset  
NOTE:  
1. Diagram for PE = H and TxS/RxS = L.  
19  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
JITTERANDOFFSETTIMINGWAVEFORMS  
nQ, QFB  
nQ, QFB  
tW(MIN)  
tW(MAX)  
tJIT(DUTY) = tW(MAX) - tW(MIN)  
Duty-Cycle Jitter  
nQ, QFB  
nQ, QFB  
tcycle n  
nQ, QFB  
nQ, QFB  
1
f
o
1
=
tjit(per)  
tcycle n  
f
o
Period jitter  
nQ, QFB  
nQ, QFB  
thalf period n+1  
thalf period n  
nQ, QFB  
nQ, QFB  
1
f
o
1
2*f  
=
tjit(hper) thalf period n  
o
Half-Period jitter  
20  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
TESTCIRCUITSANDCONDITIONS  
VDDI  
R1  
R2  
3 inch, ~50Ω  
Transmission Line  
VIN  
VDDQ  
VDD  
VDDI  
REF[1:0]  
D.U.T.  
Pulse  
Generator  
R1  
R2  
3 inch, ~50Ω  
Transmission Line  
REF[1:0]  
VIN  
Test Circuit for Differential Input(1)  
DIFFERENTIALINPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.2V  
Unit  
R1  
100  
100  
Ω
Ω
R2  
VDDI  
VCM*2  
V
HSTL: Crossing of REF[1:0] and REF[1:0]  
eHSTL: Crossing of REF[1:0] and REF[1:0]  
LVEPECL: Crossing of REF[1:0] and REF[1:0]  
1.8V LVTTL: VDDI/2  
VTHI  
V
2.5V LVTTL: VDD/2  
NOTE:  
1. This input configuration is used for all input interfaces. For single-ended testing,  
the REF[1:0] must be left floating. For testing single-ended in differential input  
mode, the VIN should be floating.  
21  
IDT5T9110  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
VDDQ  
R1  
VDDQ  
VDD  
VDDQ  
VDDQ  
VDD  
VDDQ  
REF[1:0]  
R1  
R2  
CL  
nQ  
REF[1:0]  
VDDQ  
QFB  
R2  
CL  
R1  
R2  
CL  
D.U.T.  
D.U.T.  
R1  
R2  
nQ  
FB  
FB  
QFB  
FB  
FB  
QFB  
QFB  
CL  
SW1  
SW1  
Test Circuit for Differential Outputs  
Test Circuit for Differential Feedback  
DIFFERENTIALFEEDBACKTEST  
CONDITIONS  
DIFFERENTIALOUTPUTTEST  
CONDITIONS  
Symbol  
VDD = 2.5V ± 0.2V  
VDDQ = Interface Specified  
15  
Unit  
Symbol  
VDD = 2.5V ± 0.2V  
VDDQ = Interface Specified  
15  
Unit  
CL  
R1  
pF  
Ω
Ω
V
CL  
R1  
pF  
Ω
Ω
V
100  
100  
R2  
100  
R2  
100  
VOX  
HSTL: Crossing of QFB and QFB  
eHSTL: Crossing of QFB and QFB  
1.8V LVTTL: VDDQ/2  
2.5V LVTTL: VDDQ/2  
TxS = MID or HIGH  
TxS = LOW  
VOX  
HSTL: Crossing of nQ and nQ  
eHSTL: Crossing of nQ and nQ  
1.8V LVTTL: VDDQ/2  
2.5V LVTTL: VDDQ/2  
TxS = MID or HIGH  
TxS = LOW  
VTHO  
V
VTHO  
SW1  
V
SW1  
Open  
Open  
Closed  
Closed  
22  
IDT5T9110  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLDIFFERENTIALCLOCKDRIVER TERACLOCK  
ORDERINGINFORMATION  
X
XXXXX  
XX  
IDT  
Package Package  
Device Type  
I
-40°C to +85°C (Industrial)  
Plastic Ball Grid Array  
PBGA - Green  
BB  
BBG  
5T9110  
2.5V Programmable Skew PLL Differential  
Clock Driver Teraclock  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
clockhelp@idt.com  
www.idt.com  
23  
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