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5T907PAI8

型号：

5T907PAI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

19 页

PDF大小：

128 K

下载PDF手册
2.5V SINGLE DATA RATE  
1:10 CLOCK BUFFER  
IDT5T907  
NRND  
TERABUFFER™  
NOT RECOMMENDED FOR NEW DESIGNS  
DESCRIPTION:  
FEATURES:  
TheIDT5T9072.5Vsingledatarate(SDR)clockbufferisauser-selectable  
single-ended or differential input to ten single-ended outputs buffer built on  
advancedmetalCMOStechnology. TheSDRclockbufferfanoutfromasingle  
or differential input to ten single-ended outputs reduces the loading on the  
preceding driver and provides an efficient clock distribution network. The  
IDT5T907canactasatranslatorfromadifferentialHSTL,eHSTL,1.8V/2.5V  
LVTTL,LVEPECL,orsingle-ended1.8V/2.5VLVTTLinputtoHSTL,eHSTL,  
1.8V/2.5VLVTTLoutputs. Selectableinterfaceiscontrolledby3-levelinput  
signalsthatmaybehard-wiredtoappropriatehigh-mid-lowlevels.  
TheIDT5T907hastwooutputbanksthatcanbeasynchronouslyenabled/  
disabled. Multiple power and grounds reduce noise.  
• Guaranteed Low Skew < 125ps (max)  
• Very low duty cycle distortion  
• High speed propagation delay < 2.5ns. (max)  
• Up to 250MHz operation  
• Very low CMOS power levels  
• 1.5V VDDQ for HSTL interface  
• Hot insertable and over-voltage tolerant inputs  
• 3-level inputs for selectable interface  
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input  
interface  
• Selectable differential or single-ended inputs and ten single-  
ended outputs  
• 2.5V VDD  
• Available in TSSOP package  
• NOT RECOMMENDED FOR NEW DESIGNS  
APPLICATIONS:  
• Clock and signal distribution  
FUNCTIONALBLOCKDIAGRAM  
TxS  
GL  
G1  
OUTPUT  
CONTROL  
Q1  
OUTPUT  
CONTROL  
Q2  
OUTPUT  
CONTROL  
Q3  
RxS  
A
OUTPUT  
CONTROL  
Q4  
A/VREF  
OUTPUT  
CONTROL  
Q5  
G2  
OUTPUT  
CONTROL  
Q6  
OUTPUT  
CONTROL  
Q7  
OUTPUT  
CONTROL  
Q8  
OUTPUT  
CONTROL  
Q9  
OUTPUT  
CONTROL  
Q10  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MAY 2013  
1
© 2013 Integrated Device Technology, Inc.  
DSC-5899/23  
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
VDD  
VDDQ  
VI  
Description  
Power Supply Voltage(2)  
Output Power Supply(2)  
Input Voltage  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDDQ +0.5  
–0.5 to +3.6  
–65 to +165  
150  
Unit  
V
V
GL  
VDD  
VDD  
GND  
GND  
G1  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
VDDQ  
VDDQ  
GND  
GND  
GND  
VDDQ  
Q3  
V
2
VO  
Output Voltage(3)  
V
3
VREF  
TSTG  
TJ  
Reference Voltage(3)  
Storage Temperature  
Junction Temperature  
V
4
°C  
°C  
5
NOTES:  
6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. VDDQ and VDD internally operate independently. No power sequencing requirements  
need to be met.  
3. Not to exceed 3.6V.  
VDDQ  
Q2  
7
8
Q1  
9
Q4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
GND  
VDDQ  
Q5  
GND  
VDDQ  
A/VREF  
A
Q6  
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)  
VDDQ  
GND  
Q10  
VDDQ  
GND  
Q7  
Symbol  
Parameter  
Min  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
—
3.5  
—
pF  
NOTE:  
Q9  
Q8  
1. This parameter is measured at characterization but not tested. Capacitance applies  
to all inputs except RxS and TxS.  
VDDQ  
G2  
VDDQ  
VDDQ  
GND  
GND  
VDDQ  
GND  
TxS  
GND  
GND  
VDD  
VDD  
RxS  
TSSOP  
TOP VIEW  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
2.4  
Typ.  
+25  
2.5  
Max.  
+85  
2.6  
Unit  
°C  
V
TA  
AmbientOperatingTemperature  
InternalPowerSupplyVoltage  
(1)  
VDD  
HSTL Output Power Supply Voltage  
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage  
1.4  
1.65  
1.5  
1.8  
1.6  
1.95  
V
V
(1)  
VDDQ  
2.5VLVTTLOutputPowerSupplyVoltage  
TerminationVoltage  
VDD  
V
V
VT  
VDDQ / 2  
NOTE:  
1. All power supplies should operate in tandem; if VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at a maximum, and vice-versa.  
2
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
PINDESCRIPTION  
Symbol  
A
I/O  
Type  
Description  
I
I
Adjustable(1) Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input.  
A/VREF  
Adjustable(1) Complementaryclockinput. A/VREF isthe"complementary"sideofAiftheinputisindifferentialmode. Ifoperatinginsingle-ended  
mode,A/VREF isconnectedtoGND. Forsingle-endedoperationindifferentialmode, A/VREF shouldbesettothedesiredtoggle  
voltage for A:  
2.5VLVTTL  
VREF = 1250mV  
1.8VLVTTL,eHSTL VREF = 900mV  
HSTL  
VREF = 750mV  
VREF = 1082mV  
LVEPECL  
G1  
G2  
I
I
LVTTL(5)  
LVTTL(5)  
LVTTL(5)  
Adjustable(2) Clockoutputs  
3 Level(3)  
3 Level(3)  
Gate for outputs Q1 through Q5. When G1 is LOW, these outputs are enabled. When G1 is HIGH, these outputs are asynchro-  
nouslydisabledtotheleveldesignatedbyGL(4).  
Gate for outputs Q6 through Q10. When G2 is LOW, these outputs are enabled. When G2 is HIGH, these outputs are asynchro-  
nouslydisabledtotheleveldesignatedbyGL(4).  
GL  
Qn  
I
O
I
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.  
RxS  
TxS  
Selectssingle-ended2.5VLVTTL(HIGH),1.8VLVTTL(MID)clockinputordifferential(LOW)clockinput  
I
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in  
conjunctionwithVDDQ tosettheinterfacelevels.  
VDD  
VDDQ  
PWR  
PWR  
PWR  
Power supply for the device core and inputs  
Powersupplyforthedeviceoutputs. Whenutilizing2.5VLVTTLoutputs, VDDQ shouldbeconnectedtoVDD.  
Power supply return for all power  
GND  
NOTES:  
1. Inputs are capable of translating the following interface standards. User can select between:  
Single-ended 2.5V LVTTL levels  
Single-ended 1.8V LVTTL levels  
or  
Differential 2.5V/1.8V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL levels  
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.  
3. 3 level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant.  
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt  
pulses or be able to tolerate them in down stream circuitry.  
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.  
3
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
INPUT/OUTPUTSELECTION(1)  
Input  
Output  
Input  
Output  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
eHSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
2.5VLVTTL  
HSTL DSE  
HSTL DSE  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
HSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
1.8VLVTTL  
HSTL DSE  
HSTL DSE  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
NOTE:  
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the  
A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF. Differential (DIF) inputs are used only in  
differential mode.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIHH  
Parameter  
Test Conditions  
Min.  
Max  
Unit  
V
Input HIGH Voltage Level(1)  
Input MID Voltage Level(1)  
InputLOWVoltageLevel(1)  
3-Level Inputs Only  
3-Level Inputs Only  
3-Level Inputs Only  
VIN = VDD  
VDD – 0.4  
—
VIMM  
VDD/2 – 0.2 VDD/2 + 0.2  
V
VILL  
—
—
0.4  
200  
+50  
—
V
HIGH Level  
MID Level  
LOW Level  
I3  
3-Level Input DC Current (RxS, TxS)  
VIN = VDD/2  
–50  
–200  
μA  
VIN = GND  
NOTE:  
1. These inputs are normally wired to VDD, GND, or left floating. Internal temination resistors bias unconnected inputs to VDD/2.  
4
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(9)  
InputLOWCurrent(9)  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
±5  
±5  
μA  
—
—
VIK  
ClampDiodeVoltage  
VDD = 2.4V, IIN = -18mA  
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
DC Input HIGH(4,5,8)  
DC Input LOW(4,6,8)  
Single-EndedReferenceVoltage(4,8)  
V
680  
750  
750  
900  
mV  
mV  
mV  
mV  
VREF + 100  
—
—
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
Output HIGH Voltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
V
V
V
V
OutputLOWVoltage  
0.4  
0.1  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
20  
30  
mA  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
0.1  
20  
0.3  
30  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
30  
50  
Total Power VDD Supply Current  
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
20  
35  
35  
50  
40  
50  
ITOTQ  
Total Power VDDQ Supply Current  
70  
mA  
100  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
5
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
V
InputSignalSwing(1)  
1
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
750  
mV  
V
VTHI  
CrossingPoint  
1
tR, tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VDIF (AC) specification under actual use conditions.  
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(9)  
InputLOWCurrent(9)  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
±5  
±5  
μA  
—
—
VIK  
ClampDiodeVoltage  
VDD = 2.4V, IIN = -18mA  
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
DC Input HIGH(4,5,8)  
DC Input LOW(4,6,8)  
Single-EndedReferenceVoltage(4,8)  
V
800  
900  
900  
1000  
—
mV  
mV  
mV  
mV  
VREF + 100  
—
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
Output HIGH Voltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
V
V
V
V
OutputLOWVoltage  
0.4  
0.1  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF.  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
6
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
20  
30  
mA  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
0.1  
20  
0.3  
30  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
40  
60  
Total Power VDD Supply Current  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF  
20  
35  
40  
80  
40  
50  
ITOTQ  
Total Power VDDQ Supply Current  
80  
mA  
160  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
InputSignalSwing(1)  
1
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
900  
VTHI  
CrossingPoint  
1
tR, tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VDIF (AC) specification under actual use conditions.  
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR  
LVEPECL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(6)  
InputLOWCurrent(6)  
VDD = 2.6V  
VDD = 2.6V  
VDD = 2.4V, IIN = -18mA  
VI = VDDQ/GND  
—
—
—
—
±5  
±5  
μA  
VI = GND/VDDQ  
VIK  
ClampDiodeVoltage  
—
- 0.7  
—
- 1.2  
3.6  
V
VIN  
VCM  
VREF  
VIH  
VIL  
DCInputVoltage  
- 0.3  
915  
—
V
DC Common Mode Input Voltage(3,5)  
Single-EndedReferenceVoltage(4,5)  
DC Input HIGH  
1082  
1082  
—
1248  
—
mV  
mV  
mV  
mV  
1275  
555  
1620  
875  
DC Input LOW  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, +25°C ambient.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation while in differential mode, A/VREF is tied to the DC voltage VREF.  
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should  
be referenced.  
6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
7
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL  
Symbol  
VDIF  
Parameter  
Value  
Units  
mV  
mV  
V
InputSignalSwing(1)  
732  
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
1082  
CrossingPoint  
1
VTHI  
tR, tF  
V/ns  
NOTES:  
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet  
the VDIF (AC) specification under actual use conditions.  
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(10)  
InputLOWCurrent(10)  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
V
V
- 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.7  
—
—
V
V
VIL  
0.7  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
DC Input HIGH(5,6,9)  
DC Input LOW(5,7,9)  
Single-EndedReferenceVoltage(5,9)  
0.2  
1150  
—
1350  
V
1250  
1250  
mV  
mV  
mV  
mV  
VREF + 100  
—
—
VIL  
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
Output HIGH Voltage  
IOH = -12mA  
IOH = -100μA  
IOL = 12mA  
IOL = 100μA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
V
V
V
V
OutputLOWVoltage  
0.4  
0.1  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
8
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
20  
30  
mA  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
0.1  
25  
0.3  
40  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
40  
70  
Total Power VDD Supply Current  
VDDQ = 2.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 2.5V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
VDDQ = 2.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 2.5V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
25  
40  
40  
70  
ITOTQ  
Total Power VDDQ Supply Current  
40  
80  
mA  
100  
200  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDD  
Units  
InputSignalSwing(1)  
V
V
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
VDD/2  
VTHI  
CrossingPoint  
2.5  
V
tR, tF  
V/ns  
NOTES:  
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must  
meet the VDIF (AC) specification under actual use conditions.  
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VX specification under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDD  
0
Units  
V
Input HIGH Voltage  
VIL  
InputLOWVoltage  
V
VTHI  
InputTimingMeasurementReferenceLevel(1)  
InputSignalEdgeRate(2)  
VDD/2  
2
V
tR, tF  
V/ns  
NOTES:  
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
9
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current(12)  
InputLOWCurrent(12)  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.6V  
VDD = 2.6V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.4V, IIN = -18mA  
—
- 0.7  
- 1.2  
V
V
- 0.3  
VDDQ + 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.073(10)  
—
—
0.683(11)  
V
V
VIL  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
DC Input HIGH(5,6,9)  
DC Input LOW(5,7,9)  
Single-EndedReferenceVoltage(5,9)  
0.2  
825  
—
975  
V
900  
900  
mV  
mV  
mV  
mV  
VREF + 100  
—
—
VIL  
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
Output HIGH Voltage  
IOH = -6mA  
IOH = -100μA  
IOL = 6mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
V
V
V
V
OutputLOWVoltage  
0.4  
0.1  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is constrained within  
+600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V  
LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances.  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be  
referenced.  
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.  
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIL = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.  
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.  
10  
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDDQ = Max., Reference Clock = LOW(3)  
Outputsenabled,Alloutputsunloaded  
VDD = Max., VDDQ = Max., CL = 0pF  
20  
30  
mA  
IDDQQ  
IDDD  
IDDDQ  
ITOT  
Quiescent VDDQ Power Supply Current  
0.1  
20  
0.3  
40  
mA  
μA/MHz  
μA/MHz  
mA  
Dynamic VDD Power Supply  
CurrentperOutput  
Dynamic VDDQ Power Supply  
CurrentperOutput  
VDD = Max., VDDQ = Max., CL = 0pF  
55  
80  
Total Power VDD Supply Current  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF  
VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF  
25  
40  
40  
60  
ITOTQ  
Total Power VDDQ Supply Current  
55  
110  
260  
mA  
130  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDDI  
Units  
InputSignalSwing(1)  
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
VDDI/2  
VTHI  
CrossingPoint  
1.8  
tR, tF  
V/ns  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable  
results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions.  
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the  
VX specification under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDDI  
0
Units  
V
Input HIGH Voltage(1)  
VIL  
InputLOWVoltage  
V
VTHI  
InputTimingMeasurementReferenceLevel(2)  
InputSignalEdgeRate(3)  
VDDI/2  
2
mV  
V/ns  
tR, tF  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.  
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
11  
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(7)  
Symbol  
SkewParameters  
tSK(O)  
Parameter  
Min.  
Typ.  
Max  
Unit  
ps  
Same Device Output Pin-to-Pin Skew(1) Single-EndedandDifferentialModes  
Single-EndedinDifferentialMode(DSE)  
—
—
—
—
—
—
40  
—
—
—
125  
—
125  
—
tSK(P)(2)  
tSK(P)(4)  
Pulse Skew(3)  
Single-EndedandDifferentialModes  
Single-EndedinDifferentialMode(DSE)  
Single-EndedandDifferentialModes  
Single-EndedinDifferentialMode(DSE)  
300  
—
ps  
300  
—
Pulse Skew(3)  
350  
—
ps  
350  
—
(5)  
dT  
Duty Cycle  
60  
%
tSK(PP)  
Part-to-PartSkew(6)  
Single-EndedandDifferentialModes  
—
300  
—
ps  
Single-EndedinDifferentialMode(DSE)  
300  
PropagationDelay  
tPLH  
tPHL  
tR  
Propagation Delay A to Qn  
—
—
2.5  
ns  
ps  
Output Rise Time (20% to 80%)  
Output Fall Time (20% to 80%)  
FrequencyRange(HSTL/eHSTLoutputs)  
2.5V / 1.8V LVTTL Outputs  
HSTL / eHSTL Outputs  
2.5V / 1.8V LVTTL Outputs  
HSTL / eHSTL Outputs  
350  
350  
350  
350  
—
—
—
—
—
—
—
1050  
1350  
1050  
1350  
250  
tF  
ps  
fO  
MHz  
FrequencyRange(2.5V/1.8VLVTTLoutputs)  
OutputGateEnable/DisableDelay  
—
200  
tPGE  
tPGD  
OutputGateEnabletoQn  
OutputGateEnabletoQnDriventoGLDesignatedLevel  
—
—
—
—
3.5  
3
ns  
ns  
NOTES:  
1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device.  
2. For 1.8V LVTTL and eHSTL outputs only.  
3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load conditions on any one device.  
4. For 2.5V LVTTL outputs only.  
5. For HSTL outputs only.  
6. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD/VDDQ  
levels and temperature.  
7. Guaranteed by design.  
12  
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
ACDIFFERENTIALINPUTSPECIFICATIONS(1)  
Symbol  
Parameter  
Min.  
1.73  
2.17  
Typ.  
—
Max  
—
Unit  
t W  
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2)  
Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2)  
ns  
—
—
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL  
VDIF  
VIH  
ACDifferentialVoltage(3)  
AC Input HIGH(4,5)  
AC Input LOW(4,6)  
400  
Vx + 200  
—
—
—
—
—
—
mV  
mV  
mV  
VIL  
Vx - 200  
LVEPECL  
VDIF  
ACDifferentialVoltage(3)  
AC Input HIGH(4)  
AC Input LOW(4)  
400  
1275  
—
—
—
—
—
—
mV  
mV  
mV  
VIH  
VIL  
875  
NOTES:  
1. For differential input mode, RxS is tied to GND.  
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined  
by VDIF has been met or exceeded.  
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The  
AC differential voltage must be achieved to guarantee switching to a new state.  
4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range.  
5. Voltage required to switch to a logic HIGH, single-ended operation only.  
6. Voltage required to switch to a logic LOW, single-ended operation only.  
13  
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
AC TIMING WAVEFORMS  
tW  
tW  
VIH  
VTHI  
VIL  
A
A
VIH  
VTHI  
VIL  
tPHL  
tPLH  
VOH  
VTHO  
VOL  
Qn  
Qm  
tSK(O)  
tSK(O)  
VOH  
VTHO  
VOL  
Propagation and Skew Waveforms  
NOTES:  
1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO.  
2. Pulse Skew is calculated using the following expression:  
tSK(P) = | tPHL - tPLH |  
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not  
valid measurements for this calculation because they are not taken from the same pulse.  
VIH  
VTHI  
VIL  
A
A
VIH  
VTHI  
VIL  
VIH  
VTHI  
VIL  
GL  
Gx  
Qn  
tPLH  
VIH  
VTHI  
VIL  
tPGD  
tPGE  
VOH  
VTHO  
VOL  
Gate Disable/Enable Showing Runt Pulse Generation  
NOTE:  
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.  
14  
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
TESTCIRCUITSANDCONDITIONS  
VDDI  
R1  
3 inch, ~50  
Transmission Line  
VIN  
VDDQ  
VDD  
R2  
VDDI  
A
D.U.T.  
Pulse  
Generator  
R1  
A
3 inch, ~50  
Transmission Line  
VIN  
R2  
Test Circuit for Differential Input(1)  
DIFFERENTIALINPUTTESTCONDITIONS  
Symbol  
R1  
VDD = 2.5V ± 0.1V  
100  
Unit  
Ω
R2  
100  
Ω
VDDI  
VCM*2  
V
HSTL: Crossing of A and A  
eHSTL: Crossing of A and A  
LVEPECL: Crossing of A and A  
1.8V LVTTL: VDDI/2  
2.5V LVTTL: VDD/2  
VTHI  
V
NOTE:  
1. This input configuration is used for all input interfaces. For single-ended testing,  
the VIN input is tied to GND. For testing single-ended in differential input mode,  
the VIN is left floating.  
15  
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
VDDQ  
VDDQ  
VDD  
R1  
D.U.T.  
Qn  
R2  
CL  
Test Circuit for SDR Outputs  
SDROUTPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.1V  
Unit  
VDDQ = Interface Specified  
CL  
R1  
15  
100  
pF  
Ω
Ω
V
R2  
100  
VTHO  
VDDQ / 2  
16  
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
ORDERINGINFORMATION  
XX  
X
XXXXX  
IDT  
Package Process  
Device Type  
I
-40°C to +85°C (Industrial)  
PA  
PAG  
Thin Shrink Small Outline Package  
TSSOP - Green  
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer™  
5T907  
17  
IDT5T907  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
INDUSTRIALTEMPERATURERANGE  
REVISIONHISTORY  
Rev  
Table  
Page  
Discription of Change  
Date  
A
1
NRND - Not Recommended for New Designs  
5/5/13  
18  
IDT5T907  
INDUSTRIALTEMPERATURERANGE  
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFER  
We’ve Got Your Timing Solution.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
Sales  
Tech Support  
netcom@idt.com  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.All information  
in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express  
or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document  
is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users.Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or  
their respective third party owners.  
Copyright 2013. All rights reserved.  
19  
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