IDT5T9070
2.5VSINGLEDATARATE1:10CLOCKBUFFERTERABUFFERJR.
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
VDD = Max., Reference Clock = LOW
Outputsenabled,Alloutputsunloaded
VDD = Max., VDD = Max., CL = 0pF
1.5
2
mA
IDDD
ITOT
Dynamic VDD Power Supply
CurrentperOutput
150
200
μA/MHz
Total Power VDD Supply Current
VDD = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF
VDD = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF
70
90
mA
100
150
NOTE:
1. The termination resistors are excluded from these measurements.
INPUT AC TEST CONDITIONS
Symbol
VIH
Parameter
Value
Units
Input HIGH Voltage
VDD
0
V
V
VIL
InputLOWVoltage
VTH
InputTimingMeasurementReferenceLevel(1)
InputSignalEdgeRate(2)
VDD/2
2
V
tR, tF
V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(4)
Symbol
Parameter
Min.
Typ.
Max
Unit
SkewParameters
tSK(O)
Same Device Output Pin-to-Pin Skew(1)
Pulse Skew(2)
Part-to-PartSkew(3)
—
—
—
—
—
—
125
300
300
ps
ps
ps
tSK(P)
tSK(PP)
PropagationDelay
tPLH
tPHL
tR
Propagation Delay A to Qn
—
—
2
ns
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
FrequencyRange
350
350
—
—
—
—
850
850
200
ps
ps
tF
fO
MHz
OutputGateEnable/DisableDelay
tPGE
tPGD
OutputGateEnabletoQn
OutputGateEnabletoQnDriventoGLDesignatedLevel
—
—
—
—
3.5
3
ns
ns
NOTES:
1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device.
2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device.
3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels
and temperature.
4. Guaranteed by design.
4