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5T9010BBGI8

型号：

5T9010BBGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

25 页

PDF大小：

193 K

下载PDF手册
IDT5T9010  
2.5V PROGRAMMABLE SKEW  
PLL CLOCK DRIVER TERACLOCK™  
Product Discontinuance Notice – Last Time Buy Expires on (2/24/2014)  
FEATURES:  
DESCRIPTION:  
• 2.5VDD  
The IDT5T9010 is a 2.5V PLL clock driver intended for high perfor-  
mancecomputinganddata-communicationsapplications.Akeyfeatureof  
theprogrammableskewistheabilityofoutputstoleadorlagtheREFinput  
signal. TheIDT5T9010hastenprogrammableskewoutputsinfivebanks  
oftwo,plusadedicateddifferentialfeedback.Skewiscontrolledby3-level  
input signals that may be hard-wired to appropriate high-mid-low levels.  
The redundant input capability allows for a smooth change over to a  
secondary clock source when the primary clock source is absent.  
The feedback bank allows divide-by-functionality from 1 to 12 through  
the use of the DS[1:0] inputs. This provides the user with frequency  
multiplication1to12withoutusingdividedoutputsforfeedback. Eachoutput  
bank also allows for a divide-by-functionality of 2 or 4.  
• 5 pairs of programmable skew outputs  
• Low skew: 50ps same pair, 100ps all outputs  
• Selectable positive or negative edge synchronization  
• Tolerant of spread spectrum input clock  
• Synchronous output enable  
• Selectable reference input  
• Input frequency: 4.17MHz to 250MHz  
• Output frequency: 12.5MHz to 250MHz  
• 1.8V / 2.5V LVTTL: up to 250MHz  
• HSTL / eHSTL: up to 250MHz  
• Hot insertable and over-voltage tolerant inputs  
• 3-level inputs for skew control  
• 3-level inputs for selectable interface  
• 3-level inputs for divide selection multiply/divide ratios of  
(1-6, 8, 10, 12) / (2, 4)  
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input  
interface  
• Selectable differential or single-ended inputs and ten single-  
ended outputs  
The IDT5T9010 features a user-selectable, single-ended or differential  
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom  
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended  
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.  
Selectableinterfaceiscontrolledby3-levelinputsignalsthatmaybehard-wired  
to appropriate high-mid-low levels. The outputs can be synchronously  
enabled/disabled.  
Furthermore,whenPEisheldhigh,alltheoutputsaresynchronizedwith  
thepositiveedgeoftheREFclockinput.WhenPEisheldlow,alltheoutputs  
are synchronized with the negative edge of REF.  
• PLL bypass for DC testing  
• External differential feedback, internal loop filter  
• Low Jitter: <75ps cycle-to-cycle  
• Power-down mode  
• Lock indicator  
• Available in BGA package  
TxS  
FUNCTIONALBLOCKDIAGRAM  
1sOE  
1Q0  
Skew  
Select  
OMODE  
1Q1  
3
3
3
3
1F2:0  
2sOE  
3sOE  
2Q0  
2Q1  
PD PE FS LOCK  
Skew  
Select  
PLL_EN  
3
3
FB  
/N  
2F2:0  
3
3
FB/  
VREF2  
3Q0  
3Q1  
DS1:0  
Skew  
Select  
PLL  
3
3
3
3
3
3
3
0
1
REF0  
3F2:0  
REF0/  
VREF0  
4sOE  
0
1
4Q0  
4Q1  
Skew  
Select  
RxS  
3
REF1  
4F2:0  
5sOE  
REF1/  
VREF1  
REF_SEL  
Skew  
Select  
5Q0  
5Q1  
3
5F2:0  
Skew  
Select  
QFB  
QFB  
3
3
3
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
FBF2:0  
INDUSTRIAL TEMPERATURE RANGE  
MAY 2013  
1
c
2013 Integrated Device Technology, Inc.  
DSC 5979/23  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
PINCONFIGURATION  
2
4
6
8
11  
1
3
5
7
9
10  
12  
1Q0  
GND  
GND  
2Q1  
2Q0  
2sOE  
2F2  
VDD  
1F2  
1sOE  
1Q1  
VDDQ  
A
B
A
B
VDD  
VDD  
VDD  
1F0  
1F1  
GND  
GND  
2F1  
2F0  
VDDQ  
VDDQ  
VDDQ  
3F2  
3sOE  
OMODE VDD  
VDD  
VDD  
NC  
VDD  
VDD  
VDD  
VDD  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
3F0  
C
D
E
F
C
D
E
F
REF_  
VDD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
3Q0  
3Q1  
SEL  
REF1  
REF1  
3F1  
/VREF1  
REF0  
REF0  
VDD  
VDD  
VDDQ  
VDDQ  
/VREF0  
FB  
FB  
VDD  
GND  
GND  
GND  
GND  
FBF1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
4F1  
VDDQ  
4Q1  
G
H
G
H
/VREF2  
PLL_  
PD  
EN  
PE  
VDD  
VDD  
FS  
VDD  
VDD  
GND  
GND  
GND  
GND  
VDDQ  
VDDQ  
VDDQ  
5F0  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
GND  
GND  
GND  
5F1  
RxS  
LOCK  
VDD  
TxS  
VDD  
VDD  
4F0  
4Q0  
J
J
4sOE  
K
K
VDD  
VDDQ  
VDDQ  
L
FBF0  
4F2  
L
DS1  
FBF2  
QFB  
QFB  
GND  
GND  
5Q1  
5Q0  
5F2  
VDDQ  
M
DS0  
5sOE  
M
1
3
4
5
6
7
8
9
10  
11  
12  
2
2
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
ABSOLUTEMAXIMUMRATINGS(1)  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
Parameter Description  
Min.  
2.5  
—
Typ.  
3
Max.  
3.5  
7
Unit  
pF  
Symbol  
Description  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDDQ +0.5  
–0.5 to +3.6  
150  
Unit  
V
VDDQ, VDD Power Supply Voltage(2)  
CIN  
InputCapacitance  
OutputCapacitance  
VI  
Input Voltage  
V
COUT  
6.3  
pF  
VO  
Output Voltage  
V
NOTE:  
1. Capacitance applies to all inputs except RxS, TxS, nF[2:0], FBF[2:0], and DS[1:0].  
VREF  
TJ  
Reference Voltage(3)  
Junction Temperature  
Storage Temperature  
V
°C  
°C  
TSTG  
–65 to +165  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. VDDQ and VDD internally operate independently. No power sequencing requirements  
need to be met.  
3. Not to exceed 3.6V.  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
2.3  
Typ.  
+25  
2.5  
Max.  
+85  
2.7  
Unit  
°C  
V
TA  
AmbientOperatingTemperature  
InternalPowerSupplyVoltage  
(1)  
VDD  
HSTL Output Power Supply Voltage  
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage  
1.4  
1.65  
1.5  
1.8  
1.6  
1.95  
V
V
(1)  
VDDQ  
2.5VLVTTLOutputPowerSupplyVoltage  
TerminationVoltage  
VDD  
V
V
VT  
VDDQ / 2  
NOTE:  
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.  
PINDESCRIPTION  
Symbol  
I/O  
Type  
Description  
REF[1:0]  
I
I
Adjustable(1) Clockinput. REF[1:0] isthe"true"sideofthedifferentialclockinput. Ifoperatinginsingle-endedmode, REF[1:0] istheclockinput.  
REF[1:0]/  
VREF[1:0]  
Adjustable(1)  
Complementaryclockinput. REF[1:0]/VREF[1:0] isthe"complementary"sideofREF[1:0] iftheinputisindifferentialmode. Ifoperating  
insingle-endedmode,REF[1:0]/VREF[1:0] isleftfloating. Forsingle-endedoperationindifferentialmode,REF[1:0]/VREF[1:0]shouldbeset  
tothedesiredtogglevoltageforREF[1:0]:  
2.5VLVTTL  
1.8VLVTTL,eHSTL  
HSTL  
VREF =1250mV(SSTL2compatible)  
VREF = 900mV  
VREF = 750mV  
LVEPECL  
VREF = 1082mV  
FB  
I
I
Adjustable(1) Clockinput. FBisthe"true"sideofthedifferentialfeedbackclockinput. Ifoperatinginsingle-endedmode,FBisthefeedbackclockinput.  
FB/VREF2  
Adjustable(1) Complementaryfeedbackclockinput. FB/VREF2isthe"complementary"sideofFBiftheinputisindifferentialmode. Ifoperatinginsingle-  
endedmode,FB/VREF2isleftfloating. Forsingle-endedoperationindifferentialmode, FB/VREF2shouldbesettothedesiredtogglevoltage  
for FB:  
2.5VLVTTL  
1.8VLVTTL,eHSTL  
HSTL  
VREF =1250mV(SSTL2compatible)  
VREF = 900mV  
VREF = 750mV  
LVEPECL  
VREF = 1082mV  
NOTE:  
1. Inputs are capable of translating the following interface standards. User can select between:  
Single-ended 2.5V LVTTL levels  
Single-ended 1.8V LVTTL levels  
or  
Differential 2.5V/1.8V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL levels  
3
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
PINDESCRIPTION,CONTINUED  
Symbol  
REF_SEL  
nsOE  
I/O  
Type  
Description  
I
I
LVTTL(1)  
LVTTL(1)  
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.  
Synchronousoutputenable. WhennsOEisHIGH,nQ[1:0] aresynchronouslystopped. OMODEselectswhethertheoutputsaregated  
LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the  
nQ[1:0] is stopped in a HIGH/LOW state. When OMODE is LOW, the outputs are tri-stated. Set nsOE LOW for normal operation.  
QFB  
QFB  
nQ[1:0]  
RxS  
TxS  
O
O
O
I
Adjustable(2) Feedbackclockoutput  
Adjustable(2) Complementaryfeedbackclockoutput  
Adjustable(2) Fivebanksoftwooutputs  
3-Level(3)  
3-Level(3)  
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input  
I
Setsthedrivestrengthoftheoutputdriversandfeedbackinputstobe2.5VLVTTL(HIGH),1.8VLVTTL(MID)orHSTL/eHSTL(LOW)  
compatible. UsedinconjuctionwithVDDQ tosettheinterfacelevels.  
PE  
I
LVTTL(1)  
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthereference  
clock(hasinternalpull-up).  
nF[2:0]  
FBF[2:0]  
FS  
I
I
I
I
I
I
3-Level(3)  
3-Level(3)  
LVTTL(1)  
3-Level(3)  
LVTTL(1)  
LVTTL(1)  
3-levelinputsforselecting1to18skewtapsorfrequencyfunctions(SeeControlSummarytable)  
3-levelinputsforselecting1to18skewtapsorfrequencyfunctions(SeeControlSummarytable)  
Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange (SeeProgrammableSkewRange)  
3-levelinputsforfeedbackinputdividerselection(SeeDivideSelectiontable)  
DS[1:0]  
PLL_EN  
PD  
PLLenable/disablecontrol. SetLOWfornormaloperation. WhenPLL_ENisHIGH,thePLLisdisabledandREF[1:0]goestoalloutputs.  
Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhethertheoutputs  
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/  
HIGH, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a LOW/HIGH state. When OMODE is  
LOW, theoutputsaretri-stated. SetPDHIGHfornormaloperation.  
LOCK  
O
I
LVTTL  
PLLlockindicationsignal. HIGHindicateslock. LOWindicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtothe  
inputs. (FormoreinformationonapplicationspecificuseoftheLOCKpin, pleaseseeAN237.)  
Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/Disableand  
Powerdowntables.)  
OMODE  
LVTTL(1)  
VDDQ  
VDD  
PWR  
PWR  
PWR  
Powersupplyforoutputbuffers. Whenusing2.5VLVTTL,VDDQ shouldbeconnectedtoVDD.  
Powersupplyforphaselockedloop,lockoutput,inputs,andotherinternalcircuitry  
GND  
Ground  
NOTES:  
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept the 1.8V LVTTL signals as  
well.  
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.  
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.  
POWERDOWN  
OUTPUTENABLE/DISABLE  
PD  
H
OMODE  
Output  
NormalOperation  
Tri-State  
nsOE  
OMODE  
Output  
NormalOperation  
Tri-State  
X
L
L
H
H
X
L
L
Gated(1)  
H
Gated(1)  
L
H
NOTE:  
NOTE:  
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the  
nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a  
LOW/HIGH state.  
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the  
nQ[1:0] is stopped in a HIGH/LOW state.  
4
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
PROGRAMMABLESKEW  
Output skew with respect to the REF[1:0] and REF[1:0]/VREF[1:0] input by the nF[2:0]/FBF[2:0] control pins. In order to minimize the number of  
is adjustable to compensate for PCB trace delays, backplane propaga- control pins, 3-level inputs (HIGH-MID-LOW) are used, they are in-  
tion delays or to accommodate requirements for special timing relation- tended for but not restricted to hard-wiring. Undriven 3-level inputs  
ships between clocked components. Skew is selectable as a multiple of a default to the MID level. The Control Summary Table shows how to  
time unit (tU) which ranges from 250ps to 1.25ns (see Programmable select specific skew taps by using the nF[2:0]/FBF[2:0] control pins.  
Skew Range and Resolution Table). There are 18 skew/divide configu-  
rations available for each output pair. These configurations are chosen  
EXTERNALDIFFERENTIALFEEDBACK  
By providing a dedicated external differential feedback, the IDT5T9010  
An internal loop filter moderates the response of the VCO to the  
gives users flexibility with regard to skew adjustment. The FB and FB/ phase detector. The loop filter transfer function has been chosen to  
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0] provide minimal jitter (or frequency variation) while still providing accu-  
signals at the phase detector in order to drive the VCO. Phase differ- rate responses to input frequency changes.  
ences cause the VCO of the PLL to adjust upwards or downwards  
accordingly.  
PROGRAMMABLESKEWRANGEANDRESOLUTIONTABLE  
FS = LOW  
1/(16 x FNOM)  
50 to 125MHz  
FS = HIGH  
1/(16 x FNOM)  
100 to 250MHz  
Comments  
TimingUnitCalculation(tU)  
VCOFrequencyRange(FNOM)(1,2)  
SkewAdjustmentRange(3)  
MaxAdjustment:  
±8.75ns  
±157.5°  
±43.75%  
tU = 1.25ns  
tU =0.833ns  
tU =0.625ns  
—
±4.375ns  
±157.5°  
±43.75%  
—
ns  
PhaseDegrees  
% of Cycle Time  
Example 1, FNOM = 50MHz  
Example 2, FNOM = 75MHz  
Example 3, FNOM = 100MHz  
Example 4, FNOM = 150MHz  
Example 5, FNOM = 200MHz  
Example 6, FNOM = 250MHz  
—
tU =0.625ns  
tU =0.417ns  
tU =0.313ns  
tU = 0.25ns  
—
—
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at nQ[1:0] outputs when  
they are operated in their undivided modes. The frequency appearing at the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB  
are undivided and DS[1:0] = MM. The frequency of the REF[1:0] and REF[1:0]/VREF[1:0] and FB and FB/VREF2 inputs will be FNOM /2 or FNOM /4 when the part is configured for  
frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM. Using the DS[1:0] inputs allows a different method for frequency multiplication (see Divide  
Selection Table).  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed QFB and QFB output is used for feedback, then adjustment range will be greater.  
For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’  
range applies to all output pairs where ±7tU skew adjustment is possible and at the lowest FNOM value.  
5
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DIVIDESELECTIONTABLE  
(1)  
DS [1:0]  
LL  
Divide-by-n  
Permitted Output Divide-by-n connected to FB and FB/VREF2  
2
3
1, 2  
1
LM  
LH  
4
1, 2  
1, 2  
1, 2, 4  
1, 2  
1
ML  
5
MM  
M H  
HL  
1
6
8
H M  
H H  
10  
12  
1
1
NOTE:  
1. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF[1:0]/VREF[1:0] inputs will be FNOM/N when the parts are configured for  
frequency multiplication by using an undivided output for FB and FB/VREF2 and setting DS[1:0] to N (N = 1-6, 8, 10, 12).  
CONTROL SUMMARY TABLE FORALL OUTPUTS(1)  
nF2/FBF2  
nF1/FBF1  
nF0/FBF0  
Output Skew  
Divide by 2  
+7tU  
L
L
L
L
L
M
H
L
L
L
+6tU  
L
M
M
M
H
H
H
L
+5tU  
L
M
H
L
+4tU  
L
+3tU  
L
+2tU  
L
M
H
L
+1tU  
L
Zero Skew  
Inverted  
-1tU  
H
H
H
H
H
H
H
H
H
L
M
H
L
L
-2tU  
M
M
M
H
H
H
-3tU  
M
H
L
-4tU  
-5tU  
-6tU  
M
H
-7tU  
Divide by 4  
NOTE:  
1. When PLL_EN is HIGH, the PLL is disabled and the device is put into test mode. In test mode, 5F[2:0] must be set to MHL, the REF[1:0]/REF[1:0] input frequency must be set  
to 1MHz or less, and nF[2:0]/FBF[2:0] pins should be set to LHH.  
6
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INPUT/OUTPUTSELECTION(1)  
Input  
Output  
Input  
Output  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
eHSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
2.5VLVTTL  
HSTL DSE  
HSTL DSE  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
HSTL  
2.5V LVTTL SE  
1.8V LVTTL SE  
2.5V LVTTL DSE  
1.8V LVTTL DSE  
LVEPECL DSE  
eHSTL DSE  
1.8VLVTTL  
HSTL DSE  
HSTL DSE  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
2.5V LVTTL DIF  
1.8V LVTTL DIF  
LVEPECL DIF  
eHSTL DIF  
HSTL DIF  
HSTL DIF  
NOTE:  
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the  
REF[1:0] /VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring VREF[1:0] and VREF2. Differential  
(DIF) inputs are used only in differential mode.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
VIHH  
Parameter  
Test Conditions  
Min.  
Max  
Unit  
V
Input HIGH Voltage Level(1)  
Input MID Voltage Level(1)  
InputLOWVoltageLevel(1)  
3-Level Inputs Only  
3-Level Inputs Only  
3-Level Inputs Only  
VIN = VDD  
VDD – 0.4  
—
VIMM  
VDD/2 – 0.2 VDD/2 + 0.2  
V
VILL  
—
—
0.4  
200  
+50  
—
V
HIGH Level  
MID Level  
LOW Level  
I3  
3-LevelInputDCCurrent  
VIN = VDD/2  
–50  
–200  
–100  
μA  
μA  
(RxS, TxS, nF[2:0], FBF[2:0], DS[1:0])  
Input Pull-Up Current (PE)  
VIN = GND  
IPU  
VDD = Max., VIN = GND  
—
NOTE:  
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,  
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.  
7
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
—
—
VIK  
ClampDiodeVoltage  
VDD = 2.3V, IIN = -18mA  
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
DC Input HIGH(4,5,8)  
DC Input LOW(4,6,8)  
Single-EndedReferenceVoltage(4,8)  
V
680  
750  
750  
900  
mV  
mV  
mV  
mV  
VREF + 100  
—
—
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
VOX  
Output HIGH Voltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
V
V
—
0.4  
OutputLOWVoltage  
IOL = 100μA  
—
0.1  
FB/FB Output Crossing Point  
VDDQ/2 - 150  
VDDQ/2  
VDDQ/2 + 150  
mV  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
0.75  
50  
μA  
IDDPD  
Power Down Current  
1.7  
18  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
19  
30  
μA/MHz  
mA  
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF  
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF  
115  
145  
50  
170  
220  
75  
ITOTQ  
Total Power VDDQ Supply Current(4)  
mA  
150  
225  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
8
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
V
InputSignalSwing(1)  
1
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
750  
mV  
V
VTHI  
CrossingPoint  
1
tR, tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(7)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
—
—
VIK  
ClampDiodeVoltage  
VDD = 2.3V, IIN = -18mA  
- 0.7  
- 1.2  
+3.6  
—
V
VIN  
VDIF  
VCM  
VIH  
VIL  
DCInputVoltage  
- 0.3  
0.2  
V
DCDifferentialVoltage(2,8)  
DC Common Mode Input Voltage(3,8)  
DC Input HIGH(4,5,8)  
DC Input LOW(4,6,8)  
Single-EndedReferenceVoltage(4,8)  
V
800  
900  
900  
1000  
—
mV  
mV  
mV  
mV  
VREF + 100  
—
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
VOX  
Output HIGH Voltage  
IOH = -8mA  
IOH = -100μA  
IOL = 8mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
V
V
—
0.4  
OutputLOWVoltage  
V
IOL = 100μA  
—
0.1  
V
FB/FBOutput Crossing Point  
VDDQ/2 - 150  
VDDQ/2  
VDDQ/2 + 150  
mV  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
9
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
1.8  
50  
μA  
IDDPD  
Power Down Current  
1.7  
19  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
17  
30  
μA/MHz  
mA  
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF  
VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF  
115  
150  
45  
170  
225  
70  
ITOTQ  
Total Power VDDQ Supply Current(4)  
mA  
100  
150  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL  
Symbol  
VDIF  
Parameter  
Value  
Units  
InputSignalSwing(1)  
1
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
900  
VTHI  
CrossingPoint  
1
tR, tF  
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
10  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR  
LVEPECL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
VDD = 2.7V  
VDD = 2.3V, IIN = -18mA  
VI = VDDQ/GND  
—
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
VI = GND/VDDQ  
VIK  
ClampDiodeVoltage  
—
- 0.7  
—
- 1.2  
3.6  
V
VIN  
VCM  
VREF  
VIH  
VIL  
DCInputVoltage  
- 0.3  
915  
—
V
DC Common Mode Input Voltage(3,5)  
Single-EndedReferenceVoltage(4,5)  
DC Input HIGH  
1082  
1082  
—
1248  
—
mV  
mV  
mV  
mV  
1275  
555  
1620  
875  
DC Input LOW  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, +25°C ambient.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL  
Symbol  
VDIF  
Parameter  
Value  
Units  
mV  
mV  
V
InputSignalSwing(1)  
732  
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
1082  
CrossingPoint  
1
VTHI  
tR, tF  
V/ns  
NOTES:  
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
11  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
InputLOWCurrent  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
+3.6  
V
V
- 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.7  
—
—
V
V
VIL  
0.7  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
DC Input HIGH(5,6,9)  
DC Input LOW(5,7,9)  
Single-EndedReferenceVoltage(5,9)  
0.2  
1150  
—
1350  
V
1250  
1250  
mV  
mV  
mV  
mV  
VREF + 100  
—
—
VIL  
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
Output HIGH Voltage  
IOH = -12mA  
IOH = -100μA  
IOL = 12mA  
IOL = 100μA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
V
V
V
V
OutputLOWVoltage  
0.4  
0.1  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and REF[1:0]/VREF[1:0] is left floating. If TxS is HIGH, FB/VREF2 should be left floating.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
12  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
13  
50  
μA  
IDDPD  
Power Down Current  
1.7  
21  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDD = Max., VDDQ = Max., CL = 0pF  
31  
40  
μA/MHz  
mA  
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF  
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF  
VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF  
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF  
115  
155  
80  
170  
230  
120  
375  
ITOTQ  
Total Power VDDQ Supply Current(4)  
mA  
250  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDD  
Units  
InputSignalSwing(1)  
V
V
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
VDD/2  
VTHI  
CrossingPoint  
2.5  
V
tR, tF  
V/ns  
NOTES:  
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF  
(AC) specification under actual use conditions.  
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDD  
0
Units  
V
Input HIGH Voltage  
VIL  
InputLOWVoltage  
V
VTHI  
InputTimingMeasurementReferenceLevel(1)  
InputSignalEdgeRate(2)  
VDD/2  
2
V
tR, tF  
V/ns  
NOTES:  
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
13  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V  
LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(8)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
InputLOWCurrent  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.7V  
VDD = 2.7V  
VI = VDDQ/GND  
VI = GND/VDDQ  
—
—
—
—
±5  
±5  
μA  
VIK  
VIN  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
- 1.2  
V
V
- 0.3  
VDDQ + 0.3  
Single-Ended Inputs(2)  
VIH  
DC Input HIGH  
DC Input LOW  
1.073(10)  
—
—
0.683(11)  
V
V
VIL  
DifferentialInputs  
VDIF  
VCM  
VIH  
DCDifferentialVoltage(3,9)  
DC Common Mode Input Voltage(4,9)  
DC Input HIGH(5,6,9)  
DC Input LOW(5,7,9)  
Single-EndedReferenceVoltage(5,9)  
0.2  
825  
—
975  
V
900  
900  
mV  
mV  
mV  
mV  
VREF + 100  
—
—
VIL  
VREF - 100  
—
VREF  
—
OutputCharacteristics  
VOH  
VOL  
Output HIGH Voltage  
IOH = -6mA  
IOH = -100μA  
IOL = 6mA  
VDDQ - 0.4  
VDDQ - 0.1  
—
—
—
V
V
V
V
OutputLOWVoltage  
0.4  
0.1  
IOL = 100μA  
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and REF[1:0]/VREF[1:0] is left floating. If TxS is MID, FB/VREF2 should be left floating.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode  
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching  
to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.  
5. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]  
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range  
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.  
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.  
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.  
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.  
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)  
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.  
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.  
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated  
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.  
14  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)  
Symbol  
Parameter  
Test Conditions(2)  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current(3)  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW,  
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,  
FBF[2:0] =LHH,Outputsenabled,Alloutputsunloaded  
VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH  
VDD = Max., VDDQ = Max., CL = 0pF  
100  
150  
mA  
IDDQQ  
Quiescent VDDQ Power Supply Current(3)  
1.8  
50  
μA  
IDDPD  
Power Down Current  
1.7  
22  
5
mA  
IDDD  
Dynamic VDD Power Supply  
CurrentperOutput  
30  
μA/MHz  
IDDDQ  
ITOT  
Dynamic VDDQ Power Supply  
VDD = Max., VDDQ = Max., CL = 0pF  
22  
30  
μA/MHz  
mA  
CurrentperOutput  
Total Power VDD Supply Current(4)  
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF  
VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF  
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF  
120  
160  
55  
180  
240  
80  
ITOTQ  
Total Power VDDQ Supply Current(4)  
mA  
170  
255  
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.  
2. The termination resistors are excluded from these measurements.  
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.  
4. FS = HIGH.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VDIF  
Parameter  
Value  
VDDI  
Units  
InputSignalSwing(1)  
V
mV  
V
VX  
DifferentialInputSignalCrossingPoint(2)  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
VDDI/2  
VTHI  
CrossingPoint  
1.8  
tR, tF  
V/ns  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable  
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.  
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification  
under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL  
Symbol  
VIH  
Parameter  
Value  
VDDI  
0
Units  
V
Input HIGH Voltage(1)  
VIL  
InputLOWVoltage  
V
VTHI  
InputTimingMeasurementReferenceLevel(2)  
InputSignalEdgeRate(3)  
VDDI/2  
2
mV  
V/ns  
tR, tF  
NOTES:  
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.  
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.  
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.  
15  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
Symbol  
FNOM  
tRPW  
Parameter  
Min.  
Typ.  
Max  
Unit  
VCO Frequency Range  
seeProgrammableSkewRangeandResolutionTable  
Reference Clock Pulse Width HIGH or LOW  
Feedback Input Pulse Width HIGH or LOW  
ProgrammableSkewTimeUnit  
1
1
—
—
—
—
ns  
ns  
tFPW  
tU  
seeControlSummaryTable  
50  
tSK(B)  
Output Matched Pair Skew(1,2,4)  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50  
—
—
—
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
tSK(O)  
tSK1(ω)  
tSK2(ω)  
tSK1(INV)  
tSK2(INV)  
tSK(PR)  
t(φ)  
OutputSkew(Rise-Rise,Fall-Fall,Nominal)(1,3)  
MultipleFrequencySkew(Rise-Rise,Fall-Fall,Nominal-Divided,Divided-Divided)(1,3,4)  
MultipleFrequencySkew(Rise-Fall,Nominal-Divided,Divided-Divided)(1,3,4)  
InvertingSkew(Nominal-Inverted)(1,3)  
InvertingSkew(Rise-Rise,Fall-Fall,Rise-Fall,Inverted-Divided)(1,3,4)  
Process Skew(1,3.5)  
—
—
100  
100  
400  
400  
400  
300  
100  
375  
275  
1.2  
1
—
—
—
—
REF Input to FB Static Phase Offset(6)  
-100  
-375  
-275  
—
tODCV  
Output Duty Cycle Variation from 50%(7)  
HSTL, eHSTL, 1.8V LVTTL  
2.5VLVTTL  
tORISE  
tOFALL  
OutputRiseTime(8)  
HSTL, eHSTL, 1.8V LVTTL  
2.5VLVTTL  
ns  
ns  
—
OutputFallTime(8)  
HSTL, eHSTL, 1.8V LVTTL  
2.5VLVTTL  
—
1.2  
1
—
tL  
Power-upPLLLockTime(9)  
PLLLockTimeAfterInputFrequencyChange(9)  
PLL Lock Time After Change in REF_SEL (9,11)  
PLLLockTimeAfterChangeinREF_SEL(REF1 andREF0aredifferentfrequency)(9)  
PLL Lock Time After Asserting PD Pin(9)  
Cycle-to-CycleOutputJitter(peak-to-peak)(10)  
PeriodJitter(peak-to-peak)(10)  
—
1
ms  
ms  
μs  
ms  
ms  
ps  
tL(ω)  
—
1
tL(REFSEL1)  
tL(REFSEL2)  
tL(PD)  
—
100  
1
—
—
1
tJIT(CC)  
tJIT(PER)  
—
75  
—
75  
ps  
tJIT(HP)  
tJIT(DUTY)  
VOX  
Half Period Jitter (peak-to-peak, QFB/QFB)(10,12)  
—
125  
100  
ps  
DutyCycleJitter(peak-to-peak)  
—
ps  
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel,  
QFB/QFB only(12)  
VDDQ/2 - 150 VDDQ/2 VDDQ/2 + 150 mV  
NOTES:  
1. Skew is the time between the earliest and latest output transition among all outputs for which the same tU delay has been selected, and when all outputs are loaded with the  
specified load.  
2. tSK(B) is the skew between a pair of outputs (nQ0 and nQ1) when all outputs are selected as the same class.  
3. The measurement is made at VDDQ/2.  
4. There are three classes of outputs: nominal (multiple of tU delay), inverted, and divided (divide-by-2 or divide-by-4 mode).  
5. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.).  
6. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken from VTHI on REF to VTHI on  
FB. For TxS/RxS = LOW, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to 0tU, FB input divider set to divide-by-  
one, and FS = HIGH.  
7. tODCV is measured with all outputs selected for 0tU.  
8. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.  
9. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQ is stable and  
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified  
limits.  
10. The jitter parameters are measured with all outputs selected for 0tU, FB input divider is set to divide-by-one, and FS = HIGH.  
11. Both REF inputs must be the same frequency, but up to ±180° out of phase.  
12. For HSTL/eHSTL outputs only.  
16  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
ACDIFFERENTIALINPUTSPECIFICATIONS(1)  
Symbol  
Parameter  
Min.  
Typ.  
—
Max  
—
Unit  
t W  
Reference/FeedbackInputClockPulseWidthHIGHorLOW(HSTL/eHSTLoutputs)(2)  
Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2)  
1
1
ns  
—
—
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL  
VDIF  
VIH  
ACDifferentialVoltage(3)  
AC Input HIGH(4,5)  
AC Input LOW(4,6)  
400  
Vx + 200  
—
—
—
—
—
—
mV  
mV  
mV  
VIL  
Vx - 200  
LVEPECL  
VDIF  
ACDifferentialVoltage(3)  
AC Input HIGH(4)  
AC Input LOW(4)  
400  
1275  
—
—
—
—
—
—
mV  
mV  
mV  
VIH  
VIL  
875  
NOTES:  
1. For differential input mode, RxS is tied to GND.  
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined  
by VDIF has been met or exceeded.  
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.  
The AC differential voltage must be achieved to guarantee switching to a new state.  
4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range.  
5. Voltage required to switch to a logic HIGH, single-ended operation only.  
6. Voltage required to switch to a logic LOW, single-ended operation only.  
17  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
AC TIMING DIAGRAM  
tRPWL  
tRPWH  
REF  
REF  
tFPWH  
tFPWL  
tODCV  
tODCV  
FB  
FB  
tODVC  
tODVC  
Q
tSK(O),  
tSK(B)  
tSK(O),  
tSK(B)  
OTHER Q  
tSK1(INV)  
tSK1(INV)  
INVERTED Q  
Q DIVIDED BY 2  
Q DIVIDED BY 4  
tSK2( ),  
tSK2(INV)  
tSK2(INV)  
tSK2( )  
tSK1( )  
tSK1( ),  
tSK2(INV)  
NOTE:  
1. The AC TIMING DIAGRAM applies to PE = VDD. For PE = GND, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative  
edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align.  
18  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
JITTER AND OFFSET TIMING WAVEFORMS  
QFB  
nQ[1:0], QFB  
tcycle n  
tcycle n + 1  
=
tjit(cc) tcycle n  
tcycle n+1  
Cycle-to-Cycle jitter  
REF[1:0]  
REF[1:0]  
FB  
FB  
t(Ø)n + 1  
t(Ø)n  
n = N  
1
t(Ø)n  
=
t(Ø)  
(N is a large number of samples)  
N
NOTE:  
1. Diagram for PE = H and TxS/RxS = L.  
Static Phase Offset  
QFB  
nQ[1:0], QFB  
tW(MIN)  
tW(MAX)  
tJIT(DUTY) = tW(MAX) - tW(MIN)  
Duty-Cycle Jitter  
19  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
QFB  
nQ[1:0], QFB  
tcycle n  
QFB  
nQ[1:0], QFB  
1
f
o
1
f
=
tjit(per) tcycle n  
o
Period jitter  
NOTE:  
1. 1/fo = average period.  
QFB  
QFB  
thalf period n+1  
thalf period n  
QFB  
QFB  
1
f
o
1
2*f  
=
tjit(hper) thalf period n  
o
Half-Period jitter  
NOTE:  
1. 1/fo = average period.  
20  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
TESTCIRCUITSANDCONDITIONS  
VDDI  
R1  
R2  
3 inch, ~50  
Transmission Line  
VIN  
VDDQ  
VDD  
VDDI  
REF[1:0]  
D.U.T.  
Pulse  
Generator  
R1  
R2  
REF[1:0]  
3 inch, ~50  
Transmission Line  
VIN  
Test Circuit for Differential Input(1)  
DIFFERENTIALINPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.2V  
Unit  
R1  
100  
100  
Ω
R2  
Ω
VDDI  
VCM*2  
V
HSTL: Crossing of REF[1:0] and REF[1:0]  
eHSTL: Crossing of REF[1:0] and REF[1:0]  
LVEPECL: Crossing of REF[1:0] and REF[1:0]  
1.8V LVTTL: VDDI/2  
VTHI  
V
2.5V LVTTL: VDD/2  
NOTE:  
1. This input configuration is used for all input interfaces. For single-ended testing,  
the REF[1:0] must be left floating. For testing single-ended in differential input  
mode, the VIN should be floating.  
21  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
VDDQ  
VDDQ  
VDDQ  
VDD  
R1  
R1  
R2  
REF[1:0]  
VDDQ  
VDD  
nQ[1:0]  
R2  
CL  
REF[1:0]  
D.U.T.  
VDDQ  
QFB  
FB  
FB  
QFB  
D.U.T.  
CL  
QFB  
R1  
R2  
FB  
FB  
QFB  
CL  
SW1  
SW1  
Test Circuit for Outputs  
Test Circuit for Differential Feedback  
DIFFERENTIALFEEDBACKTEST  
CONDITIONS  
OUTPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.2V  
VDDQ = Interface Specified  
15  
Unit  
Symbol  
VDD = 2.5V ± 0.2V  
Unit  
VDDQ = Interface Specified  
CL  
R1  
pF  
Ω
Ω
V
CL  
R1  
15  
100  
pF  
Ω
100  
R2  
100  
R2  
100  
Ω
VOX  
HSTL: Crossing of QFB and QFB  
eHSTL: Crossing of QFB and QFB  
1.8V LVTTL: VDDQ/2  
2.5V LVTTL: VDDQ/2  
TxS = MID or HIGH  
TxS = LOW  
VTHO  
SW1  
VDDQ / 2  
V
TxS = MID or HIGH  
TxS = LOW  
Open  
Closed  
VTHO  
V
SW1  
Open  
Closed  
22  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
ORDERINGINFORMATION  
X
XXXXX  
XX  
IDT  
Package Package  
Device Type  
I
-40°C to +85°C (Industrial)  
Plastic Ball Grid Array  
PBGA - Green  
BB  
BBG  
5T9010  
2.5V Programmable Skew PLL Clock  
Driver Teraclock  
23  
IDT5T9010  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
INDUSTRIALTEMPERATURERANGE  
REVISION HISTORY SHEET  
Rev  
Table  
Page  
Description of Change  
PDN - Product Discontinuance Notice  
Date  
A
1
5/21/13  
24  
IDT5T9010  
INDUSTRIALTEMPERATURERANGE  
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVER TERACLOCK  
We’ve Got Your Timing Solution.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
Sales  
Tech Support  
netcom@idt.com  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express  
or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document  
is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users.Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their  
respective third party owners.  
Copyright 2013. All rights reserved.  
25  
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