IDT5T9302
2.5V LVDS 1:2 CLOCK BUFFER TERABUFFER™ II
PRELIMINARY
Table 1. Pin Descriptions
Name
Type
Description
A[1:2]
Input
Input
Adjustable (1, 4) Clock input. A[1:2] is the "true" side of the differential clock input.
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For
LVTTL single-ended operation, A[1:2] should be set to the desired toggle
A[1:2]
Adjustable (1, 4) voltage for A[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
Gate control for differential outputs Q1, Q1 and Q2, Q2. When G is LOW, the
differential outputs are active. When G is HIGH, the differential outputs are
asynchronously driven to the level designated by GL(2). See Table 3A.
G
Input
Input
LVTTL
LVTTL
Specifies output disable level. If HIGH, "true" outputs disable HIGH and
"complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and
"complementary" outputs disable HIGH. See Table 3A.
GL
Q[1:2]
Q{1:2}
Output
Output
LVDS
LVDS
Clock outputs.
Complementary clock outputs.
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1
and A1. See Table 3B.
SEL
PD
Input
Input
LVTTL
LVTTL
Power-down control. Shuts off entire chip. If LOW, the device goes into low
power mode. Inputs and outputs are disabled. Both "true" and “complementary”
outputs will pull to VDD. Set HIGH for normal operation.(3)
VDD
GND
nc
Power
Power
Power supply for the device core and inputs.
Power supply return for all power.
No connect; recommended to connect to GND.
NOTES:
1.
Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2.
3.
4.
Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control
signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.
It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
The user must take precautions with any differential input interface standard being used in order to prevent instability when there is
no input signal.
Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz))
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
3
pF
NOTE: This parameter is measured at characterization but not tested.
IIDT™ LVDS CLOCK BUFFER TERABUFFER™ II
3
IDT5T9302 REV. A APRIL 29, 2008
