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5T9306NLI

型号：

5T9306NLI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

16 页

PDF大小：

367 K

下载PDF手册
2.5V LVDS 1:6 Clock Buffer  
Terabuffer™ II  
IDT5T9306  
DATA SHEET  
DESCRIPTION:  
FEATURES:  
TheIDT5T93062.5Vdifferential clockbufferisauser-selectabledifferential  
inputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDSoutputs  
reduces loading on the preceding driver and provides an efficient clock  
distributionnetwork. TheIDT5T9306canactasatranslatorfromadifferential  
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to  
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to  
translate to LVDS outputs. The redundant input capability allows for an  
asynchronouschange-over fromaprimaryclocksourcetoasecondaryclock  
source. SelectablereferenceinputsarecontrolledbySEL.  
• Guaranteed Low Skew < 25ps (max)  
• Very low duty cycle distortion < 125ps (max)  
• High speed propagation delay < 1.75ns (max)  
• Additive phase jitter, RMS 0.159ps (typical) @ 125MHz  
• Up to 1GHz operation  
• Selectable inputs  
• Hot insertable and over-voltage tolerant inputs  
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),  
CML, or LVDS input interface  
TheIDT5T9306outputscanbeasynchronouslyenabled/disabled. When  
disabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiplepower  
and grounds reduce noise.  
• Selectable differential inputs to six LVDS outputs  
• Power-down mode  
• 2.5V VDD  
• Available in VFQFPN package  
APPLICATIONS:  
• Clock distribution  
FUNCTIONALBLOCKDIAGRAM  
GL  
G
Q1  
OUTPUT  
CONTROL  
Q1  
PD  
Q2  
Q2  
OUTPUT  
CONTROL  
A1  
1
A1  
Q3  
Q3  
OUTPUT  
CONTROL  
A2  
Q4  
Q4  
OUTPUT  
CONTROL  
0
A2  
Q5  
Q5  
OUTPUT  
CONTROL  
SEL  
Q6  
Q6  
OUTPUT  
CONTROL  
IDT5T9306 REVISION B JANUARY 31, 2011  
1
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
PINCONFIGURATION  
28  
27 26 25 24 23 22  
21  
G
1
2
3
4
5
6
7
PD  
20  
19  
18  
17  
16  
15  
VDD  
Q4  
VDD  
Q1  
Q1  
Q4  
GND  
VDD  
A1  
VDD  
A2  
A1  
A2  
14  
8 9 10 11 12 13  
VFQFPN  
TOP VIEW  
IDT5T9306 REVISION B JANUARY 31, 2011  
2
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
ABSOLUTEMAXIMUMRATINGS(1)  
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)  
Symbol  
VDD  
VI  
Description  
Max  
–0.5 to +3.6  
–0.5 to +3.6  
–0.5 to VDD +0.5  
–65 to +150  
150  
Unit  
V
Symbol  
Parameter  
Min  
Typ.  
Max.  
Unit  
Power Supply Voltage  
CIN  
Input Capacitance  
—
—
3
pF  
Input Voltage  
V
NOTE:  
Output Voltage(2)  
Storage Temperature  
Junction Temperature  
V
1. This parameter is measured at characterization but not tested  
VO  
TSTG  
TJ  
°C  
°C  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
2. Not to exceed 3.6V.  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
2.3  
Typ.  
+25  
2.5  
Max.  
+85  
2.7  
Unit  
°C  
V
TA  
AmbientOperatingTemperature  
InternalPowerSupplyVoltage  
VDD  
PINDESCRIPTION  
Symbol  
A[1:2]  
I/O  
Type  
Description  
I
I
Adjustable(1,4) Clockinput. A[1:2] isthe"true"sideofthedifferentialclockinput.  
A[1:2]  
Adjustable(1,4) Complementaryclockinputs. A[1:2] isthecomplementarysideofA[1:2]. ForLVTTLsingle-endedoperation, A[1:2] shouldbesettothe  
desiredtogglevoltageforA[1:2]:  
3.3V LVTTL VREF = 1650mV  
2.5V LVTTL VREF = 1250mV  
G
I
I
LVTTL  
LVTTL  
GatecontrolfordifferentialoutputsQ1 andQ1 throughQ6 andQ6. WhenGisLOW, thedifferentialoutputsareactive. WhenGis  
HIGH,thedifferentialoutputsareasynchronouslydriventotheleveldesignatedbyGL(2).  
GL  
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"  
outputsdisableLOWand"complementary"outputsdisableHIGH.  
Qn  
Qn  
SEL  
O
O
I
LVDS  
LVDS  
LVTTL  
LVTTL  
Clockoutputs  
Complementaryclockoutputs  
Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.  
PD  
I
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both  
"true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)  
VDD  
GND  
N C  
PWR  
PWR  
Power supply for the device core and inputs  
Power supply return for all power  
Noconnect;recommendedtoconnecttoGND  
NOTES:  
1. Inputs are capable of translating the following interface standards:  
Single-ended 3.3V and 2.5V LVTTL levels  
Differential HSTL and eHSTL levels  
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels  
Differential LVDS levels  
Differential CML levels  
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt  
pulses or be able to tolerate them in down stream circuitry.  
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-  
up after asserting PD.  
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.  
IDT5T9306 REVISION B JANUARY 31, 2011  
3
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
—
—
—
—
±5  
±5  
- 1.2  
+3.6  
—
μA  
InputLOWCurrent  
VDD = 2.7V  
VIK  
ClampDiodeVoltage  
DCInputVoltage  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
—
V
V
V
V
V
V
VIN  
VIH  
VIL  
- 0.3  
1.7  
—
DC Input HIGH  
—
DC Input LOW  
—
0.7  
—
VTHI  
VREF  
DCInputThresholdCrossingVoltage  
Single-EndedReferenceVoltage(3)  
—
VDD /2  
1.65  
1.25  
3.3VLVTTL  
2.5VLVTTL  
—
—
—
—
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, +25°C ambient.  
3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR  
DIFFERENTIALINPUTS(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
InputCharacteristics  
IIH  
IIL  
Input HIGH Current  
VDD = 2.7V  
—
—
—
—
±5  
±5  
μA  
InputLOWCurrent  
VDD = 2.7V  
VIK  
VIN  
VDIF  
VCM  
ClampDiodeVoltage  
VDD = 2.3V, IIN = -18mA  
—
- 0.7  
—
- 1.2  
+3.6  
—
V
V
V
V
DCInputVoltage  
- 0.3  
0.1  
0.05  
DCDifferentialVoltage(3)  
DC Common Mode Input Voltage(4)  
—
—
VDD  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, +25°C ambient.  
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential  
voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state.  
4. VCM specifies the maximum allowable range of (VTR + VCP) /2.  
DCELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING  
RANGE FOR LVDS(1)  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.(2)  
Max  
Unit  
OutputCharacteristics  
VOT(+)  
VOT(-)  
ΔVOT  
VOS  
DifferentialOutputVoltagefortheTrueBinaryState  
DifferentialOutputVoltagefortheFalseBinaryState  
ChangeinVOT BetweenComplementaryOutputStates  
OutputCommonModeVoltage(OffsetVoltage)  
ChangeinVOS BetweenComplementaryOutputStates  
OutputsShortCircuitCurrent  
247  
247  
—
—
—
—
1.2  
—
12  
6
454  
454  
50  
mV  
mV  
mV  
V
1.125  
—
1.375  
50  
ΔVOS  
IOS  
mV  
mA  
mA  
VOUT + and VOUT - = 0V  
VOUT + = VOUT -  
—
24  
IOSD  
DifferentialOutputsShortCircuitCurrent  
—
12  
NOTES:  
1. See RECOMMENDED OPERATING RANGE table.  
2. Typical values are at VDD = 2.5V, TA = +25°C ambient.  
IDT5T9306 REVISION B JANUARY 31, 2011  
4
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL  
Symbol  
VDIF  
VX  
Parameter  
Value  
Units  
V
InputSignalSwing(1)  
DifferentialInputSignalCrossingPoint(2)  
1
750  
mV  
%
DH  
Duty Cycle  
50  
VTHI  
tR, tF  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
CrossingPoint  
2
V
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL  
Symbol  
VDIF  
VX  
Parameter  
Value  
Units  
V
InputSignalSwing(1)  
DifferentialInputSignalCrossingPoint(2)  
1
900  
mV  
%
DH  
Duty Cycle  
50  
VTHI  
tR, tF  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
CrossingPoint  
2
V
V/ns  
NOTES:  
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND  
LVPECL(3.3V)  
Symbol  
VDIF  
Parameter  
Value  
Units  
mV  
InputSignalSwing(1)  
732  
VX  
DifferentialInputSignalCrossingPoint(2)  
LVEPECL  
LVPECL  
1082  
mV  
1880  
DH  
Duty Cycle  
50  
%
V
VTHI  
tR, tF  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
CrossingPoint  
2
V/ns  
NOTES:  
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.  
This device meets the VX specification under actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
IDT5T9306 REVISION B JANUARY 31, 2011  
5
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS  
Symbol  
VDIF  
VX  
Parameter  
Value  
Units  
mV  
V
InputSignalSwing(1)  
DifferentialInputSignalCrossingPoint(2)  
400  
1.2  
DH  
Duty Cycle  
50  
%
VTHI  
tR, tF  
InputTimingMeasurementReferenceLevel(3)  
InputSignalEdgeRate(4)  
CrossingPoint  
2
V
V/ns  
NOTES:  
1. The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)  
specification under actual use conditions.  
2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under  
actual use conditions.  
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.  
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.  
ACDIFFERENTIALINPUTSPECIFICATIONS(1)  
Symbol  
VDIF  
VIX  
Parameter  
Min.  
0.1  
Typ.  
—
Max  
3.6  
Unit  
V
ACDifferentialVoltage(2)  
DifferentialInputCrosspointVoltage  
CommonModeInputVoltageRange(3)  
InputVoltage  
0.05  
0.05  
- 0.3  
—
VDD  
VDD  
+3.6  
V
VCM  
—
V
VIN  
V
NOTES:  
1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded.  
2. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage  
must be achieved to guarantee switching to a new state.  
3. VCM specifies the maximum allowable range of (VTR + VCP) /2.  
POWER SUPPLY CHARACTERISTICS FOR LVDS OUTPUTS(1)  
Symbol  
Parameter  
Test Conditions  
VDD = Max., All Input Clocks = LOW(2)  
Outputsenabled  
Typ.  
Max  
Unit  
IDDQ  
Quiescent VDD Power Supply Current  
—
240  
mA  
ITOT  
Total Power VDD Supply Current  
Total Power Down Supply Current  
VDD = 2.7V., FREFERENCE CLOCK = 1GHz  
PD = LOW  
—
250  
5
mA  
mA  
IPD  
—
NOTES:  
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.  
2. The true input is held LOW and the complementary input is held HIGH.  
IDT5T9306 REVISION B JANUARY 31, 2011  
6
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1,5)  
Symbol  
Parameter  
Min.  
Typ.  
Max  
Unit  
SkewParameters  
tSK(O)  
Same Device Output Pin-to-Pin Skew(2)  
Pulse Skew(3)  
—
—
—
—
—
—
25  
ps  
ps  
ps  
tSK(P)  
125  
300  
tSK(PP)  
Part-to-PartSkew(4)  
PropagationDelay  
tPLH  
tPHL  
fO  
Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint  
—
—
1.25  
1.75  
1
ns  
FrequencyRange(6)  
—
GHz  
OutputGateEnable/DisableDelay  
tPGE  
Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint  
—
—
—
—
3.5  
3.5  
ns  
ns  
tPGD  
Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level  
Power Down Timing  
tPWRDN  
PD Crossing VTHI to Qn = VDD, Qn = VDD  
Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level  
—
—
—
—
100  
100  
μS  
μS  
tPWRUP  
RMS Additive Phase Jitter  
RMS Additive Phase Jitter @ 25MHz (12kHz – 10MHz Integration Range)  
RMS Additive Phase Jitter @ 125MHz (12kHz – 20MHz Integration Range)  
RMS Additive Phase Jitter @ 156.25MHz (12kHz – 20MHz Integration Range)  
0.541  
0.159  
0.185  
ps  
ps  
ps  
tJIT  
Output Rise/Fall Time  
tR/tF  
Output Rise/Fall Time(6), (20% - 80%)  
125  
600  
ps  
NOTES:  
1. AC propagation measurements should not be taken within the first 100 cycles of startup.  
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.  
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any differential output pair under identical input and output interfaces, transitions and load conditions  
on any one device.  
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions  
at identical VDD levels and temperature.  
5. All parameters are tested with a 50% input duty cycle.  
6. Guaranteed by design but not production tested.  
IDT5T9306 REVISION B JANUARY 31, 2011  
7
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
DIFFERENTIAL ACTIMING WAVEFORMS  
1/fo  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - A[1:2]  
tPHL  
tPLH  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
tSK(O)  
tSK(O)  
+ VDIF  
VDIF = 0  
- VDIF  
Qm - Qm  
Output Propagation and Skew Waveforms  
NOTES:  
1. Pulse skew is calculated using the following expression:  
tSK(P) = | tPHL - tPLH |  
Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.  
2. AC propagation measurements should not be taken within the first 100 cycles of startup.  
IDT5T9306 REVISION B JANUARY 31, 2011  
8
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
+ VDIF  
VDIF = 0  
- VDIF  
A[1:2] - A[1:2]  
VIH  
VTHI  
VIL  
GL  
G
tPLH  
VIH  
VTHI  
VIL  
tPGD  
tPGE  
+ VDIF  
VDIF = 0  
- VDIF  
Qn - Qn  
Differential Gate Disable/Enable Showing Runt Pulse Generation  
NOTE:  
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.  
+VDIF  
VDIF=0  
-VDIF  
A1 - A1  
+VDIF  
VDIF=0  
-VDIF  
A2 - A2  
VIH  
VTHI  
VIL  
G
VIH  
VTHI  
VIL  
PD  
+VDIF  
VDIF=0  
-VDIF  
Qn - Qn  
Power Down Timing  
NOTES:  
1. It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after  
asserting PD.  
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.  
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn-Qn goes to VDIF = 0.  
IDT5T9306 REVISION B JANUARY 31, 2011  
9
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
TESTCIRCUITSANDCONDITIONS  
~50  
VIN  
Transmission Line  
VDD/2  
A
A
D.U.T.  
Pulse  
Generator  
~50  
VIN  
Transmission Line  
-VDD/2  
Scope  
50  
50  
Test Circuit for Differential Input  
DIFFERENTIALINPUTTESTCONDITIONS  
Symbol  
VDD = 2.5V ± 0.2V  
Unit  
VTHI  
Crossing of A and A  
V
IDT5T9306 REVISION B JANUARY 31, 2011  
10  
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
VDD  
A
A
Qn  
Qn  
Pulse  
Generator  
RL  
RL  
D.U.T.  
VOS  
VOD  
Test Circuit for DC Outputs and Power Down Tests  
VDD/2  
SCOPE  
CL  
Z = 50  
A
A
Qn  
Qn  
Pulse  
Generator  
50  
50  
D.U.T.  
Z = 50  
CL  
-VDD/2  
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing  
LVDSOUTPUTTESTCONDITION  
Symbol  
VDD = 2.5V ± 0.2V  
Unit  
CL  
0(1)  
8(1,2)  
50  
pF  
RL  
Ω
NOTES:  
1. Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only.  
2. The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent  
load.  
IDT5T9306 REVISION B JANUARY 31, 2011  
11  
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
VFQFPNEPADTHERMALRELEASEPATH  
In order to maximize both the removal of heat from the package and the  
electrical performance, a land pattern must be incorporated on the Printed  
Circuit Board (PCB) within the footprint of the package corresponding to the  
exposed metal pad or exposed heat slug on the package, as shown in  
Figure 1. The solderable area on the PCB, as defined by the solder mask,  
should be at least the same size/shape as the exposed pad/slug area on the  
package to maximize the thermal/electrical performance. Sufficient clearance  
should be designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
“heat pipes”) are application specific and dependent upon the package  
power dissipation as well as electrical conductivity requirements. Thus,  
thermal and electrical analysis and/or testing are recommended to determine  
the minimum number needed. Maximum thermal and electrical performance  
is achieved when an array of vias is incorporated in the land pattern. It is  
recommended to use as many vias connected to ground as possible. It is  
also recommended that the via diameter should be 12 to 13mils (0.30 to  
0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any  
solder wicking inside the via during the soldering process which may result  
in voids in solder between the exposed pad/slug and the thermal land.  
Precautions should be taken to eliminate any solder voids between the  
exposed heat slug and the land pattern. Note: These recommendations are  
to be used as a guideline only. For further information, refer to theApplication  
Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically  
Enhance Leadframe Base Package,Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer and  
electrical grounding from the package to the board through a solder joint,  
thermal vias are necessary to effectively conduct from the surface of the PCB  
to the ground plane(s). The land pattern must be connected to ground  
through these vias. The vias act as “heat pipes”. The number of vias (i.e.  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
FIGURE 1. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)  
IDT5T9306 REVISION B JANUARY 31, 2011  
12  
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
RECOMMENDEDLANDINGPATTERN  
NL 28 pin  
NOTE: All dimensions are in millimeters.  
IDT5T9306 REVISION B JANUARY 31, 2011  
13  
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
July 23, 2002  
Datasheet creation  
October 8, 2002  
Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 4, DC Cha. for LVPECL  
and Differential Input tables; page 6, DC Cha. and Power Supply tables; page 7, entire page; page 9, added note 3;  
page 10, entire page; page 10, entire page; page 11, entire page; page 12, Ordering Info; added 3 new pages (10 thru  
12) of diagrams.  
October 10, 2002  
October 24, 2002  
Page 1, entire page changed; page 2, both diagrams; page 3, Pin Description and notes; page 7, AC Cha. table; page  
8, added new LVPECL table; page 10, removed Input Clock Switching diagram; page 11, deleted entire page; page  
12, changed Power Down Timing; page 15, Ordering Info.  
Page2,addednote1toTQFPTOPVIEWtext;page3,adednote4toPinDescription;page4,replaced"Compliantdevices  
must meet" with the text "This device meets" in four instances; page 5, Differential Input table, note 1, changed 1V  
to 732mV and replaced "Compliant devices must meet" with the text "This device meets"; page 6, DC Electrical table,  
Vdif row, changed Min. value to 0.1, and under Differential Input table replaced "Compliant devices must meet" with  
the text "This device meets" page 7, Power Supply table, replaced ((TBD)) with 800MHz, and under AC Electrical table,  
replaced((TBD))with500;page8,completelyalteredACDIfferentialtable;page12,LVDSOutputtable,replaced((TBD))  
with 3.  
November 1, 2002  
December 12, 2002  
December 16, 2002  
Radical changes to entire document.  
Radical changes to entire document, using 5T9316 as a base.  
Throughout document, removed "Differential" from title; page 7, Power Supply table, changed Max values, changed  
FREFERENCE value; page 10, note 1, changed Gx to G.  
May 8, 2003  
Page 2, corrected pinout diagram.  
August 7, 2003  
Page 1, Features text, 3rd bullet, changed 2ns to 1.75ns, 4th bullet, changed 800MHz to 1GHz, and 7th bullet, added  
CML, on Description, 3rd line, added CML to list; page 4, Pin Descr., note 1, added "Differential CML levels", for  
Description of PD row, replaced 2nd sentence with "Both 'true' and 'complementary' output will pull to Vdd"; page  
5, DC... forDifferentialInputstable, removednote5andchangedVcmMax. from3.5toVdd;page7, PowerSupplytable,  
changed 800MHz to 1GHz; page 8, AC Differential table, changed Vix and Vcm Max specs from 3.5V to Vdd, removed  
notes 4 and 5, and placed entire table on page 7, for AC Elect. table, added notes 5 and 6, changed ((TBD)) to 300ps,  
tplh Type to 1.25ns, and Max from 2ns to 1.75ns, and changed fo Max from 800MHz to 1GHz.  
Page 1, Features, 7th bullet, added "3.3V / 2,5V LVTTL" to front, Description, added to 1st paragraph "A single-ended  
3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs."; page 4, Pin Description table, added large  
block of text to 2nd row, added "Single-ended 3.3V and 2.5V LVTTL levels" to note 1; page 5, DC for LVTTL table, added  
Vref row and note 3, for DC for LVDS table, changed Ios ratings from 5 Typ, 7.5 Max to 12 Typ, 24 Max, and changed  
Iosd ratings from 5 Typ, 7.5 Max to 6 Typ, 12 Max; page 7, Power Supply table, changed Ipd from 3 to 5.  
Page 2, changed pin 22 to NC; page 3, changed pin 25 to NC; page 4, added NC row to Pin Description.  
Removed TQFP package.  
October 2, 2003  
March 26, 2004  
June 22, 2004  
October 26, 2004  
October 27, 2004  
October 29, 2004  
March 9, 2005  
Inserted a page before Ordering Info and added Landing Pattern.  
Added note to Landing Pattern.  
Changed landing pattern diagram.  
Page 6, switched Iddq and Itot values.  
October 23, 2007  
April 15, 2008  
Page 7, added Additive Phase Jitter, RMS specs to the AC Electrical Characterisitcs Table.  
Page 7, added Rise/Fall Time spec. to the AC Electrical Characteristics Table.  
January 31, 2011  
Page 12, added VFQFPN Thermal Release Path application note.  
Updated to header/footer to new format.  
IDT5T9306 REVISION B JANUARY 31, 2011  
14  
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
ORDERINGINFORMATION  
XX  
X
XXXXX  
Package Process  
Device Type  
I
-40°C to +85°C (Industrial)  
Thermally Enhanced Plastic Very Fine Pitch  
Quad Flat No Lead Package  
NL  
2.5V 1:6 LVDS Clock Buffer Terabuffer™ II  
5T9306  
IDT5T9306 REVISION B JANUARY 31, 2011  
15  
©2011 Integrated Device Technology, Inc.  
IDT5T9306 Data Sheet  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
IDT5T9306  
2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II  
We'veGotYourTimingSolution  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
Sales  
Techical Support  
netcom@idt.com  
+480-763-2056  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.All information  
in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are  
determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any  
kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property  
rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users.  
Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or  
their respective third party owners.  
Copyright 2011.All rights reserved.  
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