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XWM8740EDS

型号:

XWM8740EDS

描述:

24位高性能192kHz的立体声DAC[ 24-bit, High Performance 192kHz Stereo DAC ]

品牌:

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数:

20 页

PDF大小:

345 K

WM8740  
24-bit, High Performance 192kHz Stereo DAC  
Advanced Information, July 2000, Rev 1.7  
DESCRIPTION  
FEATURES  
120dB SNR (‘A’ weighted mono @48kHz), THD+N: -104dB  
@ FS  
117dB SNR (‘A’ weighted stereo @48kHz), THD+N: -104dB  
@ FS  
Sampling frequency: 8kHz to 192kHz  
Selectable digital filter roll-off  
Optional interface to industry standard external filters  
Differential mono mode needing no glue logic  
Input data word: 16 to 24-bit  
The WM8740 is a very high performance stereo DAC  
designed for audio applications such as CD, DVD, home  
theatre systems, set top boxes and digital TV. The WM8740  
supports data input word lengths from 16 to 24-bits and  
sampling rates up to 192kHz. The WM8740 consists of a  
serial interface port, digital interpolation filter, multi-bit sigma  
delta modulator and stereo DAC in a small 28-pin SSOP  
package. The WM8740 also includes a digitally controllable  
mute and attenuator function on each channel.  
Hardware or SPI compatible serial port control modes:  
The internal digital filter has two selectable roll-off  
characteristics. A sharp or slow roll-off can be selected  
dependent on application requirements. Additionally, the  
internal digital filter can be by-passed and the WM8740  
used with an external digital filter.  
Hardware mode: mute, de-emphasis, audio format  
control  
Serial mode: mute, de-emphasis, attenuation (256  
steps), phase reversal  
Fully differential voltage outputs  
The WM8740 supports two connection schemes for audio  
DAC control. The SPI-compatible serial control port  
provides access to a wide range of features including on-  
chip mute, attenuation and phase reversal. A hardware  
controllable interface is also available.  
APPLICATIONS  
CD, DVD audio  
Home theatre systems  
Professional audio systems  
BLOCK DIAGRAM  
MODE ML/I2S MC/DM1 MD/DM0 DIFFHW MUTEB CSBIWO RSTB ZERO MODE8X AGNDR AVDDR  
(24)  
(28)  
(27)  
(26)  
(6)  
(25)  
(23)  
(22) (21)  
(4)  
(10) (9)  
WM8740  
(11) VMIDR  
CONTROL INTERFACE  
SIGMA  
DELTA  
MODULATOR  
LOW  
PASS  
FILTER  
(12) VOUTRP  
(13) VOUTRN  
RIGHT  
DAC  
SCLK (5)  
MUX  
MUX  
MUTE/  
ATTEN  
BCKIN (3)  
SERIAL  
INTERFACE  
DIGITAL  
FILTERS  
LRCIN (1)  
DIN (2)  
SIGMA  
DELTA  
MODULATOR  
LOW  
PASS  
FILTER  
(17) VOUTLP  
(16) VOUTLN  
LEFT  
DAC  
MUTE/  
ATTEN  
(18) VMIDL  
(15)  
(8)  
(20) (19)  
(14) (7)  
AVDD DVDD  
AVDDL. AGNDL AGND DGND  
WOLFSON MICROELECTRONICS LTD  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
Advanced Information data sheets contain  
preliminary data on new products in the  
preproduction phase of development.  
Supplementary data will be published at a  
later date.  
http://www.wolfson.co.uk  
2000 Wolfson Microelectronics Ltd.  
WM8740  
Advanced Information  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
ML/I2S  
MC/DM1  
MD/DM0  
MUTEB  
MODE  
LRCIN  
DIN  
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
XWM8740EDS  
-25° to +85°C  
28-pin SSOP  
BCKIN  
MODE8X  
SCLK  
DIFFHW  
DGND  
CSBIWO  
RSTB  
DVDD  
ZERO  
AVDDR  
AGNDR  
VMIDR  
AVDDL  
AGNDL  
VMIDL  
11  
12  
13  
14  
VOUTLP  
VOUTLN  
AVDD  
VOUTRP  
VOUTRN  
AGND  
PIN DESCRIPTION  
PIN  
1
NAME  
LRCIN  
DIN  
TYPE  
Digital input  
Digital input  
Digital input  
Digital input  
Digital input  
Digital input  
Supply  
DESCRIPTION  
Sample rate clock input.  
2
Audio data serial input (except in 8XMODE when it is DINL).  
Audio data bit clock input .  
3
BCKIN  
MODE8X  
SCLK  
4
Internal pull-down, active high, 8 x fs mode.  
System clock input.  
5
6
DIFFHW  
DGND  
DVDD  
Internal pull-down, active high, differential mono mode.  
Digital ground supply.  
7
8
Supply  
Digital positive supply.  
9
AVDDR  
AGNDR  
VMIDR  
Supply  
Analogue positive supply.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Supply  
Analogue ground supply.  
Analogue output  
Mid rail right channel.  
VOUTRP Analogue output  
VOUTRN Analogue output  
Right channel DAC output positive.  
Right channel DAC output negative.  
Analogue ground supply.  
AGND  
AVDD  
Supply  
Supply  
Analogue positive supply.  
VOUTLN Analogue output  
VOUTLP Analogue output  
Left channel DAC output negative.  
Left channel DAC output positive.  
Mid rail left channel.  
VMIDL  
AGNDL  
AVDDL  
ZERO  
Analogue output  
Supply  
Analogue ground supply.  
Supply  
Analogue positive supply.  
Digital output  
Digital input  
Infinite zero detect active low. Open drain type output with active pull-down.  
Reset input active low. Internal pull-up.  
RSTB  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
2
Advanced Information  
WM8740  
PIN  
NAME  
TYPE  
DESCRIPTION  
Hardware Mode  
Normal Mode  
Software  
Mode  
Differential Mode  
8X Mode  
Wordlength:  
Wordlength:  
Wordlength:  
Low for 20-bit data.  
High for 24-bit data.  
Low for  
serial  
interface  
operation.  
23  
CSBIWO  
Digital input  
Low for 16-bit data.  
High for 20-bit  
(normal) or 24-bit  
I2S data.  
Low for 16-bit data.  
High for 20-bit  
(normal) or 24-bit  
I2S data.  
Internal pull-down  
24  
25  
MODE  
Digital input  
Low for hardware  
mode.  
Low for left  
mono mode.  
DINR  
High for  
software  
mode.  
Internal pull-up  
High for right  
mono mode  
MUTEB  
Digital input  
Low to soft mute.  
Low to soft mute.  
Low to soft mute.  
Low to  
soft mute.  
Internal pull-up  
High for normal  
operation.  
High for normal  
operation.  
High for normal  
operation.  
High for  
normal  
operation.  
26  
27  
28  
MD/DM0  
MC/DM1  
ML/I2S  
Digital input  
De-emphasis mode  
select bit 0.  
Low for no  
de-emphasis.  
LRP LRCLK  
polarity select.  
Control serial  
interface  
data signal.  
Internal pull-up  
High for 44.1kHz  
de-emphasis.  
Digital input  
De-emphasis mode  
select bit 1.  
Low for normal filter  
operation.  
Unused.  
Control serial  
interface  
clock signal.  
Internal pull-up  
Leave unconnected.  
High for filter slow  
roll-off.  
Digital input  
Audio serial format:  
Low right justified.  
High I2S.  
Audio serial format:  
Low right justified.  
High I2S.  
Input data format:  
Low right justified.  
High left justified.  
Control serial  
interface  
load signal.  
Internal pull-up  
Note: Digital input pins have Schmitt trigger input buffers.  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
CONDITION  
MIN  
MAX  
+7.0V  
Supply voltage  
-0.3V  
Reference input  
VDD + 0.3V  
Operating temperature range, TA  
Storage temperature  
°
°
+85 C  
-25 C  
°
°
+150 C  
-65 C  
Package body temperature (soldering, 10 seconds)  
Package body temperature (soldering, 2 minutes)  
°
+240 C  
°
+183 C  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
3
WM8740  
Advanced Information  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital supply range  
Analogue supply range  
Ground  
DVDD  
AVDD  
-10%  
-10%  
3.3 to 5  
+10%  
+10%  
V
V
3.3 to 5  
AGND, DGND  
0
0
V
Difference DGND to AGND  
Analogue supply current  
Digital supply current  
Analogue supply current  
Digital supply current  
-0.3  
+0.3  
V
AVDD = 5V  
DVDD = 5V  
AVDD = 3.3V  
DVDD = 3.3V  
15  
15  
15  
9
mA  
mA  
mA  
mA  
ELECTRICAL CHARACTERISTICS  
TEST CONDITIONS  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
DAC Circuit Specifications  
SNR  
SYMBOL  
TEST CONDITIONS  
MIN  
110  
-95  
TYP  
MAX  
UNIT  
Mono fs @ 48kHz  
Stereo fs @ 48kHz  
Stereo fs @ 96kHz  
Mono 0dB  
120  
117  
116  
-104  
-104  
117  
dB  
dB  
dB  
dB  
dB  
dB  
(See Note 1)  
THD (full-scale)  
(See Note 2)  
Stereo 0dB  
THD+N (Dynamic range)  
(See Note 2)  
-60dB  
Filter Characteristics (Sharp Roll-off)  
Passband  
±0.0012 dB  
0.4535fs  
-82  
dB  
Stopband  
-3dB  
0.491fs  
30/fs  
Passband ripple  
±0.0012  
±0.001  
dB  
dB  
s
Stopband attenuation  
Delay time  
f > 0.5465fs  
Filter Characteristics (Slow Roll-off)  
Passband  
±0.001dB  
0.274fs  
0.459fs  
Stopband  
-3dB  
Passband ripple  
dB  
dB  
s
Stopband attenuation  
Delay time  
f > 0.732fs  
-82  
9/fs  
Internal Analogue Filter  
Bandwidth  
-3dB  
195  
kHz  
dB  
Passband edge response  
Digital Logic Levels  
20kHz  
-0.043  
Input LOW level  
Input HIGH level  
Output LOW level  
Output HIGH level  
VIL  
VIH  
0.8  
2.0  
V
V
VOL  
VOH  
IOL = 2mA  
IOH = 2mA  
AVSS + 0.3V  
AVDD - 0.3V  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
4
Advanced Information  
WM8740  
TEST CONDITIONS  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Analogue Output Levels  
Output level differential  
Into 10kohm, full scale 0dB,  
(5V supply)  
2
1.32  
1
VRMS  
VRMS  
Into 10kohm, full scale 0dB,  
(3.3V supply)  
Minimum resistance load  
To midrail or AC coupled  
(5V supply)  
kohms  
ohms  
To midrail or AC coupled  
(3.3V supply)  
600  
Maximum capacitance load  
Output DC level  
5V or 3.3V  
100  
pF  
V
AVDD/2  
Reference Levels  
Potential divider resistance  
10  
AVDD/2  
2.2  
kohms  
AVDD to VMIDL/VMIDR and  
VMIDL/VMIDR to AGND  
Voltage at VMIDL/VMIDR  
POR  
POR threshold  
V
Notes: 1.  
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured A’  
weighted over a 20Hz to 20kHz bandwidth.  
2.  
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher  
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low  
pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.  
LRCIN  
tBCH  
tBCL  
tLB  
BCKIN  
DIN  
tBCY  
tBL  
tDS  
tDH  
Figure 1 Audio Data Input Timing  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN pulse cycle time  
BCKIN pulse width high  
BCKIN pulse width low  
tBCY  
tBCH  
tBCL  
tBL  
100  
40  
ns  
ns  
ns  
ns  
40  
BCKIN rising edge to  
LRCIN edge  
20  
LRCIN rising edge to  
BCKIN rising edge  
tLB  
20  
ns  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
5
WM8740  
Advanced Information  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
DIN setup time  
DIN hold time  
SYMBOL  
tDS  
TEST CONDITIONS  
MIN  
20  
TYP  
MAX  
UNIT  
ns  
tDH  
20  
ns  
tSCKIL  
SCKI  
tSCKIH  
tSCKY  
Figure 2 System Clock Timing Requirements  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
System Clock Timing Information  
System clock pulse width high  
System clock pulse width low  
System clock cycle time  
tSCKIH  
tSCKIL  
tSCKY  
10  
10  
27  
ns  
ns  
ns  
tMLL  
tMHH  
ML/I2S  
tMCY  
tMCH tMCL  
tMLD  
tMLS  
MC/DM1  
MD/DM0  
tMDS  
tMDH  
LSB  
Figure 3 Program Register Input Timing – SPI Compatible Serial Control Mode  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Program Register Input Information  
MC/DM1 pulse cycle time  
MC/DM1 pulse width low  
MD/DM0 pulse width high  
MD/DM0 set-up time  
tMCY  
tMCL  
tMCH  
tMDS  
tMDH  
tMLL  
tMHH  
tMLS  
tMLD  
80  
32  
32  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MC/DM1 hold time  
ML/I2S pulse width low  
ML/I2S pulse width high  
ML/I2S set-up time  
ML/I2S delay from MC  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
6
Advanced Information  
WM8740  
DEVICE DESCRIPTION  
The WM8740 is a high performance 128fs oversampling rate stereo DAC employing a novel 64 level  
sigma delta DAC design which provides optimised signal-to-noise performance and clock jitter  
tolerance. It is ideally suited to high quality audio applications such as CD, DVD-audio, home theatre  
receivers and professional mixing consoles. The WM8740 supports sample rates from 8ks/s to  
192ks/s.  
The control functions of the WM8740 are either pin selected (hardware mode) or programmed via the  
serial interface (software mode). Control functions that are available include: data input word length  
and format selection (16-24 bits: I2S, left justified or right justified): de-emphasis sample rate  
selection (48kHz, 44.1kHz and 32kHz); differential output modes; a software or hardware mute and  
independently digitally controllable attenuation on both channels.  
The digital filtering may be bypassed entirely by selecting MODE8X. Data is then input directly to the  
DAC, bypassing the digital filters. Left and right channels are input separately, using the MODE pin  
as the right channel input. This mode allows the use of alternative digital filters, such as the Pacific  
Microsonics PMD100 HDCD filter.  
In addition to the normal stereo operating mode the WM8740 may also be used in dual differential  
mode with either the left or right channel (selectable) being output dual differentially. Two WM8740s  
can then be used in parallel to implement a stereo channel, each supporting a single channel  
differentially. Note that this mode uses 2 pairs of differential outputs for each channel the benefit is  
SNR improved by 3dB. This mode is available in both software and hardware modes and may also  
be used in conjunction with MODE8X.  
SYSTEM CLOCK  
Sample rates from 8ks/s up to 96ks/s are available, and automatically selected, with a system clock  
of 256fs or 384fs. In addition a system clock of 128fs or 192fs may be used, with sample rates up to  
192ks/s. With a 128fs or 192fs system clock 64x oversampling mode operation is automatically  
selected and the first stage of the digital filter is bypassed.  
WM8740 has an asynchronous monitor circuit, which in the event of removal of the master system  
clock, resets the digital filters and analogue circuits, muting the output. Re-application of the system  
clock re-starts the filters from an intitialised state. Control registers are not reset under this condition.  
The WM8740 is tolerant of asynchronous bit clock jitter. The internal signal processing  
resynchronises to the external LRCIN once the phase difference between bit clock and the system  
clock exceeds half an LRCIN period. During this re-synch period the interpolating filters will either  
miss or repeat an audio sample, minimising the audible effects of the operation. Table 1 shows the  
typical system clock frequency inputs for the WM8740.  
SAMPLING  
RATE  
SYSTEM CLOCK FREQUENCY (MHZ)  
128fs  
192fs  
256fs  
384fs  
(LRCIN)  
32kHz  
4.096  
5.6448  
6.114  
6.144  
8.467  
8.192  
11.2896  
12.288  
24.576  
12.288  
16.9340  
18.432  
36.864  
44.1kHz  
48kHz  
9.216  
96kHz  
12.288  
24.576  
18.432  
36.864  
192kHz  
Unavailable Unavailable  
Table 1 System Clock Frequencies Versus Sampling Rate  
AUDIO DATA INTERFACE  
Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs, in  
which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs or 192fs may be  
used, in which case the first filter stage is bypassed and an oversampling ratio of 64x results. Finally,  
in MODE8X, data may be input at 8x the normal rate, in which case separate input pins are used to  
input the two stereo channels of data (unless DIFFHW mode and MODE8X are both selected, in  
which case only a mono channel is converted differentially). In MODE8X all filter stages are by-  
passed, prior to the sigma delta modulator. Data is input MSB first in all modes.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
7
WM8740  
Advanced Information  
NORMAL SAMPLE RATE  
In normal mode, the data is input serially on one pin for both left and right channels.  
Data can be right justifiedmeaning that the last 16, 20 or 24 bits (depending on chosen PCM word  
length) that were clocked in prior to the transition on LRCIN are valid.  
Alternatively data can be left justified(20 and 24-bit PCM data only), where the bits are clocked in  
as the first 20 or 24 bits after a transition on LRCIN.  
For the three I2S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked left justified”  
except with one additional preceding clock cycle.  
1/fs  
LEFT  
RIGHT  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
16-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
B0  
B15  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
B15  
B2 B1 B0  
B2 B1 B0  
B2 B1 B0  
20-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B19 B18 B17  
B19 B18 B17  
24-BIT RIGHT  
JUSTIFIED  
DIN (PIN 2)  
B23 B22 B21 B20 B19  
B23 B22 B21 B20 B19  
24-BIT LEFT  
JUSTIFIED  
DIN (PIN 2)  
B23 B22 B21  
B4 B3 B2 B1 B0  
B23 B22 B21  
B4 B3 B2 B1 B0  
20-BIT LEFT  
JUSTIFIED  
DIN (PIN 2)  
B0  
B19 B18 B17  
B0  
B19 B18 B17  
B0  
LEFT  
RIGHT  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
16-BIT I2S  
DIN (PIN 2)  
B15  
B23  
B19  
B2 B1 B0  
B15  
B23  
B19  
B2 B1 B0  
B15  
B23  
B19  
24-BIT I2S  
DIN (PIN 2)  
B6 B5 B4 B3 B2 B1 B0  
B6 B5 B4 B3 B2 B1 B0  
20-BIT I2S  
DIN (PIN 2)  
B2 B1 B0  
B2 B1 B0  
Figure 4 Audio Data Input Format  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
8
Advanced Information  
WM8740  
8 X FS INPUT SAMPLE RATE  
Due to the higher speed of the interface in 8 x fs mode, audio data is input on two pins. The MODE  
pin (pin 24) is used as the second input for the right channel data and left data is input on DIN (pin2).  
In this mode, software control of the device is not available. The data can be input in two formats, left  
or right justified, selectable by ML/I2S and two word lengths (20 or 24 bit), selectable by CSBIWO. In  
both modes the data is always clocked in MSB first.  
For left justified data the word start is marked by the falling edge of LRCIN. The data is clocked in on  
the next 20/24 BCKIN rising edges. This format is compatible with devices such as the PMD100.  
For right justified the data is justified to the rising edge of LRCIN and the data is clocked in on the  
preceding 20/24 BCKIN rising edges before the LRCIN rising edge. This format is compatible with  
devices such as the DF1704 or SM5842.  
In both modes the polarity of LRCIN can be switched using MD/DM0.  
Differential hardware mode can be used in conjunction with 8fs mode by setting the DIFFHW  
pin high. In differential 8fs mode the data is input on DIN and output differentially. MODE is  
unused and must be tied low.  
1/8fs  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
LEFT AUDIO  
B23  
B23  
B22  
B22  
B21  
B21  
B20  
B20  
B19  
B19  
B2  
B2  
B1  
B1  
B0  
B0  
B23  
B23  
B22  
B22  
B21  
B21  
B20  
B20  
DATA DIN  
(PIN 2)  
RIGHT AUDIO  
DATA MODE  
(PIN 24)  
1/8fs  
LRCIN (PIN 1)  
BCKIN (PIN 3)  
LEFT AUDIO  
DATA DIN  
(PIN 2)  
B23  
B22  
B21  
B21  
B20  
B20  
B19  
B19  
B2  
B2  
B1  
B1  
B0  
B0  
RIGHT AUDIO  
DATA MODE  
(PIN 24)  
B23  
B22  
Figure 5 Audio Data Input Format (8 x fs Operation)  
MODES OF OPERATION  
Control of the various modes of operation is either by software control over the serial interface, or  
by hard-wired pin control. Selection of software or hardware mode is via MODE pin. The following  
functions may be controlled either via the serial control interface or by hard wiring of the  
appropriate pins.  
HARDWARE CONTROL MODES  
When the MODE pin is held lowthe following hardware modes of operation are available. In  
Hardware differential mode or 8X mode some of these modes/control words are altered or  
unavailable.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
9
WM8740  
Advanced Information  
DE-EMPHASIS CONTROL  
MDDM1  
MCDMO  
DE-EMPHASIS  
PIN 27  
PIN 26  
L
L
L
H
L
Off  
48kHz  
44.1kHz  
32kHz  
H
H
H
Table 2 De-Emphasis Control  
AUDIO INPUT FORMAT  
ML/I2S  
PIN 28  
L
CSBIWO  
PIN 23  
L
DATA FORMAT  
16 bit normal right  
justified  
L
H
20 bit normal right  
justified  
H
H
L
16 bit I2S  
24 bit I2S  
H
Table 3 Audio Input Format  
SOFT MUTE  
MUTEB  
PIN 25  
L
FUNCTION  
Mute On (no output)  
Mute Off (normal operation)  
H
Table 4 Soft Mute  
A logic low on the MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of  
128/fs seconds per 0.5dB step. Setting MUTEB high will cause the attenuation to ramp back to its  
previous value.  
SOFTWARE CONTROL INTERFACE  
The WM8740 can be controlled using a 3-wire serial interface. MD/DM0 (pin 26) is used for the  
program data, MC/DM1 (pin 22) is used to clock in the program data and ML/I2S (pin 28) is use to  
latch in the program data. The 3-wire interface protocol is shown in Figure 6. CSB/IWO (pin 23) must  
be low when writing.  
ML/I2S (PIN 28)  
MC/DM1 (PIN 27)  
MD/DM0 (PIN 26)  
B15 B14 B13  
B2  
B1  
B0  
Figure 6 Three-Wire Serial Interface  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
10  
Advanced Information  
WM8740  
REGISTER MAP  
WM8740 controls the special functions using 4 program registers, which are 16-bits long. These  
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is  
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the 4  
registers. Note that in hardware differential mode and 8X modes, software control is not available.  
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by  
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
AL7  
AR7  
-
B6  
AL6  
AR6  
-
B5  
AL5  
AR5  
-
B4  
AL4  
AR4  
IW1  
B3  
AL3  
AR3  
B2  
AL2  
AR2  
B1  
AL1  
AR1  
B0  
AL0  
AR0  
M0  
M1  
M2  
M3  
M4  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A2 (0) A1(0) A0(0) LDL  
A2(0) A1(0) A0(1) LDR  
A2(0) A1(1) A0(0)  
A2(0) A1(1) A0(1) IZD  
A2(1) A1(1) A0(0)  
-
IW0 OPE DEM MUT  
SF1  
-
SF0  
CK0 REV SR0 ATC LRP  
I2S  
-
CDD DIFF1 DIFF0  
-
-
-
-
Table 5 Mapping of Program Registers  
REGISTER  
BITS  
NAME  
AL[7:0]  
LDL  
DEFAULT  
DESCRIPTION  
0
[7:0]  
FF  
0
Attenuation data for left channel.  
Attenuation data load control for left channel.  
Attenuation data for right channel.  
Attenuation data load control for right channel.  
Left and right DACs soft mute control.  
De-emphasis control.  
8
[7:0]  
8
1
2
AR[7:0]  
LDR  
FF  
0
0
MUT  
DEM  
OPE  
IW[1:0]  
I2S  
0
1
0
2
0
Left and right DACs operation control.  
Input audio data bit select.  
[4:3]  
0
0
3
0
Audio data format select.  
1
LRP  
0
Polarity of LRCIN select.  
2
ATC  
0
Attenuator control.  
3
SR0  
0
Digital filter slow roll-off select.  
Output phase reverse.  
4
REV  
0
5
CKO  
SF[1:0]  
IZD  
0
CLKO frequency select.  
[7:6]  
8
0
Sampling rate select.  
0
Infinite zero detection circuit control.  
Differential output mode.  
4
[5:4]  
6
DIFF  
CDD  
0
0
Clock loss detector disable.  
Table 6 Register Bit Descriptions  
DAC OUTPUT ATTENUATION  
The level of attenuation for eight bit code X, is given by:  
0.5 (X - 255) dB, 1 X 255  
- dB (mute),  
X = 0  
Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in B[7:0]. When LDL is set  
to 0, attenuation data will be loaded into AL[7:0], but it will not affect the filter attenuation. LDR in  
register 1 has the same function for right channel attenuation. Only when LDL or LDR is set to 1will  
the filter attenuation be updated. This permits left and right channel attenuation to be updated  
simultaneously.  
Attenuation level is controlled by AL[7:0] (left channel) or AR[7:0] (right channel). Attenuation levels  
are given in Table 7.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
11  
WM8740  
Advanced Information  
X[7:0]  
ATTENUATION LEVEL  
00(hex)  
- dB (mute)  
01(hex)  
-127.0dB  
:
:
:
:
FD(hex)  
FE(hex)  
-1.0dB  
-0.5dB  
0.0dB  
FF(hex)  
Table 7 Attenuation Control Level  
Bit 2 in Reg3 is used to control the attenuator (ATC). When ATC is high, the attenuation data  
loaded in program register 0 is used for both the left and the right channels. When ATC is low, the  
attenuation data for each register is applied separately to left and right channels.  
SOFT MUTE  
MUT  
(REG2, B0)  
L
Soft Mute off (normal operation)  
Soft Mute on (no output)  
H
Table 8 Soft Mute  
Setting MUT causes the attenuation to ramp from the current value down to 00. The values held in  
the attenuation registers are unchanged. When MUT is reset the attenuation will ramp back up to the  
previous value. The ramp rate is 128/fs s/0.5dB step.  
DIGITAL DE-EMPHASIS  
DEM  
(REG2, B1)  
L
De-emphasis off  
De-emphasis on  
H
Table 9 Digital De-Emphasis  
DAC OPERATION ENABLE  
OPE  
(REG2,B2)  
L
Normal operation  
H
DAC output forced to bipolar zero,  
irrespective of input data.  
Table 10 DAC Operation Enable  
AUDIO DATA INPUT FORMAT  
I2S  
IW1  
IW0  
AUDIO INTERFACE  
(REG3, B0)  
(REG2, B4)  
(REG2, B3)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16-bit standard right justified  
20-bit standard right justified  
24-bit standard right justified  
24-bit left justified (MSB first)  
16-bit I2S  
24-bit I2S  
20-bit I2S  
20-bit left justified (MSB first)  
Table 11 Audio Data Input Format  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
12  
Advanced Information  
WM8740  
POLARITY OF LR INPUT CLOCK  
The left channel data for a particular sample instant is always input first, then the right channel data.  
LRP  
(REG3, B1)  
L
LR High left channel  
LR Low right channel  
LR Low left channel  
LR High right channel  
H
Table 12 Polarity of LR Input Clock  
INDIVIDUAL OR COMMON ATTENUTATION CONTROL  
ATC  
(REG3, B2)  
L
Individual control  
H
Common control from Reg0  
Table 13 Individual or Common Attenuation Control  
DIGITAL FILTER ROLL-OFF SELECTION  
SRO  
(REG3, B3)  
L
Sharp  
Slow  
H
Table 14 Digital Filter Roll-Off Selection  
ANALOGUE OUTPUT POLARITY REVERSAL  
REV  
(REG3, B4)  
L
Normal  
H
Inverted  
Table 15 Analogue Output Polarity Reversal  
CLKO OUTPUT FREQUENCY  
CKO  
(REG3, B5)  
L
XTI  
H
XTI/2  
Table 16 CLKO Output Frequency  
DE-EMPHASIS SAMPLE RATE  
SF1  
SF0  
SAMPLE RATE  
(REG3, B7)  
(REG3, B6)  
0
0
1
1
0
1
0
1
No de-emphasis  
48kHz  
44.1kHz  
32kHz  
Table 17 De-Emphasis Sample Rate  
INFINITE ZERO DETECT  
IZD  
(REG3, B8)  
L
Zero detect mute off  
Zero detect mute on  
H
Table 18 Infinite Zero Detect  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
13  
WM8740  
Advanced Information  
DIFFERENTIAL MONO MODE  
Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed  
stereo, mono left or mono right, as shown in Table 19.  
DIFF[1:0]  
B[4:5])  
00  
DIFFERENTIAL OUTPUT MODE  
Stereo  
01  
Stereo reverse.  
10  
Mono left differential outputs.  
VOUTL is left channel.  
VOUTR is the negative of left channel.  
Mono right differential outputs.  
VOUTL is the negative right channel.  
VOUTR is right channel.  
11  
Table 19 Differential Output Modes  
Using these controls a pair of WM8740 devices may be used to build a dual differential stereo  
implementation with higher performance and differential output.  
Note: DIFFHW mode pin may be used to achieve the same result by hardware means.  
CLOCK LOSS DETECTOR DISABLE  
CDD (REG4, B6)  
L
Clock loss detector on  
Clock loss detector off  
R
Table 20 Clock Loss Detector Disable  
When the system clock is inactive for approximately 100µs, the clock loss detector circuit detects the  
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.  
Setting the CDD bit disables this behaviour.  
MUTE MODES  
The device has various mute modes.  
DIGITAL FILTER  
ANALOGUE  
ANMUTE  
Asserted  
ANRES  
Reg bit OPE = 1’  
Unaffected  
MUTEB pin  
Gain ramped to zero  
Asserted when  
gain = 0  
On release volume ramps  
to previous value  
AUTOMUTE  
Automute has no effect on digital  
filters  
Asserted after  
1024 zero input  
samples if IZD = 1  
(detect 1024 zero  
input samples)  
Reg bit MUT  
As MUTEB pin  
As MUTEB pin  
Asserted  
Gain = 00  
Gain = -dB  
(left & right)  
RAM initialise  
Gain initialised to 0dB  
Asserted  
Asserted  
Loss of system  
clock  
Not running (no clock). On clock  
restart, filters initialised, RAM  
initialised. Registers unchanged  
Asserted  
Asserted  
No LRCLK or invalid  
SCLK/LRCLK ratio  
Filters initialised, RAM initialised.  
Registers unchanged  
Asserted  
RB  
Reset gain initialised to 0dB  
Asserted  
Asserted  
Asserted  
Asserted  
Power-on reset  
Table 21 Mute Modes  
Reset  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
14  
Advanced Information  
WM8740  
ANRES is the reset to the switched capacitor filter.  
ANMUTE is an analogue muting signal gating the analogue signal at the output (after  
the SC filter)  
AUTOMUTE is asserted when both the IZD register bit is asserted and the input audio  
data has been zero on both left and right channels for 1024 input samples. The first  
non-zero sample de-asserts.  
Applying a logic low to MUTEB or setting MUT in Reg2 causes the gain registers to  
ramp to zero. When a logic high is applied, the gain ramps slowly back up to the value  
held in the appropriate attenuation register (AL or AR). The ramp rate = 128/fs s/0.5dB  
step.  
If SOFTMUTE is set or  
MUTEB=0 then GAINL and  
GAINR are overridden to 00  
GAINL[0:7]  
Signal  
Processing  
GAINR[0:7]  
SOFTMUTE  
MUTEB  
gain ramps between  
previous and new gain  
setting  
Automute:  
Detect 1024  
zero input  
samples  
IZD  
OPE  
FREQ_INVALID  
INIT  
ANMUTE  
ZERO  
Figure 7 Mute Modes  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
15  
WM8740  
Advanced Information  
FILTER RESPONSES  
Figure 8 Digital Filter Response (Sharp Roll-off Mode)  
Figure 9 Digital Filter Response (Sharp Roll-off Mode)  
Figure 10 Digital Filter Response (Slow Roll-off Mode)  
Figure 11 Digital Filter Response (Slow Roll-off Mode)  
0
-20  
-40  
-60  
-80  
-100  
-120  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
2
Frequency (Fs)  
Figure 12 Digital Filter Response 128fs Mode (192kHz  
Sample Rate) Normal Mode Solid, Slow Mode Dashed  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
16  
Advanced Information  
WM8740  
1
0.8  
0.6  
0.4  
0.2  
0
1
0.8  
0.6  
0.4  
0.2  
0
-0.2  
-0.4  
-0.2  
-0.4  
0
10  
20  
30  
40  
50  
60  
0
10  
20  
30  
40  
50  
60  
Time (input samples)  
Time (input samples)  
Figure 13 Impulse Response (Normal Roll-off,  
no De-emphasis)  
Figure 14 Impulse Response (Slow Roll-off,  
no De-emphasis)  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
17  
WM8740  
Advanced Information  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD  
AVDD  
8
15  
9
DVDD  
AVDD  
AVDDR  
AVDDL  
+
C1  
C2  
7
20  
DGND  
+
C3  
C4  
C5  
C6  
DGND  
14  
10  
19  
16  
17  
AGND  
AGNDR  
AGNDL  
AGND  
28  
27  
26  
23  
22  
-
ML/I2S  
VOUTLN  
VOUTLP  
LEFT OUTPUT DATA  
+
MC/DM1  
MD/DM0  
CSB/IWO  
RSTB  
Software I/F or  
Hardware Control  
13  
12  
-
VOUTRN  
VOUTRP  
RIGHT OUTPUT DATA  
+
12  
6
MODE8X  
WM8740  
AVDD  
DIFFHW  
MODE  
R1  
24  
25  
21  
ZERO  
11  
18  
MUTEB  
VMIDR  
VMIDL  
+
C
C12  
+
11  
1
2
3
LRCIN  
DIN  
C9  
C10  
Audio Serial Data I/F  
System Clock Input  
BCKIN  
AGND  
5
SCLK  
Notes: 1. AGND and DGND should be connected as close to the WM8740 as possible.  
2. 2 to C5, C9 and C11 should be positioned as close to the WM8740 as possible.  
C
3. Capacitor type used can have a big effect on device performance. It is  
recommended that capacitors with very low ESR are used and that ceramics are  
either NPO or COG type material to achieve best performance from the WM8740.  
Figure 15 External Components Diagram  
RECOMMENDED EXTERNAL COMPONENTS VALUES  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1 and C6  
C2 to C5  
10µF  
0.1µF  
10µF  
0.1µF  
10µF  
10kΩ  
De-coupling for DVDD and AVDD.  
De-coupling for DVDD and AVDD.  
C7 and C8  
C9 and C11  
C10 and C12  
R1  
Output AC coupling caps to remove VMID DC level from outputs.  
Reference de-coupling capacitors for VMIDR and VMIDL.  
Resistor to AVDD for open drain output operation.  
Table 22 External Components Description  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
18  
Advanced Information  
WM8740  
SUGGESTED DIFFERENTIAL OUTPUT FILTER CIRCUIT  
Figure 16 Suggested Differential Output Filter Circuit  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
19  
WM8740  
Advanced Information  
PACKAGE DIMENSIONS  
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)  
DM007.B  
b
e
28  
15  
E1  
E
GAUGE  
PLANE  
1
14  
Θ
D
0.25  
c
L
A1  
A A2  
-C-  
C
0.10  
SEATING PLANE  
Dimensions  
(mm)  
NOM  
-----  
Symbols  
MIN  
-----  
MAX  
A
A1  
A2  
b
c
D
e
E
E1  
L
2.13  
0.25  
1.88  
0.38  
0.20  
10.50  
0.05  
1.62  
0.22  
0.09  
9.90  
-----  
1.75  
-----  
-----  
10.20  
0.65 BSC  
7.80  
7.40  
5.00  
0.63  
0o  
8.20  
5.60  
1.03  
8o  
5.30  
0.90  
4o  
θ
REF:  
JEDEC.95, MO-150  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.  
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.7 July 2000  
20  
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