WM8170
Product Preview Rev 1.0
SETTING THE MAXIMUM CONVERSION RATE
The maximum conversion rate of the ADC, S/H and PGA stages within the WM8170 are directly
related to the value of bias current at which the signal path operates. Within limits an increase in bias
current allows an increase in maximum conversion rate to be achieved. Inserting a resistor between
the ISET pin and AGND sets the value of bias current.
The value should be set to that recommended in Table 2 corresponding to the maximum conversion
rate at which the device is required to operate.
Note that the higher the value of RISET the lower the power consumption of the device will be.
RISET
22kW
20kW
17kW
15kW
MAX. CONVERSION RATE (MSPS)
12
15
18
21
Table 2 RISET vs Maximum Conversion Rate
BLACK LEVEL OFFSET CORRECTION CIRCUITRY
Unless compensated for, the analogue signal applied to the input of the ADC would contain
unacceptably high and variable DC offsets. The offsets consist of the sum of two principal
components. These are black level offsets in the output video from the CCD, which can be monitored
during optically black pixel phases, and offsets from the amplifiers in the analogue signal path of the
WM8170. These offsets would reduce the maximum dynamic range that the ADC can achieve and
can vary significantly with time and temperature. Additionally, any DC offsets in the signal path are
multiplied by the PGA gain, which can cause the internal amplifiers to limit, particularly if the gain is
at a high setting.
The DC correction circuitry within the WM8170 has two distinct modes of operation.
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Basic DC correction mode
Extended DC correction mode
The Basic mode is intended for applications where there is a large difference in the video DC value
on adjacent lines in the video stream.
The Extended mode is intended for continuous time video applications, where it is necessary to track
the video signal DC component without introducing any digital correction noise to the image. This
mode is recommended for most of the popular area array CCDs.
BASIC DC CORRECTION MODE
In the Basic DC correction mode, the DC offset correction is performed in two stages. There is an
analogue DC correction loop that removes the majority of the offset, and a digital clamp that removes
the rest. Applying a falling edge to the BLCENB digital input pin enables firstly the analogue
correction loop and then the digital correction circuitry. This correction circuitry is to be used during
periods when optically black pixels are being output from the CCD. The block diagram of the Basic
offset correction circuitry is shown in Figure 15.
ANALOGUE CORRECTION LOOP
The Analogue Correction Loop functions by comparing the output from the PGA during the optically
black video period with a DAC output voltage, derived from the ADC reference voltages, which
corresponds to a 10-bit code which is programmable between 0 and 255 (dec). This code is the
required TARGET for the WM8170 to output for optically black pixels. The output of the comparator,
sampled ANDUR times per analogue enable, controls an up/down counter, the contents of which
provide the input data to an 8-bit bipolar DAC. The output of this DAC is subtracted from the input of
the PGA such that the PGA output becomes closer to the TARGET value programmed. Using this
method the majority of any DC offset from either the input video signal, or the signal chain amplifiers
is removed.
The Analogue Correction Loop does not correct for DC offsets in the ADC or the comparator in the
feedback path, and is quantised, in terms of ADC codes, to the resolution of the 8-bit DAC, which
changes depending on the actual PGA gain set. Therefore the resulting output code from the ADC
during these optically black pixels will not be exactly equal to the TARGET value. The residual error
in the black level is corrected in the digital correction circuitry.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
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