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XWM8192

型号：

XWM8192

描述：

（88）位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ]

品牌：

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数：

24 页

PDF大小：

619 K

下载PDF手册
WM8192  
(8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser  
Product Preview, June 2000, Rev 1.0  
DESCRIPTION  
FEATURES  
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit ADC  
The WM8192 is a 16-bit analogue front end/digitiser IC  
which processes and digitises the analogue output signals  
from CCD sensors or Contact Image Sensors (CIS) at pixel  
sample rates of up to 6MSPS.  
6MSPS conversion rate  
Low power – 240mW typical  
5V single supply or 5V/3.3V dual supply operation  
Single or 3 channel operation  
Correlated double sampling  
The device includes three analogue signal processing  
channels each of which contains Reset Level Clamping,  
Correlated Double Sampling and Programmable Gain and  
Offset adjust functions. Three multiplexers allow single  
channel processing. The output from each of these  
channels is time multiplexed into a single high-speed 16-bit  
Analogue to Digital Converter. The digital output data is  
available in 8 or 4-bit wide multiplexed format.  
Programmable gain (8-bit resolution)  
Programmable offset adjust (8-bit resolution)  
Programmable clamp voltage  
8 or 4-bit wide multiplexed data output formats  
Internally generated voltage references  
28-pin SOIC package  
An internal 4-bit DAC is supplied for internal reference level  
generation. This may be used during CDS to reference CIS  
signals or during Reset Level Clamping to clamp CCD  
signals. An external reference level may also be supplied.  
ADC references are generated internally, ensuring optimum  
performance from the device.  
Serial control interface  
APPLICATIONS  
•
•
•
•
Flatbed and sheetfeed scanners  
USB compatible scanners  
Using an analogue supply voltage of 5V and a digital  
interface supply of either 5V or 3.3V, the WM8192 typically  
only consumes 240mW when operating from a single  
5V supply.  
Multi-function peripherals  
High-performance CCD sensor interface  
BLOCK DIAGRAM  
VRLC/VBIAS  
(26)  
VSMP MCLK  
(5) (7)  
AVDD DVDD1 DVDD2  
VRT VRX VRB  
(24) (25) (23)  
(21)  
(3)  
(10)  
CL  
RS VS  
TIMING CONTROL  
WM8192  
VREF/BIAS  
R
8
M
U
X
OFFSET  
DAC  
(4) OEB  
G
B
RINP (1)  
RLC  
RLC  
CDS  
CDS  
+
PGA  
+
+
M
U
X
I/P SIGNAL  
POLARITY  
ADJUST  
R
G
B
8
(13) OP[0]  
(14) OP[1]  
(15) OP[2]  
(16) OP[3]  
(17) OP[4]  
(18) OP[5]  
(19) OP[6]  
(20) OP[7]/SDO  
M
U
X
DATA  
I/O  
PORT  
16-  
BIT  
ADC  
M
U
X
GINP (28)  
BINP (27)  
+
+
PGA  
8
OFFSET  
DAC  
8
I/P SIGNAL  
POLARITY  
ADJUST  
RLC  
CDS  
PGA  
+
8
OFFSET  
DAC  
8
I/P SIGNAL  
POLARITY  
ADJUST  
(9) SEN  
(12) SCK  
(11) SDI  
CONFIGURABLE  
SERIAL  
CONTROL  
RLC  
DAC  
4
INTERFACE  
(6) RLC/ACYC  
(8)  
DGND  
(22)  
AGND1  
(2)  
AGND2  
Product Preview data sheets contain  
specifications for products in the formative  
WOLFSON MICROELECTRONICS LTD  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
http://www.wolfson.co.uk  
phase of development. These products may  
be changed or discontinued without notice.  
2000 Wolfson Microelectronics Ltd.  
WM8192  
Product Preview  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
RINP  
1
2
28  
27  
GINP  
BINP  
XWM8192CDW/V  
0 to 70oC  
28-pin SOIC  
AGND2  
DVDD1  
OEB  
3
4
5
6
7
8
26  
25  
24  
23  
22  
21  
VRLC/VBIAS  
VRX  
VSMP  
VRT  
RLC/ACYC  
MCLK  
VRB  
AGND1  
AVDD  
DGND  
SEN  
DVDD2  
SDI  
9
20  
19  
18  
17  
16  
15  
OP[7]/SDO  
OP[6]  
10  
11  
12  
13  
14  
OP[5]  
SCK  
OP[4]  
OP[0]  
OP[1]  
OP[3]  
OP[2]  
PIN DESCRIPTION  
PIN  
1
NAME  
RINP  
TYPE  
DESCRIPTION  
Analogue input  
Supply  
Red channel input video.  
Analogue ground (0V).  
2
AGND2  
DVDD1  
3
Supply  
Digital supply (5V) for logic and clock generator. This must be operated at the same  
potential as AVDD.  
4
5
6
OEB  
VSMP  
Digital input  
Digital input  
Digital input  
Output Hi-Z control, all digital outputs disabled when OEB = 1.  
Video sample synchronisation pulse.  
RLC/ACYC  
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if  
used on every pixel. ACYC autocycles between R, G, B inputs.  
7
MCLK  
Digital input  
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or  
any multiple of 2 thereafter depending on input sample mode).  
8
DGND  
SEN  
Supply  
Digital ground (0V).  
9
Digital input  
Supply  
Enables the serial interface when high.  
Digital supply (5V/3.3V), all digital I/O pins.  
Serial data input.  
10  
11  
12  
DVDD2  
SDI  
Digital input  
Digital input  
SCK  
Serial clock.  
Digital multiplexed output data bus.  
ADC output data (d15:d0) is available in two multiplexed formats as shown, under  
the control of register bit MUXOP.  
See ‘Output Formats’ description in Device Description section for further details.  
8+8-bit  
4+4+4+4-bit  
A
B
A
B
C
D
13  
14  
15  
16  
17  
18  
19  
20  
OP[0]  
OP[1]  
OP[2]  
OP[3]  
OP[4]  
OP[5]  
OP[6]  
OP[7]  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
Digital output  
d8  
d0  
d1  
d2  
d3  
d4  
d5  
d6  
d7  
d9  
d10  
d11  
d12  
d13  
d14  
d15  
d12  
d13  
d14  
d15  
d8  
d9  
d4  
d5  
d6  
d7  
d0  
d1  
d2  
d3  
d10  
d11  
Alternatively, pin OP[7]/SDO may be used to output register read-back data when  
OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device  
Description section for further details.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
2
Product Preview  
WM8192  
PIN  
21  
NAME  
TYPE  
Supply  
Supply  
DESCRIPTION  
AVDD  
AGND1  
VRB  
Analogue supply (5V). This must be operated at the same potential as DVDD1.  
Analogue ground (0V).  
22  
23  
Analogue output Lower reference voltage.  
This pin must be connected to AGND via a decoupling capacitor.  
Analogue output Upper reference voltage.  
This pin must be connected to AGND via a decoupling capacitor.  
Analogue output Input return bias voltage.  
This pin must be connected to AGND via a decoupling capacitor.  
24  
25  
26  
VRT  
VRX  
VRLC/VBIAS  
Analogue I/O  
Selectable analogue output voltage for RLC or single-ended bias reference.  
This pin would typically be connected to AGND via a decoupling capacitor.  
VRLC can be externally driven if programmed Hi-Z.  
27  
28  
BINP  
GINP  
Analogue input  
Analogue input  
Blue channel input video.  
Green channel input video.  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at  
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified.  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible  
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage  
of this device.  
As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount  
assembly. It is anticipated as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture  
barrier bags.  
CONDITION  
MIN  
MAX  
Analogue supply voltage: AVDD  
Digital supply voltages: DVDD1 − 2  
Digital ground: DGND  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND - 0.3V  
GND + 7V  
GND + 7V  
GND + 0.3V  
GND + 0.3V  
DVDD2 + 0.3V  
AVDD + 0.3V  
AVDD + 0.3V  
Analogue grounds: AGND1 − 2  
Digital inputs, digital outputs and digital I/O pins  
Analogue inputs (RINP, GINP, BINP)  
Other pins  
°
°
Operating temperature range: TA  
Storage temperature  
0 C  
+70 C  
°
°
-65 C  
+150 C  
°
Package body temperature (soldering, 10 seconds)  
Package body temperature (soldering, 2 minutes)  
Notes:  
+240 C  
+183°C  
1.  
2.  
GND denotes the voltage of any ground pin.  
AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages  
between these pins will degrade performance.  
RECOMMENDED OPERATING CONDITIONS  
CONDITION  
SYMBOL  
TA  
MIN  
0
TYP  
MAX  
70  
UNITS  
Operating temperature range  
Analogue supply voltage  
Digital core supply voltage  
Digital I/O supply voltage  
°C  
V
AVDD  
DVDD1  
4.75  
4.75  
5.0  
5.0  
5.25  
5.25  
V
5V I/O  
DVDD2  
DVDD2  
4.75  
2.97  
5.0  
3.3  
5.25  
3.63  
V
V
3.3V I/O  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
3
WM8192  
Product Preview  
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST  
MIN  
TYP  
MAX  
UNIT  
CONDITIONS  
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)  
Full-scale input voltage range  
(see Note 1)  
Max Gain  
Min Gain  
0.4  
Vp-p  
Vp-p  
V
4.08  
Input signal limits (see Note 2)  
Full-scale transition error  
VIN  
0
AVDD  
Gain = 0dB;  
PGA[7:0] = 4B(hex)  
20  
20  
mV  
Zero-scale transition error  
Gain = 0dB;  
mV  
PGA[7:0] = 4B(hex)  
Differential non-linearity  
DNL  
INL  
TBD  
TBD  
1
LSB  
LSB  
%
Integral non-linearity  
Channel to channel gain matching  
References  
Upper reference voltage  
VRT  
VRB  
VRX  
VRTB  
2.85  
1.35  
0.65  
1.5  
V
V
V
V
Ω
Lower reference voltage  
Input return bias voltage  
Diff. reference voltage (VRT-VRB)  
Output resistance VRT, VRB, VRX  
VRLC/Reset-Level Clamp (RLC)  
RLC switching impedance  
VRLC short-circuit current  
VRLC output resistance  
1
50  
5
Ω
mA  
Ω
2
VRLC Hi-Z leakage current  
RLCDAC resolution  
VRLC = 0 to AVDD  
1
µA  
4
bits  
V/step  
V/step  
V
RLCDAC step size, RLCDAC = 0  
RLCDAC step size, RLCDAC = 1  
VRLCSTEP  
VRLCSTEP  
VRLCBOT  
0.24  
0.16  
0.40  
RLCDAC output voltage at  
code 0(hex), RLCDACRNG = 0  
RLCDAC output voltage at  
code 0(hex), RLCDACRNG = 1  
VRLCBOT  
VRLCTOP  
VRLCTOP  
0.25  
4.20  
2.85  
V
V
RLCDAC output voltage at  
code F(hex) RLCDACRNG, = 0  
RLCDAC output voltage at  
V
code F(hex), RLCDACRNG = 1  
VRLC deviation  
-50  
+50  
mV  
Offset DAC, Monotonicity Guaranteed  
Resolution  
8
bits  
LSB  
Differential non-linearity  
Integral non-linearity  
Step size  
DNL  
INL  
0.1  
0.5  
1
0.25  
2.04  
-260  
+260  
LSB  
mV/step  
mV  
Output voltage  
Code 00(hex)  
Code FF(hex)  
mV  
Notes:  
1.  
2.  
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.  
Input signal limits are the limits within which the full-scale input voltage signal must lie.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
4
Product Preview  
WM8192  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST  
MIN  
TYP  
MAX  
UNIT  
CONDITIONS  
Programmable Gain Amplifier  
Resolution  
Gain  
8
208  
bits  
V/V  
283 − PGA[7 : 0]  
Max gain, each channel  
Min gain, each channel  
Gain error, each channel  
DIGITAL SPECIFICATIONS  
Digital Inputs  
GMAX  
GMIN  
7.4  
0.74  
1
V/V  
V/V  
%
High level input voltage  
Low level input voltage  
High level input current  
Low level input current  
Input capacitance  
VIH  
VIL  
IIH  
0.8 DVDD2  
V
0.2 DVDD2  
V
1
1
µA  
µA  
pF  
IIL  
CI  
5
Digital Outputs  
High level output voltage  
Low level output voltage  
High impedance output current  
Digital IO Pins  
VOH  
VOL  
IOZ  
IOH = 1mA  
IOL = 1mA  
DVDD2 - 0.5  
V
V
0.5  
1
µA  
Applied high level input voltage  
Applied low level input voltage  
High level output voltage  
Low level output voltage  
Low level input current  
High level input current  
Input capacitance  
VIH  
VIL  
VOH  
VOL  
IIL  
0.8 DVDD2  
DVDD2 - 0.5  
V
V
0.2 DVDD2  
IOH = 1mA  
IOL = 1mA  
V
0.5  
1
V
µA  
µA  
pF  
µA  
IIH  
1
CI  
5
High impedance output current  
Supply Currents  
IOZ  
1
Total supply current − active  
48  
45  
mA  
mA  
Total analogue supply current −  
IAVDD  
active  
Digital core supply current,  
DVDD1 − active  
2
1
mA  
mA  
µA  
Digital I/O supply current,  
DVDD2 − active  
Supply current − full power down  
100  
mode  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
5
WM8192  
Product Preview  
INPUT VIDEO SAMPLING  
tPER  
tMCLKH tMCLKL  
MCLK  
tVSMPH  
tVSMPSU  
VSMP  
INPUT  
tVSU  
tVH  
tRSU  
tRH  
VIDEO  
Figure 1 Input Video Timing  
Note:  
1.  
See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
MCLK period  
tPER  
83.3  
ns  
MCLK high period  
MCLK low period  
VSMP set-up time  
VSMP hold time  
tMCLKH  
tMCLKL  
tVSMPSU  
tVSMPH  
tVSU  
37.5  
37.5  
10  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Video level set-up time  
Video level hold time  
Reset level set-up time  
Reset level hold time  
Notes:  
15  
5
tVH  
tRSU  
15  
5
tRH  
1.  
2.  
tVSU and tRSU denote the set-up time required after the input video signal has settled.  
Parameters are measured at 50% of the rising/falling edge.  
OUTPUT DATA TIMING  
MCLK  
tPD  
OP[7:0]  
Figure 2 Output Data Timing  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
6
Product Preview  
WM8192  
OEB  
tPZE  
tPEZ  
OP[7:0]  
Hi-Z  
Hi-Z  
Figure 3 Output Data Enable Timing  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated  
PARAMETER  
SYMBOL  
tPD  
TEST CONDITIONS  
MIN  
TYP  
MAX  
75  
UNITS  
ns  
Output propagation delay  
Output enable time  
Output disable time  
IOH = 1mA, IOL = 1mA  
tPZE  
50  
ns  
tPEZ  
25  
ns  
SERIAL INTERFACE  
tSPER  
tSCKL tSCKH  
SCK  
tSSU  
tSH  
SDI  
SEN  
SDO  
tSCE  
tSEW tSEC  
tSCRDZ  
tSERD  
tSCRD  
ADC  
DATA  
ADC DATA  
MSB  
LSB  
REGISTER DATA  
Figure 4 Serial Interface Timing  
Test Conditions  
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
SCK period  
tSPER  
83.3  
ns  
SCK high  
tSCKH  
tSCKL  
tSSU  
37.5  
37.5  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK low  
SDI set-up time  
SDI hold time  
tSH  
10  
SCK to SEN set-up time  
SEN to SCK set-up time  
SEN pulse width  
tSCE  
20  
tSEC  
20  
tSEW  
tSERD  
tSCRD  
tSCRDZ  
50  
SEN low to SDO = Register data  
SCK low to SDO = Register data  
SCK low to SDO = ADC data  
35  
35  
25  
Note:  
1.  
Parameters are measured at 50% of the rising/falling edge  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
7
WM8192  
Product Preview  
DEVICE DESCRIPTION  
INTRODUCTION  
A block diagram of the device showing the signal path is presented on Page 1.  
The WM8192 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then  
processes the sampled video signal with respect to the video reset level or an internally/externally  
generated reference level using either one or three processing channels.  
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping  
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit  
Programmable Gain Amplifier (PGA).  
The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from  
the ADC is presented on an 8-bit wide bi-directional bus, with optional 8 or 4-bit multiplexed formats.  
On-chip control registers determine the configuration of the device, including the offsets and gains  
applied to each channel. These registers are programmable via a serial interface.  
INPUT SAMPLING  
The WM8192 can sample and process one to three inputs through one or three processing channels  
as follows:  
Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for  
each pixel and a separate channel processes each input. The signals are then multiplexed into the  
ADC, which converts all three inputs within the pixel period.  
Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the  
corresponding channel, and converted by the ADC. The choice of input and channel can be changed  
via the control interface, e.g. on a line-by-line basis if required.  
Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into  
the red channel for processing before being converted by the ADC. The input selected can be  
switched in turn (RINP → GINP → BINP → RINP…) together with the PGA and Offset DAC control  
registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling  
sequences can be generated via the control registers. This mode causes the blue and green  
channels to be powered down. Refer to the Line-by-Line Operation section for more details.  
RESET LEVEL CLAMPING (RLC)  
To ensure that the signal applied to the WM8192 lies within its input range (0V to AVDD) the CCD  
output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the  
WM8192 side of this capacitor to a suitable voltage during the CCD reset period.  
A typical input configuration is shown in Figure 5. A clamp pulse, CL, is generated from MCLK and  
VSMP by the Timing Control Block. When CL is active the voltage on the WM8192 side of CIN, at  
RINP, is forced to the VRLC/VBIAS voltage (VVRLC ) by switch 1. When the CL pulse turns off, the  
voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset  
to video level) will couple through CIN to RINP.  
RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to  
the CDS/non-CDS Processing section.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
8
Product Preview  
WM8192  
RLC/ACYC MCLK VSMP  
TIMING CONTROL  
FROM CONTROL  
INTERFACE  
CL  
RS  
VS  
CIN  
S/H  
+
-
TO OFFSET DAC  
+
RINP  
2
S/H  
1
RLC  
CDS  
INPUT SAMPLING  
BLOCK FOR RED  
CHANNEL  
EXTERNAL VRLC  
CDS  
VRLC/  
VBIAS  
4-BIT  
RLC DAC  
FROM CONTROL  
INTERFACE  
VRLCEXT  
Figure 5 Reset Level Clamping and CDS Circuitry  
If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 6 illustrates control of  
RLC for a typical CCD waveform, with CL applied during the reset period.  
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during  
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal  
CL pulse on the next reset level. The position of CL can be adjusted by using control bits  
CDSREF[1:0] (Figure 7).  
If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit  
RLCINT determines whether clamping is applied.  
MCLK  
VSMP  
1
X
X
0
X
X
0
RLC/ACYC  
Programmable Delay  
CL  
(CDSREF = 01)  
INPUT VIDEO  
RGB  
RGB  
RGB  
No RLC on this Pixel  
RLC on this Pixel  
Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL  
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits  
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit  
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit  
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.  
CDS/NON-CDS PROCESSING  
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel  
common mode noise. For CDS operation, the video level is processed with respect to the video reset  
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must  
be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from  
the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by  
programming control bits CDSREF[1:0], as shown in Figure 7.  
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MCLK  
VSMP  
VS  
RS/CL (CDSREF = 00)  
RS/CL (CDSREF = 01)  
RS/CL (CDSREF = 10)  
RS/CL (CDSREF = 11)  
Figure 7 Reset Sample and Clamp Timing  
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed  
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described  
above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this  
mode.  
OFFSET ADJUST AND PROGRAMMABLE GAIN  
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset  
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each  
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].  
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order  
(Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,  
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.  
ADC INPUT BLACK LEVEL ADJUST  
The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going  
input signals, a black level (zero differential) output from the PGA should be offset to the top of the  
ADC range. For positive going input signal the black level should be offset to the bottom of the ADC  
range. This is achieved by writing to control bits PGAFS[1:0].  
OVERALL SIGNAL FLOW SUMMARY  
Figure 8 represents the processing of the video signal through the WM8192.  
OUTPUT  
INVERT  
BLOCK  
INPUT  
SAMPLING  
BLOCK  
OFFSET DAC PGA  
ADC BLOCK  
BLOCK  
BLOCK  
D2  
x (65535/VFS  
)
V1  
V2  
V3  
D1  
+0  
if PGAFS[1:0]=11  
X
+65535 if PGAFS[1:0]=10  
+32768 if PGAFS[1:0]=0x  
OP[7:0]  
+
+
VIN  
digital  
analog  
+
-
CDS = 1  
CDS = 0  
D2 = D1 if INVOP = 0  
D2 = 65535-D1 if INVOP = 1  
VRESET  
PGA gain  
A = 208/(283-PGA[7:0])  
VVRLC  
Offset  
DAC  
260mV*(DAC[7:0]-127.5)/127.5  
VIN is RINP or GINP or BINP  
RESET is VIN sampled during reset clamp  
VRLC is voltage applied to VRLC pin  
V
RLCEXT=1  
RLCEXT=0  
CDS, RLCEXT,RLCV[3:0], DAC[7:0],  
PGA[7:0], PGAFS[1:0] and INVOP are set  
by programming internal control registers.  
CDS=1 for CDS, 0 for non-CDS  
RLC  
DAC  
See parametrics for  
DAC voltages.  
Figure 8 Overall Signal Flow  
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WM8192  
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the  
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the  
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC  
,
optionally set via the RLC DAC.  
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the  
black level of the input signal towards 0V, producing V2.  
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,  
outputting voltage V3.  
The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.  
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.  
CALCULATING OUTPUT FOR ANY GIVEN INPUT  
The following equations describe the processing of the video and reset level signals through  
the WM8192.  
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING  
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the  
input video.  
V1  
=
VIN - VRESET .................................................................. Eqn. 1  
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted  
instead.  
V1  
=
VIN - VVRLC .................................................................... Eqn. 2  
If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.  
If RLCEXT = 0, VVRLC is the output from the internal RLC DAC.  
VVRLC  
=
(VRLCSTEP RLCV[3:0]) + VRLCBOT ................................. Eqn. 3  
V
RLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.  
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST  
The resultant signal V1 is added to the Offset DAC output.  
V2  
=
V1 + {260mV (DAC[7:0]-127.5) } / 127.5 .................... Eqn. 4  
PGA NODE: GAIN ADJUST  
The signal is then multiplied by the PGA gain,  
V3  
=
V2 208/(283- PGA[7:0]) .............................................. Eqn. 5  
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION  
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by  
PGAFS[1:0].  
D1[15:0] = INT{ (V3 /VFS  
D1[15:0] = INT{ (V3 /VFS  
D1[15:0] = INT{ (V3 /VFS  
)
)
)
65535} + 32767 PGAFS[1:0] = 00 or 01 ..... Eqn. 6  
65535} PGAFS[1:0] = 11 .............. Eqn. 7  
65535} + 65535 PGAFS[1:0] = 10 .............. Eqn. 8  
where the ADC full-scale range, VFS = 3V  
OUTPUT INVERT BLOCK: POLARITY ADJUST  
The polarity of the digital output may be inverted by control bit INVOP.  
D2[15:0] = D1[15:0]  
(INVOP = 0) ...................... Eqn. 9  
(INVOP = 1) ...................... Eqn. 10  
D2[15:0] = 61535 – D1[15:0]  
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OUTPUT FORMATS  
The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by  
setting control bit MUXOP. Latency of valid output data with respect to VSMP is programmable by  
writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing  
Diagrams section.  
Figure 9 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 10 shows the output data  
formats for Mode 3. Table 1 summarises the output data obtained for each format.  
MCLK  
MCLK  
8+8-BIT  
OUTPUT  
8+8-BIT  
OUTPUT  
A
B
A
B
4+4+4+4-BIT  
OUTPUT  
4+4+4+4-BIT  
OUTPUT  
A
B
C
D
A B A B C  
D
Figure 9 Output Data Formats  
Figure 10 Output Data Formats  
(Mode 3)  
(Modes 1 − 2, 4 − 6)  
OUTPUT  
FORMAT  
MUXOP  
OUTPUT  
PINS  
OUTPUT  
8+8-bit  
multiplexed  
0
1
OP[7:0]  
A = d15, d14, d13, d12, d11, d10, d9, d8  
B = d7, d6, d5, d4, d3, d2, d1,d0  
4+4+4+4-bit  
(nibble)  
OP[7:4]  
A = d15, d14, d13, d12  
B = d11, d10, d9, d8  
C = d7, d6, d5, d4  
D = d3, d2, d1, d0  
Table 1 Details of Output Data Shown in Figure 9 and Figure 10.  
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WM8192  
CONTROL INTERFACE  
The internal control registers are programmable via the serial digital control interface. The register  
contents can be read back via the serial interface on pin OP[7]/SDO.  
SERIAL INTERFACE: REGISTER WRITE  
Figure 11 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit  
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data  
word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.  
When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the  
appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.  
SCK  
a5  
0
a3  
a2  
a1  
a0  
b7  
b6  
b5  
b4  
b3  
b2  
b1  
b0  
SDI  
Address  
Data Word  
SEN  
Figure 11 Serial Interface Register Write  
SERIAL INTERFACE: REGISTER READ-BACK  
Figure 12 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus  
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing  
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of  
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge  
of SCK). Note that pin SDO is shared with an output pin, OP[7], therefore OEB should always be  
held low when register read-back data is expected on this pin. The next word may be read in to SDI  
while the previous word is still being output on SDO.  
SCK  
a5  
1
a3 a2 a1 a0  
x
x
x
x
x
x
x
x
SDI  
Address  
Data Word  
SEN  
SDO/  
OP[7]  
d7 d6 d5 d4 d3 d2 d1 d0  
Output Data Word  
OEB  
Figure 12 Serial Interface Register Read-back  
TIMING REQUIREMENTS  
To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock  
(VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces  
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum  
sample rates for the various modes are shown in Table 4.  
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PROGRAMMABLE VSMP DETECT CIRCUIT  
The VSMP input is used to determine the sampling point and frequency of the WM8192. Under  
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling  
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on  
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal  
may not be readily available. The programmable VSMP detect circuit in the WM8192 allows the  
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register  
clock, when applied to the VSMP pin.  
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge  
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.  
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.  
Figure 13 shows the internal VSMP pulses that can be generated by this circuit for a typical clock  
input signal. The internal VSMP pulse is then applied to the timing control block in place of the  
normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising  
MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.  
MCLK  
INPUT  
PINS  
VSMP  
POSNNEG = 1  
(VDEL = 000) INTVSMP  
(VDEL = 001) INTVSMP  
(VDEL = 010) INTVSMP  
(VDEL = 011) INTVSMP  
(VDEL = 100) INTVSMP  
(VDEL = 101) INTVSMP  
(VDEL = 110) INTVSMP  
(VDEL = 111) INTVSMP  
POSNNEG = 0  
(VDEL = 000) INTVSMP  
(VDEL = 001) INTVSMP  
(VDEL = 010) INTVSMP  
(VDEL = 011) INTVSMP  
(VDEL = 100) INTVSMP  
(VDEL = 101) INTVSMP  
(VDEL = 110) INTVSMP  
(VDEL = 111) INTVSMP  
Figure 13 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit  
REFERENCES  
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins  
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and  
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin  
VRLC/VBIAS  
POWER SUPPLY  
The WM8192 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)  
supplies.  
POWER MANAGEMENT  
Power management for the device is performed via the Control Interface. The device can be powered  
on or off completely by the EN bit. Alternatively, when control bit SELPD is high, only blocks selected  
by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power  
dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery  
into a fully active state. In Line-by-line operation, the green and blue channel PGAs are automatically  
powered down.  
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WM8192  
All the internal registers maintain their previously programmed value in power down modes and the  
Control Interface inputs remain active. Table 2 summarises the power down control bit functions.  
EN  
0
SELDPD  
0
0
1
Device completely powers down.  
1
Device completely powers up.  
X
Blocks with respective SELDIS[3:0] bit high are disabled.  
Table 2 Power Down Control  
LINE-BY-LINE OPERATION  
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a  
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to  
accommodate this type of signal the WM8192 can be set into Monochrome mode, with the input  
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8192  
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is  
set the green and blue processing channels are powered down and the device is forced internally to  
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.  
Figure 14 shows the signal path when operating in colour line-by-line mode.  
VRLC/VBIAS  
VSMP  
MCLK  
CL  
RS VS TIMING CONTROL  
WM8192  
R
8
OFFSET  
MUX  
OFFSET  
DAC  
G
B
16-  
BIT  
ADC  
DATA  
I/O  
PORT  
RINP  
RLC  
RLC  
RLC  
CDS  
+
PGA  
8
+
OP[7:0]  
INPUT  
MUX  
R
G
B
I/P SIGNAL  
POLARITY  
ADJUST  
PGA  
MUX  
GINP  
BINP  
SEN  
CONFIGURABLE  
SERIAL  
SCK  
CONTROL  
INTERFACE  
SDI  
RLC  
DAC  
4
RLC/ACYC  
Figure 14 Signal Path When in Line-by-Line Mode  
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-  
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.  
The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively,  
all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to  
select the desired colour. It is also possible for the input multiplexer to be controlled separately from  
the PGA and Offset multiplexers. Table 3 describes all the multiplexer selection modes that are  
possible.  
FME ACYCNRLC  
NAME  
Internal,  
no force mux  
DESCRIPTION  
0
0
1
0
1
0
Input mux, offset and gain registers determined by  
internal register bits INTM1, INTM0.  
Auto-cycling,  
no force mux  
Input mux, offset and gain registers auto-cycled, RINP  
→ GINP → BINP → RINP… on RLC/ACYC pulse.  
Internal,  
Input mux selected from internal register bits FM1, FM0;  
force mux  
Offset and gain registers selected from internal register  
bits INTM1, INTM0.  
1
1
Auto-cycling,  
force mux  
Input mux selected from internal register bits FM1, FM0;  
Offset and gain registers auto-cycled, RINP → GINP →  
BINP → RINP… on RLC/ACYC pulse.  
Table 3 Colour Selection Description in Line-by-Line Mode  
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OPERATING MODES  
Table 4 summarises the most commonly used modes, the clock waveforms required and the register  
contents required for CDS and non-CDS operation.  
MODE  
DESCRIPTION  
CDS  
MAX  
SENSOR  
INTERFACE  
DESCRIPTION  
TIMING  
REQUIRE-  
MENTS  
REGISTER  
CONTENTS  
WITH CDS  
REGISTER  
CONTENTS  
WITHOUT  
CDS  
AVAILABLE SAMPLE  
RATE  
1
Colour  
Pixel-by-Pixel  
Yes  
2MSPS  
The 3 input channels  
are sampled in  
MCLK max  
= 12MHz  
SetReg1:  
03(hex)  
SetReg1:  
01(hex)  
parallel. The signal is  
then gain and offset  
adjusted before being  
multiplexed into a  
single data stream  
and converted by the  
ADC, giving an output  
data rate of 6MSPS  
max.  
MCLK:  
VSMP  
ratio is 6:1  
2
3
Monochrome/  
Colour  
Line-by-Line  
Yes  
Yes  
2MSPS  
4MSPS  
As mode 1 except:  
Only one input  
channel at a time  
is continuously  
sampled.  
MCLK max  
= 12MHz  
SetReg1:  
07(hex)  
SetReg1:  
05(hex)  
MCLK:  
VSMP  
ratio is 6:1  
Fast  
Monochrome/  
Colour  
Identical to mode 2  
MCLK max  
= 12MHz  
Identical to  
mode 2 plus  
SetReg3:  
bits 5:4 must  
be set to  
Identical to  
mode 2  
MCLK:  
VSMP  
ratio is 3:1  
Line-by-Line  
0(hex)  
4
5
Maximum  
speed  
Monochrome/  
Colour  
No  
6MSPS  
Identical to mode 2  
Identical to mode 1  
MCLK max  
= 12MHz  
CDS not  
possible  
SetReg1:  
45(hex)  
MCLK:  
VSMP  
ratio is 2:1  
Line-by-Line  
Slow Colour  
Pixel-by-Pixel  
Yes  
1.5MSPS  
MCLK max  
= 12MHz  
Identical to  
mode 1  
Identical to  
mode 1  
MCLK:  
VSMP  
ratio is  
2n:1, n ≥ 4  
6
Slow  
Monochrome/  
Colour  
Yes  
1.5MSPS  
Identical to mode 2  
MCLK max  
= 12MHz  
Identical to  
mode 2  
Identical to  
mode 2  
MCLK:  
VSMP  
Line-by-Line  
ratio is  
2n:1, n ≥ 4  
Table 4 WM8192 Operating Modes  
Notes:  
1.  
2.  
In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled.  
For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection  
Description in Line-by-Line Mode.  
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WM8192  
OPERATING MODE TIMING DIAGRAMS  
The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video  
requirements for operation of the most commonly used modes as shown in Table 4. The diagrams  
are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown  
as R, G and B respectively. X denotes invalid data.  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
OP[7:0]  
(DEL = 00)  
RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB  
BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB  
GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB  
RA RB GA GB BA BB RA RB GA GB BA BB RA RB GB GA BA BB RA RB GA GB BA BB RA RB GA GB BA BB  
OP[7:0]  
(DEL = 01)  
OP[7:0]  
(DEL = 10)  
OP[7:0]  
(DEL = 11)  
Figure 15 Mode 1 Operation  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
RA  
RB  
X
RA  
X
RB  
X
RA  
X
RB  
X
RA  
X
RB  
X
RA  
X
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP[7:0] (DEL = 00)  
OP[7:0] (DEL = 01)  
OP[7:0] (DEL = 10)  
OP[7:0] (DEL = 11)  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
X
X
RA  
X
RB  
X
RA  
X
RB  
X
RA  
X
RB  
X
RA  
X
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
Figure 16 Mode 2 Operation  
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23.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
OP[7:0]  
(DEL = 00)  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
OP[7:0]  
(DEL = 01)  
OP[7:0]  
(DEL = 10)  
OP[7:0]  
(DEL = 11)  
Figure 17 Mode 3 Operation  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
OP[7:0]  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RB  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RB  
RA  
RB  
RA  
RB  
(DEL = 00)  
OP[7:0]  
(DEL = 01)  
RA  
RA  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RA  
RA  
RA  
RA  
RA  
RA  
RB  
RB  
RB  
RA  
RA  
RA  
RB  
RB  
RB  
OP[7:0]  
(DEL = 10)  
OP[7:0]  
(DEL = 11)  
Figure 18 Mode 4 Operation  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
18  
Product Preview  
WM8192  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT  
VIDEO  
OP[7:0]  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB  
X
X
X
X
X
X
X
X
(DEL = 00)  
OP[7:0]  
BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB  
X
X
X
X
X
X
X
X
(DEL = 01)  
OP[7:0]  
GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
X
X
X
X
X
X
X
X
(DEL = 10)  
OP[7:0]  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
RA RB GA GB BA BB  
X
X
X
X
X
X
(DEL = 11)  
Figure 19 Mode 5 Operation (MCLK:VSMP Ratio = 8:1)  
16.5 MCLK PERIODS  
MCLK  
VSMP  
INPUT VIDEO  
OP[7:0]  
(DEL = 00)  
RA  
X
RB  
X
RA  
X
RB  
X
RA  
X
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP[7:0]  
(DEL = 01)  
RA  
RB  
RA  
RB  
X
RA  
RB  
OP[7:0]  
(DEL = 10)  
RA  
RB  
RA  
RB  
RA  
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OP[7:0]  
RA  
RB  
RA  
RB  
RA  
RB  
RA  
RB  
X
X
X
X
X
X
X
X
X
X
X
X
X
(DEL = 11)  
Figure 20 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
19  
WM8192  
Product Preview  
DEVICE CONFIGURATION  
REGISTER MAP  
The following table describes the location of each control bit used to determine the operation of the  
WM8192. The register map is programmed by writing the required codes to the appropriate  
addresses via the serial interface.  
ADDRESS  
<a5:a0>  
DESCRIPTION  
DEF  
RW  
BIT  
(hex)  
b7  
b6  
b5  
b4  
PGAFS[0]  
0
b3  
b2  
b1  
b0  
EN  
000001  
000010  
000011  
000100  
000101  
000110  
000111  
001000  
001001  
001010  
001011  
001100  
100000  
100001  
Setup Reg 1  
Setup Reg 2  
Setup Reg 3  
Software Reset  
Auto-cycle Reset  
Setup Reg 4  
Revision Number  
Setup Reg 5  
Setup Reg 6  
Reserved  
03  
20  
1F  
00  
00  
00  
41  
00  
00  
00  
00  
00  
80  
80  
RW  
RW  
RW  
W
MODE4  
DEL[0]  
PGAFS[1]  
SELPD  
MONO  
INVOP  
RLCV[2]  
CDS  
DEL[1]  
RLCDACRNG  
CDSREF [1]  
VRLCEXT  
RLCV[3]  
MUXOP  
RLCV[1]  
0
CHAN[1] CHAN[0]  
CDSREF [0]  
RLCV[0]  
W
RW  
R
FM[1]  
FM[0]  
INTM[1]  
INTM[0]  
RLCINT  
FME  
ACYCNRLC  
LINEBYLINE  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
0
0
POSNNEG  
VDEL[2]  
VDEL[1]  
VDEL[0]  
VSMPDET  
0
0
0
0
SELDIS[3]  
SELDIS[2]  
SELDIS[1]  
SELDIS[0]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved  
Reserved  
0
0
0
0
0
0
0
0
DAC Value (Red)  
DAC[7]  
DAC[7]  
DAC[6]  
DAC[6]  
DAC[5]  
DAC[5]  
DAC[4]  
DAC[4]  
DAC[3]  
DAC[3]  
DAC[2]  
DAC[2]  
DAC[1]  
DAC[1]  
DAC[0]  
DAC[0]  
DAC Value  
(Green)  
100010  
100011  
101000  
101001  
DAC Value (Blue)  
DAC Value (RGB)  
PGA Gain (Red)  
80  
80  
00  
00  
RW  
W
DAC[7]  
DAC[7]  
PGA[7]  
PGA[7]  
DAC[6]  
DAC[6]  
PGA[6]  
PGA[6]  
DAC[5]  
DAC[5]  
PGA[5]  
PGA[5]  
DAC[4]  
DAC[4]  
PGA[4]  
PGA[4]  
DAC[3]  
DAC[3]  
PGA[3]  
PGA[3]  
DAC[2]  
DAC[2]  
PGA[2]  
PGA[2]  
DAC[1]  
DAC[1]  
PGA[1]  
PGA[1]  
DAC[0]  
DAC[0]  
PGA[0]  
PGA[0]  
RW  
RW  
PGA Gain  
(Green)  
101010  
101011  
PGA Gain (Blue)  
PGA Gain (RGB)  
00  
00  
RW  
W
PGA[7]  
PGA[7]  
PGA[6]  
PGA[6]  
PGA[5]  
PGA[5]  
PGA[4]  
PGA[4]  
PGA[3]  
PGA[3]  
PGA[2]  
PGA[2]  
PGA[1]  
PGA[1]  
PGA[0]  
PGA[0]  
Table 5 Register Map  
REGISTER MAP DESCRIPTION  
The following table describes the function of each of the control bits shown in Table 5.  
REGISTER  
BIT  
NO  
BIT  
NAME(S)  
DEFAULT  
DESCRIPTION  
Setup  
Register 1  
0
1
EN  
1
1
Global power down: 0 = complete power down, 1 = fully active.  
CDS  
Select correlated double sampling mode: 0 = single ended mode,  
1 = CDS mode.  
2
3
MONO  
SELPD  
0
0
Mono/colour select: 0 = colour, 1 = monochrome operation.  
Selective power down: 0 = no individual control,  
1 = individual blocks can be disabled (controlled by SELDIS[3:0]).  
5:4  
PGAFS[1:0]  
MODE4  
00  
Offsets PGA output to optimise the ADC range for different polarity sensor  
output signals. Zero differential PGA input signal gives:  
00 = Zero output  
(use for bipolar video)  
01 = Zero output  
10 = Full-scale positive output  
(use for negative going video)  
11 = Full-scale negative output  
(use for positive going video)  
6
0
Required when operating in MODE4: 0 = other modes, 1 = MODE4.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
20  
Product Preview  
WM8192  
REGISTER  
BIT  
NO  
BIT  
NAME(S)  
DEFAULT  
DESCRIPTION  
Determines the output data format.  
Setup  
1
MUXOP  
0
Register 2  
0 = 8-bit multiplexed (8+8 bits)  
1 = 4-bit multiplexed mode (4+4+4+4-bits)  
2
INVOP  
0
Digitally inverts the polarity of output data.  
0 = negative going video gives negative going output,  
1 = negative-going video gives positive going output data.  
3
5
VRLCEXT  
0
1
When set powers down the RLCDAC, changing its output to Hi-Z, allowing  
VRLC/VBIAS to be externally driven.  
RLCDACRNG  
Sets the output range of the RLCDAC.  
0 = RLCDAC ranges from 0 to AVDD (approximately),  
1 = RLCDAC ranges from 0 to VRT (approximately).  
7:6  
DEL[1:0]  
00  
Sets the output latency in ADC clock periods.  
1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC  
clock period = 3 MCLK periods.  
00 = Minimum latency  
01 = Delay by one ADC clock  
period  
10 = Delay by two ADC clock periods  
11 = Delay by three ADC clock  
periods  
Setup  
Register 3  
3:0  
5:4  
RLCV[3:0]  
1111  
01  
Controls RLCDAC driving VRLC pin to define single ended signal  
reference voltage or Reset Level Clamp voltage. See Electrical  
Characteristics section for ranges.  
CDSREF[1:0]  
CDS mode reset timing adjust.  
00 = Advance 1 MCLK period  
01 = Normal  
10 = Retard 1 MCLK period  
11 = Retard 2 MCLK periods  
7:6  
CHAN[1:0]  
00  
Monochrome mode channel select.  
00 = Red channel select  
01 = Green channel select  
10 = Blue channel select  
11 = Reserved  
Software  
Reset  
Any write to Software Reset causes all cells to be reset.  
Auto-cycle  
Reset  
Any write to Auto-cycle Reset causes the auto-cycle counter to reset  
to RINP.  
Setup  
Register 4  
0
1
LINEBYLINE  
ACYCNRLC  
0
0
Selects line by line operation 0 = normal operation,  
1 = line by line operation.  
When line by line operation is selected MONO is forced to 1 and  
CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals  
are produced. Green and Blue PGAs are also disabled to save power.  
When LINEBYLINE = 0 this bit has no effect.  
When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC  
input pin and the input multiplexer and offset/gain register controls.  
0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of  
input and gain/offset multiplexers,  
1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin.  
See Table 4, Colour Selection Description in Line-by-Line Mode for colour  
selection mode details.  
When auto-cycling is enabled, the RLC/ACYC pin cannot be used for  
reset level clamping. The RLCINT bit may be used instead.  
2
FME  
0
When LINEBYLINE = 0 this bit has no effect.  
When LINEBYLINE = 1 this bit controls the input force mux mode:  
0 = No force mux, 1 = Force mux mode. Forces the input mux to be  
selected by FM[1:0] separately from gain and offset multiplexers.  
See Table 4 for details.  
3
RLCINT  
0
When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine  
whether Reset Level Clamping is used.  
0 = RLC disabled, 1 = RLC enabled.  
5:4  
INTM[1:0]  
00  
Colour selection bits used in internal modes.  
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.  
See Table 4 for details.  
7:6  
FM[1:0]  
00  
Colour selection bits used in input force mux modes.  
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.  
See Table 4 for details.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
21  
WM8192  
Product Preview  
REGISTER  
BIT  
NO  
BIT  
NAME(S)  
DEFAULT  
DESCRIPTION  
Setup  
Register 5  
0
VSMPDET  
0
0 = Normal operation, signal on VSMP input pin is applied directly to  
Timing Control block.  
1 = Programmable VSMP detect circuit is enabled. An internal  
synchronisation pulse is generated from signal applied to VSMP input pin  
and is applied to Timing Control block.  
3:1  
VDEL[2:0]  
000  
When VSMPDET = 0 these bits have no effect.  
When VSMPDET = 1 these bits set a programmable delay from the  
detected edge of the signal applied to the VSMP pin. The internally  
generated pulse is delayed by VDEL MCLK periods from the detected  
edge.  
See Figure 13, Internal VSMP Pulses Generated for details.  
4
POSNNEG  
0
When VSMPDET = 0 this bit has no effect.  
When VSMPDET = 1 this bit controls whether positive or negative edges  
are detected:  
0 = Negative edge on VSMP pin is detected and used to generate internal  
timing pulse.  
1 = Positive edge on VSMP pin is detected and used to generate internal  
timing pulse.  
See Figure 13 for further details.  
Setup  
Register 6  
3:0  
7:0  
SELDIS[3:0]  
DAC[7:0]  
0000  
Selective power disable register - activated when SELPD = 1.  
Each bit disables respective cell when 1, enabled when 0.  
SELDIS[0] = Red CDS, PGA  
SELDIS[1] = Green CDS, PGA  
SELDIS[2] = Blue CDS, PGA  
SELDIS[3] = ADC  
Offset DAC  
(Red)  
0
Red channel offset DAC value.  
Offset DAC  
(Green)  
7:0  
7:0  
7:0  
DAC[7:0]  
DAC[7:0]  
DAC[7:0]  
0
0
0
Red channel offset DAC value  
Red channel offset DAC value  
Offset DAC  
(Blue)  
Offset DAC  
(RGB)  
A write to this register location causes the red, green and blue offset DAC  
registers to be overwritten by the new value  
PGA gain  
(Red)  
7:0  
7:0  
7:0  
7:0  
PGA[7:0]  
PGA[7:0]  
PGA[7:0]  
PGA[7:0]  
0
0
0
0
Determines the gain of the red channel PGA according to the equation:  
Red channel PGA gain = 208/(283-PGA[7:0])  
PGA gain  
(Green)  
Determines the gain of the green channel PGA according to the equation:  
Green channel PGA gain = 208/(283-PGA[7:0])  
PGA gain  
(Blue)  
Determines the gain of the blue channel PGA according to the equation:  
Blue channel PGA gain = 208/(283-PGA[7:0])  
PGA gain  
(RGB)  
A write to this register location causes the red, green and blue PGA gain  
registers to be overwritten by the new value  
Table 6 Register Control Bits  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
22  
Product Preview  
WM8192  
RECOMMENDED EXTERNAL COMPONENTS  
DVDD  
3
8
DVDD1  
DGND  
10  
DVDD2  
C1  
C2  
AVDD  
21  
22  
2
AVDD  
AGND1  
AGND2  
C3  
DGND  
AGND  
AGND  
24  
25  
23  
VRT  
VRX  
VRB  
1
RINP  
GINP  
BINP  
C4  
C5  
Video  
Inputs  
28  
27  
C6  
C7  
C8  
26  
VRLC/VBIAS  
C9  
AGND  
WM8192  
AGND  
20  
19  
18  
17  
16  
15  
14  
13  
OP[7]/SDO  
DVDD  
AVDD  
7
5
6
MCLK  
OP[6]  
Timing  
Signals  
VSMP  
OP[5]  
C10  
C11  
+
C12  
+
+
Output  
Data  
Bus  
RLC/ACYC  
OP[4]  
OP[3]  
12  
11  
9
SCK  
SDI  
OP[2]  
DGND  
AGND  
OP[1]  
SEN  
OP[0]  
Interface  
Controls  
4
OEB  
NOTES: 1. C1-9 should be fitted as close to WM8192 as possible.  
2. AGND and DGND should be connected as close to WM8192 as possible.  
3. DVDD should be connected as close to WM8192 as possible.  
Figure 21 External Components Diagram  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1  
C2  
100nF  
100nF  
100nF  
10nF  
De-coupling for DVDD1.  
De-coupling for DVDD2.  
De-coupling for AVDD.  
C3  
C4  
High frequency de-coupling between VRT and VRB.  
C5  
1µF  
Low frequency de-coupling between VRT and VRB (non-polarised).  
De-coupling for VRB.  
C6  
100nF  
100nF  
100nF  
100nF  
10µF  
C7  
De-coupling for VRX.  
C8  
De-coupling for VRT.  
C9  
De-coupling for VRLC.  
C10  
C11  
C12  
Reservoir capacitor for DVDD.  
Reservoir capacitor for DVDD.  
Reservoir capacitor for AVDD.  
10µF  
10µF  
Table 7 External Components Descriptions  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
23  
WM8192  
Product Preview  
PACKAGE DIMENSIONS  
D: 28 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch  
DM016.B  
e
B
15  
28  
ZONE A  
ZONE B  
E
H
L
h x 45o  
1
14  
D
α
C
A1  
SEATING PLANE  
-C-  
A
0.10 (0.004)  
Dimensions  
(mm)  
Dimensions  
(Inches)  
Symbols  
MIN  
2.35  
0.10  
0.33  
0.23  
17.70  
MAX  
2.65  
0.30  
0.51  
0.32  
18.10  
MIN  
MAX  
A
A1  
B
C
D
e
0.0926  
0.0040  
0.0130  
0.0091  
0.6969  
0.1043  
0.0118  
0.0200  
0.0125  
0.7125  
1.27 BSC  
0.0500 BSC  
E
h
H
L
7.40  
0.25  
10.00  
0.40  
0o  
7.60  
0.75  
10.65  
1.27  
8o  
0.2914  
0.0100  
0.3940  
0.0160  
0o  
0.2992  
0.0290  
0.4190  
0.0500  
8o  
α
REF:  
JEDEC.95, MS-013  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).  
D. MEETS JEDEC.95 MS-013, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
E. PIN ONE INDICATORS WILL BE LOCATED IN EITHER ZONE A OR ZONE B.  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.0 June 2000  
24  
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