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XWM8816EDW

型号:

XWM8816EDW

描述:

立体声数字音量控制[ Stereo Digital Volume Control ]

品牌:

WOLFSON[ WOLFSON MICROELECTRONICS PLC ]

页数:

12 页

PDF大小:

369 K

WM8816  
Stereo Digital Volume Control  
Advanced Information, September 2000, Rev 1.1  
DESCRIPTION  
FEATURES  
Gain range from -111.5dB to +15.5dB  
0.5dB Gain step size  
The WM8816 is a highly linear stereo volume control for  
audio systems. The design is based on resistor chains with  
external op-amps, which provides flexibility for the supply  
voltage, signal swing, noise floor and cost optimisation. The  
gain of each channel can be independently programmed  
from -111.5dB to +15.5dB through a digital serial control  
interface.  
Total Harmonic Distortion 0.001% (100dB) typical  
Crosstalk -110dB typical  
Input signals up to ±18V  
Zero Detection for Gain Changes  
Hardware and Software Mute  
Power On/Off Transient Suppression  
Audible clicks on gain changes are eliminated by changing  
gains only when a zero crossing has been detected in the  
signal. The device also features peak level detection, which  
can be used for Automatic Gain Control. The WM8816  
operates from a single +5V supply and accepts signal input  
levels up to ±18V.  
APPLICATIONS  
Audio Amplifiers  
The WM8816 is available in a 16-pin SOIC package. It is  
guaranteed over a temperature range of -40° to 85°C.  
Consumer Audio / Entertainment Systems  
Mixing Desks  
Audio Recording Equipment  
BLOCK DIAGRAM  
(3) LFO  
LIN (4)  
(2) LMO  
LGND (5)  
-
LEFT OUT  
+
Zero  
Peak  
Crossing  
Detector  
Level  
Detector  
CSB (6)  
MUTEB (8)  
DATA (9)  
External Opamps  
DAC  
Control  
WM8816  
CCLK (10)  
Zero  
Crossing  
Detector  
Peak  
Level  
Detector  
+
-
RIGHT OUT  
(15) RMO  
(14) RFO  
RGND (12)  
RIN (13)  
(1)  
(16)  
(7)  
(11)  
AVDD  
AGND  
DVDD  
DGND  
WOLFSON MICROELECTRONICS LTD  
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK  
Tel: +44 (0) 131 667 9386  
Fax: +44 (0) 131 667 5176  
Email: sales@wolfson.co.uk  
Advanced information data sheets contain  
preliminary data on new products in the  
pre-production phase of development.  
Supplementary data will be published at a  
later date.  
http://www.wolfson.co.uk  
2000 Wolfson Microelectronics Ltd.  
WM8816  
Advanced Information  
PIN CONFIGURATION  
ORDERING INFORMATION  
DEVICE  
TEMP. RANGE  
PACKAGE  
XWM8816EDW  
-40 to +85oC  
16-pin SOIC (plastic)  
1
2
3
4
5
6
7
8
AVDD  
LMO  
LFO  
16  
15  
14  
13  
12  
11  
10  
9
AGND  
RMO  
RFO  
RIN  
LIN  
LGND  
CSB  
RGND  
DGND  
CCLK  
DVDD  
MUTEB  
DATA  
PIN DESCRIPTION  
PIN  
1
NAME  
AVDD  
LMO  
TYPE  
DESCRIPTION  
Supply Voltage for Analogue Circuitry  
Supply  
2
Analogue Output  
Analogue Input  
Analogue Input  
Analogue Input  
Digital Input  
Supply  
External Op-amp Inverting Input (Left Channel)  
External Op-amp Feedback Signal (Left Channel)  
Input Signal (Left Channel)  
3
LFO  
4
LIN  
5
LGND  
CSB  
Input Signal Ground (Left Channel)  
Chip Select (active low)  
6
7
DVDD  
MUTEB  
DATA  
CCLK  
DGND  
RGND  
RIN  
Supply Voltage for Digital Circuitry  
Mute (active low)  
8
Digital Input  
Digital In / Out  
Digital Input  
Supply  
9
Serial Interface Data Input / Output (tri-state)  
Serial Interface Clock  
10  
11  
12  
13  
14  
15  
16  
Digital Ground  
Analogue Input  
Analogue Input  
Analogue Input  
Analogue Output  
Supply  
Input Signal Ground (Right Channel)  
Input Signal (Right Channel)  
RFO  
External Op-amp Feedback Signal (Right Channel)  
External Op-amp Inverting Input (Right Channel)  
Analogue Ground  
RMO  
AGND  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
2
Advanced Information  
WM8816  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating  
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical  
Characteristics at the test conditions specified.  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore susceptible to damage  
from excessive static voltages. To optimise the distortion and noise performance of pins 3, 4, 13 and 14, the  
on-chip ESD protection circuitry has been restricted, and consequently only achieves 300V when characterised  
to the Human Body Model. Proper ESD precautions must be taken during handling and storage of this device.  
As per JEDEC specification JESD22-A112-A, this product requires specific storage conditions prior to surface mount assembly. It  
has been classified as having a Moisture Sensitivity Level of 3 and is therefore supplied in vacuum-sealed moisture barrier bags.  
CONDITION  
MIN  
-20V  
MAX  
+20V  
Input signal voltage  
Positive supply voltage (AVDD to AGND, DVDD to DGND)  
Input voltage (all other pins)  
Operating temperature  
-0.5V  
-0.5V  
-40°C  
-55°C  
6V  
AVDD + 0.5V  
85°C  
Storage temperature  
125°C  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Input signal voltage  
-18  
4.5  
+18  
5.5  
V
V
Positive supply voltage  
Negative supply voltage  
Input signal grounds  
Operating temperature  
AVDD, DVDD  
AGND, DGND  
LGND, RGND  
5
0
V
0
V
-20  
60  
60  
°C  
ELECTRICAL CHARACTERISTICS  
TEST CONDITIONS  
AVDD = 5.0V, AGND = 0V, TA = 25°C, unless otherwise stated.  
PARAMETER  
Analogue Inputs / Outputs  
Input resistance  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
RIN  
CIN  
For any gain  
For any gain  
7
10  
2
kΩ  
pF  
Input capacitance  
Input offset voltage  
Voffset  
External OP275  
opamp, gain = 1  
1
5
mV  
Supply current  
IDD  
From AVDD / AGND  
From AVDD  
2.5  
80  
mA  
dB  
Power supply rejection ratio  
(Note 1)  
PSRR  
Gain Control  
Gain range  
G
D
-111.5  
+15.5  
0.5  
dB  
dB  
dB  
Gain step size  
Gain error (Note 1)  
0.5  
DE  
Lowest gains  
guaranteed by  
design, not tested in  
production.  
Gain match error (Note 1)  
Mute attenuation  
ME  
Between channels  
0.2  
dB  
dB  
MATT  
113  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
3
WM8816  
Advanced Information  
TEST CONDITIONS  
AVDD = 5.0V, AGND = 0V, TA = 25°C, unless otherwise stated.  
PARAMETER  
Audio Performance  
Noise (Note 1)  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Gain = 0dB  
Gain = -60dB  
13  
V
IN = 0V, VOUT with OP275,  
N
4
µV rms  
A-weighed  
Gain = mute  
2.5  
Total Harmonic Distortion plus  
Noise  
VIN= 1Vrms, gain=0dB,  
THD+N  
V
OUT with OP275,  
DC to 20 kHz  
0.001  
(100)  
130  
%
(dB)  
dB  
Dynamic Range (Note 1)  
Crosstalk (Note 1)  
DR  
CR  
120  
Between channels,  
gain=0dB, fIN=1kHz  
-100  
-110  
dB  
Digital Inputs / Outputs  
Input low voltage  
VIL  
VIH  
All digital inputs  
All digital inputs  
ILoad = 2mA  
0.3 DVDD  
0.4  
V
V
V
V
Input high voltage  
0.7 DVDD  
DVDD -0.4  
Output low voltage  
VOL  
VOH  
Output high voltage  
Control Interface Timing  
Clock Frequency  
ILoad = 2mA  
fCCLK  
tWHC  
tWLC  
tRC  
1
MHz  
ns  
Period of CCLK high  
Period of CCLK low  
Rise time of CCLK  
VIH to VIH  
VIL to VIL  
VIL to VIH  
VIH to VIL  
500  
500  
ns  
100  
100  
ns  
Fall time of CCLK  
tFC  
ns  
Hold time, CCLK high to CSB low  
tHCHS  
tSSLCH  
20  
ns  
Setup time, CSB low to CCLK  
high  
100  
ns  
Setup time, valid DATA to CCLK  
high  
tSDCH  
tHCHD  
tDCLD  
tDSZ  
100  
100  
ns  
ns  
ns  
ns  
ns  
ns  
Hold time, CCLK high to invalid  
DATA  
Setup time, CCLK low to valid  
DATA  
Hold time, CSB high or 16th  
CCLK low to invalid DATA  
Hold time, 16th CCLK high to  
CSB high  
Load = 100pF  
200  
200  
Load = 3.3kΩ  
20  
tHLCHS  
tSSHCH  
200  
200  
Setup time, CSB high to CCLK  
high  
Note:  
1. Guaranteed by design.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
4
Advanced Information  
WM8816  
CONTROL INTERFACE TIMING DIAGRAM  
tWLC  
tWHC  
tRC  
tFC  
CCLK  
tHCSH  
tHLCHS  
tDSSHCH  
tSSLCH  
CSB  
DATA (IN)  
tSDCH  
tHCHD  
A4  
A7  
A6  
A5  
A3  
A2  
A1  
A0  
D7  
D6  
D5  
D4  
tDCLD  
D5  
D3  
D2  
D1  
D0  
tDSZ  
DATA (OUT)  
D7  
D6  
D4  
D3  
D2  
D1  
D0  
ADDRESS BYTE  
DATA BYTE  
Figure 1 Control Interface Timing Diagram  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
5
WM8816  
Advanced Information  
DEVICE DESCRIPTION  
The WM8816 is a stereo digital volume control designed for audio systems. The levels of the left  
and right analogue channels can be programmed independently through the serial interface. The  
resistor values in the internal resistor chains are decoded to 0.5 dB resolution with multiplexers,  
giving a gain range of -111.5 to +15.5 dB. The code for -112 dB activates mute for maximum  
attenuation.  
The WM8816 has two constant impedance signal inputs. The left channel input is between LIN and  
LGND, and the right channel between RIN and RGND. The output pins LFO, LMO (left) and RFO,  
RMO (right) are designed to interface directly to two external op-amps, which produce the volume  
controlled output signals. This provides flexibility for the supply voltage and signal swing; while the  
WM8816 runs at 5V, the output signal swing depends solely on the op-amp supply.  
INTERFACES  
Control information is written into or read back from the internal register via the serial control port.  
This port consists of a bi-directional data pin (DATA), an active low chip select pin (CSB) and the  
control clock (CCLK). Control data is shifted into the serial input register on the rising edges of CCLK  
pulses, while CSB is low. All control instructions require two bytes of data. The first byte contains a 4-  
bit register address and a read/write bit, and the second byte is the control word. CSB must return to  
high at the end of each word. When reading from the control registers, data is shifted out on the  
falling edges of CCLK.  
When CSB is high, the DATA pin is in a high impedance state. In a multi-channel system, the same  
DATA and CCLK lines can thus be connected to several WM8816 volume controllers, and each  
device can be independently addressed by pulling its CSB pin low.  
OPERATING MODES  
When power is first applied, a power-on reset initialises the control registers mutes the WM8816. To  
activate the device, the MUTEB pin must be high and a non-zero value must be written to the gain  
register. After that the device can be muted again either by pulling the MUTEB pin low or by writing  
zero (00hex) to the gain register.  
For device testing, the MUTEB pin becomes an output when Bit 1 of the test register is high. Internal  
signals can then be directed to MUTEB and monitored.  
CHANGING THE GAIN OF THE CHANNEL  
The WM8816 has two gain registers for the left and right channels respectively. There is also an alias  
register address to update both gain registers simultaneously. When a new gain value is written into  
a gain register the WM8816 will wait until the next falling edge zero crossing in the input signal before  
changing the gain. This ensures that no audible click is produced at the output. If there are no zero  
crossings in the signal after 18ms, the gain is changed regardless. If both gain registers are changed  
simultaneously, the gain is changed first on the right and then the left channel.  
PEAK LEVEL DETECTION  
The WM8816 has an on-chip 8-bit digital-to-analogue converter (DAC) used for monitoring the peak  
level of the output signal. The DAC input value is programmed via the serial interface. The reference  
value VREF is calculated from VREF = k/256 × 18V, where k is the DAC input code. When a positive  
peak signal level exceeds this value, the peak detector sets Bit 1 (for the left channel) or Bit 0 (right  
channel) of the status register. These bits remain set until the status register is read.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
6
Advanced Information  
WM8816  
REGISTER MAP  
REGISTER  
ADDRESS BYTE BITS  
DATA BYTE  
7
6
5
4
3
2
1
0
MSB…LSB  
Output code  
00000000  
00000001  
00000010  
00000011  
Input code  
11111111  
11111110  
11111101  
:
Function  
Peak Detector Status  
CR4  
X
1
0
1
1
R/W  
X
X
No overload  
Right overload  
Left overload  
Both overload  
DAC output  
Peak Detector  
Reference  
X
1
1
0
0
R/W  
X
X
255/256 × 18V  
254/256 × 18V  
253/256 × 18V  
:
CR3  
00000010  
00000001  
00000000  
Input code  
11111111  
11111110  
11111101  
:
2/256 × 18V  
1/256 × 18V  
AGND  
Gain dB  
+15.5  
Left Channel Gain  
CR2  
X
1
1
0
1
R/W  
X
X
+15.0  
+14.5  
:
11100000  
00000010  
00000001  
00000000  
Input code  
11111111  
11111110  
11111101  
:
0.0  
-111.0  
-111.5  
mute  
Right Channel Gain  
CR1  
X
1
1
1
0
R/W  
X
X
Gain dB  
+15.5  
+15.0  
+14.5  
:
11100000  
00000010  
00000001  
00000000  
0.0  
-111.0  
-111.5  
mute  
Test, CR5  
X
X
1
1
1
0
1
0
1
1
R/W  
W
X
X
X
X
Reserved  
Write to both gain registers  
Both Channel Gains  
Table 1 Register Map Description  
Notes:  
1. Address bit 2 is the read / write bit (1 for read, 0 for write).  
2. X are dont cares, set to 1 for minimum power consumption.  
3. All registers are set to their default value (all zeros) during power-on reset, except CR3 which is set to 255.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
7
WM8816  
Advanced Information  
TEST REGISTER  
When bit 1 in register CR5 is set, MUTEB becomes an output pin. Bits 2, 3 and 4 select different  
internal signals which can then be seen via the MUTEB pin.  
CONDITION  
DATA BYTE BITS  
FUNCTION  
7
6
5
4
3
2
1
0
Normal (MUTEB  
0
0
0
0
0
0
0
1
Latch the new gain value to resistor network  
configured as input)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Left delay generator  
Left peak detector  
Test Mode  
Left zero crossing  
Left enable for zero crossing and delay generator  
Right delay generator  
(MUTEB configured  
as output)  
Right peak detector  
Right zero crossing  
Right enable for zero crossing and delay generator  
Table 2 Test Register Description  
PERFORMANCE GRAPHS  
-70  
-80  
-90  
THD+N  
(dB)  
-100  
-110  
-120  
-60  
-50  
-40  
-30  
-20  
-10  
+0  
+10  
Input Signal Level (dBV)  
Figure 2 THD + Noise versus input level at gains of +6dB, 0dB, -6dB, -12dB and mute  
+0  
-20  
-40  
d
B
V
-60  
-80  
-100  
-120  
-140  
5k  
10k  
15k  
20k  
25k  
30k  
Frequency (Hz)  
Figure 3 FFT of output signal with 1kHz, 1V rms sine wave input  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
8
Advanced Information  
WM8816  
+0  
-20  
-40  
-60  
d
B
V
-80  
-100  
-120  
-140  
5k  
10k  
15k  
20k  
25k  
30k  
Frequency (Hz)  
Figure 4 FFT of output signal with 10kHz, 1V rms sine wave input  
POWER SUPPLY DECOUPLING  
For best audio performance, all digital activities should be avoided during analogue signal  
processing. Special attention should be paid to power and ground decoupling. If possible separate  
analogue and digital power supplies should be used. A clean analogue power supply should be used  
for AVDD. DVDD should be the same as AVDD to avoid latch-up phenomena. Decoupling capacitors  
should be located as close to the WM8816 as possible.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
9
WM8816  
Advanced Information  
RECOMMENDED EXTERNAL COMPONENTS  
LFO  
3
2
+18V  
4
5
LIN  
-
LMO  
LEFT CHANNEL  
INPUT  
+
LGND  
-18V  
RFO  
14  
+18V  
13 RIN  
12  
-
RMO 15  
RIGHT CHANNEL  
INPUT  
+
RGND  
-18V  
+5V DC  
WM8816  
6
9
1
CSB  
AVDD  
C1  
C2  
16  
DATA  
CCLK  
MUTEB  
AGND  
Micro  
Controller  
10  
8
7
+
DVDD  
C3  
11  
DGND  
Note: Connect signal ground and non-inverting opamp input together on the PCB  
Figure 5 Typical Application  
RECOMMENDED EXTERNAL COMPONENTS VALUES  
COMPONENT  
REFERENCE  
SUGGESTED  
VALUE  
DESCRIPTION  
C1  
C2  
C3  
220nF  
220nF  
10µF  
Analogue Supply Decoupling  
Digital Supply Decoupling  
General Supply Decoupling  
Table 3 Recommended External Components Values  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
10  
Advanced Information  
WM8816  
LFO  
3
2
+18V  
4
5
LIN  
2K  
2K  
-
LMO  
+
LGND  
+18V  
DAC  
WM8816  
-18V  
-
RFO  
Balanced  
Output  
14  
+
+18V  
13 RIN  
12  
2K  
-
RMO 15  
-18V  
+
RGND  
-18V  
2K  
Figure 6 Configuration for Double Balanced Output (One Channel)  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
11  
WM8816  
Advanced Information  
PACKAGE DIMENSIONS  
DM019.A  
DW: 16 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch  
e
B
16  
9
E
H
L
1
8
D
h x 45o  
A1  
SEATING PLANE  
-C-  
α
A
C
0.10 (0.004)  
Dimensions  
(mm)  
Dimensions  
(Inches)  
Symbols  
MIN  
MAX  
2.65  
0.30  
0.51  
0.32  
10.50  
MIN  
MAX  
A
A1  
B
C
D
e
2.35  
0.10  
0.33  
0.23  
10.10  
0.0926  
0.0040  
0.0130  
0.0091  
0.3465  
0.1043  
0.0118  
0.0200  
0.0125  
0.3622  
1.27 BSC  
0.0500 BSC  
E
h
H
L
7.40  
0.25  
10.00  
0.40  
0o  
7.60  
0.75  
10.65  
1.27  
8o  
0.2914  
0.0100  
0.3940  
0.0160  
0o  
0.2992  
0.0290  
0.4190  
0.0500  
8o  
α
REF:  
JEDEC.95, MS-013  
NOTES:  
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES).  
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.  
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN).  
D. MEETS JEDEC.95 MS-013, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.  
WOLFSON MICROELECTRONICS LTD  
AI Rev 1.1 September 2000  
12  
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XWM8191CFT 14位6MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 6MSPS CIS/CCD Analogue Front End/Digitiser ] 27 页

WOLFSON

XWM8192 (88)位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ] 24 页

WOLFSON

XWM8192CDW/V (88)位输出16位CIS / CCD AFE /数字转换器[ (88) Bit Output 16-bit CIS/CCD AFE/Digitiser ] 24 页

CIRRUS

XWM8194CDW/V [ Analog Circuit, 1 Func, CMOS, PDSO28, 7.50 MM, 1.27 MM PITCH, MS-013AE, SOIC-28 ] 27 页

WOLFSON

XWM81955CFT/RV 14位12MSPS CIS / CCD模拟前端/数字转换器[ 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser ] 33 页

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