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OXU140CM-PBBG

型号：

OXU140CM-PBBG

描述：

USB的On-the -全速主机，高速外设与多存储接口[ USB On-The-Go Full Speed Host, High Speed Peripheral with Multi-Storage Interface ]

品牌：

OXFORD[ OXFORD SEMICONDUCTOR ]

页数：

20 页

PDF大小：

516 K

下载PDF手册
Data Sheet  
OXU140CM  
USB On-The-Go Full Speed Host, High Speed Peripheral  
with Multi-Storage Interface  
Features  
„
Single‐chip USB OTG full‐speed host and high‐speed peripheral  
controller  
†
†
†
Reduces system cost and board space  
Minimizes system design complexity and power  
Simultaneous USB host, peripheral, and  
CE‐ATA/MMC/SD interface operation  
†
USB peripheral to CE‐ATA/MMC/SD bridging  
„
„
„
Compatible with the USB 2.0 and OTG specifications  
CE‐ATA 1.1 command support with built‐in flow control  
MMC 4.1 compatible  
†
Configurable 1‐/4‐/8‐bit data bus at up to 48 MHz clock  
frequency  
†
†
Dual‐voltage (3.3 V and 1.8 V) I/O support  
Integrated smart clock control for reduced power  
consumption  
„
„
„
„
3.3 V power supply, flexible I/O voltage of 1.65 V to 3.6 V  
(LVCMOS/TTL) to interface to a wide range of MCUs  
Low‐power sleep mode to minimize power consumption when  
not in use  
Integrated on‐chip charge pump, supports up to 100 mA of  
current, enables support for broad range of USB devices  
Packaging  
†
8 × 8 mm BGA, 100 ball, RoHS compliant  
14 × 14 mm LQFP, 128 pin, RoHS compliant  
†
„
„
„
„
16‐bit memory mapped interface can gluelessly interface to most  
popular microprocessors and DSPs  
Fast microprocessor access cycle and double/multi buffering  
support for all four types of USB transfers  
Two DMA (slave) channel support for peripheral controller and  
CE‐ATA/MMC/SD controller lowers CPU utilization  
Integrated PLL supports external crystal or crystal oscillators of  
12 MHz or 30 MHz, for system flexibility  
DS-0038 Jul 06  
External--Free Release  
1
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
„
„
„
„
16 Kbytes of on‐chip SRAM, optimized buffer size for  
performance and cost  
USB peripheral allows up to 8 bi‐directional endpoints and  
transfers to enable support for multi‐function systems  
Host Negotiation Protocol and Session Request Protocol  
implemented in hardware  
Transaction scheduling and transfer level protocol implemented  
in hardware (including data toggle, retry, and bandwidth  
management) for high performance  
Device  
Overview  
The Oxford Semiconductor OXU140CM is a single‐chip USB On‐The‐Go  
(OTG) controller that incorporates a full‐speed host, a high‐speed  
peripheral controller, and a multi‐storage interface that supports the  
following technologies:  
„
Consumer electronics advanced technology attachment  
(CE‐ATA) HDDs  
„
„
MultiMediaCard (MMC)  
Secure Digital (SD)  
The high‐speed peripheral port offers high‐data‐rate transfers to and  
from host PCs. This is essential for devices such as smart phones,  
portable media players, car audio/navigation units, and personal storage  
devices, where media transfer times greatly impact the user experience.  
The full‐speed host port enables the connection of a wide range of  
devices, such as flash drives, keyboards, mice, and digital still cameras.  
The OXU140CM low‐power design is ideal for extending the battery life  
in mobile applications.  
The multi‐storage interface provides glueless support for CE‐ATA hard  
drives. This new class of drives is designed for lower pin count, better  
power utilization, and a more efficient command protocol than existing  
hard drives, making it ideal for portable applications. The interface also  
supports MMC and SD flash memory devices, providing additional  
product flexibility in memory capacity expansion. The OXU140CM  
implements fast bridging between the USB peripheral port and the  
multi‐storage interface, improving data transfer rates and minimizing  
CPU utilization.  
The OXU140CM allows for simultaneous host and peripheral operation.  
The ports can be configured in one of two modes:  
„
„
One OTG port and one full‐speed host port  
One high‐speed peripheral port and two full‐speed host ports  
The multi‐storage interface can be used in conjunction with either mode.  
2
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
The OXU140CM is supported with USB device drivers and the Oxford  
Semiconductor USBLinkTM product suite. The USBLink host, peripheral,  
and OTG stacks have been ported to a wide variety of real time operating  
system including VxWorks®, ThreadX®, and Nucleus®.  
In addition, Oxford Semiconductor also makes available low‐level  
controller drivers for other native USB stacks such as those included with  
Windows® CE and Linux® 2.6.x.  
Figure 1 shows a block diagram of the OXU140CM.  
Figure 1 OXU140CM Architectural Diagram  
Clock/  
Osc Pads  
and Clk  
Div  
OSC1  
OSC2  
ENVREG  
Voltage Regulator  
VREGOUT  
VBus Control Circuit  
and  
Vbus Charge Pump  
VBUS  
ACK[1:0]  
REQ[1:0]  
/EXVBO  
DMA  
Interface  
System Configuration  
& Control Registers  
HNP/SRP Logic  
ID  
USB Peripheral  
Controller Registers  
/RESET  
/CS  
USB  
Peripheral  
Controller  
/WR  
/RD  
P_DM  
P_DP  
µP  
INT  
Interface  
OTG XCVR  
GPIO  
Memory  
Blocks  
A[14:1]  
D[15:0]  
DM1  
DP1  
Host SIE  
& Root  
Hub  
USB Host  
Control  
Logic  
Tes t  
Control  
TEST  
DM2  
DP2  
USB Host  
Controller  
Registers  
USB Xcvr  
/PO  
/OC  
M_CLK  
M_CMD  
CE-ATA/MMC/SD  
Controller  
M_DATA  
[7:0]  
DS-0038 Jul 06  
External--Free Release  
3
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Development  
Support  
The OXU140CM product suite includes the USB controller as well as the  
protocol stacks and the driver software that enable a wide variety of USB  
applications. This unique ability to deliver a total hardware and software  
solution sets Oxford Semiconductor apart from other semiconductor  
companies and benefits customers by:  
„
„
„
Shortening time to market  
Reducing risk  
Offering a single source for hardware & software, thereby  
reducing the number of suppliers the customer has to deal with  
Oxford Semiconductor is a Microsoft® Windows® Embedded Partner  
and has developed host and peripheral controller drivers for Windows  
CE 5.0. Similar software support is also available for Linux® 2.6.x.  
For customers using an RTOS such as VxWorks®, ThreadX®, Nucleus®,  
OSE, LynxOS®, and AMXTM, among others, Oxford Semiconductor  
offers its USBLink host, peripheral and On‐The‐Go software solutions.  
The USBLink Product Suite is a modularized approach to providing USB  
connectivity for a wide variety of embedded products. Due to its flexible  
architecture and broad based support for USB host, peripheral and OTG  
applications, Oxford Semiconductor can tailor the USBLink software  
deliverables to meet each customer’s USB requirements.  
The USBLink solutions are configurable and can support systems with:  
„
„
„
„
Big or little endian processors  
DMA or non‐DMA USB controllers  
A wide variety of USB controllers, including the OXU140CM  
Complex to simple operating systems  
Oxford Semiconductor has over eight years of experience developing  
embedded USB technology. Its USBLink software has been ported to  
twenty different operating systems and a wide variety of embedded  
architectures. USBLink is shipping in many millions of units.  
4
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Electrical  
Characteristics  
Tables 1 to 11 detail the required operating conditions for the device and  
the DC and AC electrical characteristics.  
Table 1 Absolute Maximum Device Ratings  
Symbol  
DD3.3  
Parameter  
3.3 V power supply  
Min  
Max  
Unit  
V
V
V
-0.3  
4.0  
V
1.8 V power supply  
-0.3  
-0.3  
2.16  
4.0  
V
V
DD1.8  
1.8 V to 3.3 V  
DDW  
wide-range I/O power supply  
V
T
DC input voltage  
-0.3  
-40  
4.0  
V
I
Storage temperature  
+150  
°C  
S
Note:  
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera‐  
tion should be restricted to the normal operating conditions specified in the following section. Expo‐  
sure to absolute maximum rating conditions for extended periods may affect device reliability.  
Table 2 Recommended Operating Conditions  
Symbol  
DD3.3  
Parameter  
3.3 V power supply  
Min  
Max  
Unit  
V
V
V
2.97  
3.63  
V
1.8 V power supply  
1.62  
1.62  
1.98  
3.63  
V
V
DD1.8  
1.8 to 3.3 V  
DDW  
wide-range I/O power supply  
V
V
T
DC input voltage of 3.3 V pins  
DC input voltage of wide-range pins  
Operating temperature  
0
0
3.6  
V
V
I3.3  
IW  
1.1*V  
DDW  
-40  
+85  
°C  
O
Table 3 DC Characteristics, Full-Speed USB I/O Signals: DP , DM  
N
N
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
V
V
V
Differential input sensitivity  
|V  
V N)| (where N = 1 or 2)  
I(DP -- I(DM  
0.2  
V
N)  
DI  
Differential comm. mode range  
Static output low  
0.8  
0.0  
2.8  
1.3  
2.5  
0.3  
3.6  
2.0  
20  
V
V
CM  
OL  
Static output high  
V
OH  
CRS  
Output signal crossover  
Input capacitance  
V
C
pF  
IN  
DS-0038 Jul 06  
External--Free Release  
5
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Table 4 DC Characteristics, High-Speed USB I/O Signals: DP and DM Only  
P
P
Symbol  
Parameter  
Condition  
P)|  
I(DP ) -- VI(DM  
Min  
Max  
Unit  
V
High-speed differential input  
sensitivity  
|V  
300  
mV  
P
HSDIFF  
V
V
High-speed data signaling  
common mode range  
-50  
500  
100  
mV  
HSCM  
HSSQ  
High-speed squelch detection  
threshold  
Squelch detected  
mV  
mV  
mV  
No squelch detected  
150  
-10  
V
V
V
V
High-speed idle output voltage  
(differential)  
10  
10  
HSIO  
High-speed low-level output  
voltage (differential)  
-10  
mV  
mV  
mV  
HSOL  
HSOH  
CHIRPK  
High-speed high-level output  
voltage (differential)  
-360  
-900  
400  
-500  
Chirp-K output voltage  
(differential)  
Table 5 DC Characteristics, Logic Signals  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
Low-level output voltage  
0.4  
V
OL  
V
V
V
High-level output voltage  
Low-level input voltage  
High-level input voltage  
V
V
V
V
V
V
= 3.3 V  
= 1.8 V  
= 3.3 V  
= 1.8 V  
= 3.3 V  
= 1.8 V  
2.4  
V
V
OH  
DDW  
DDW  
DDW  
DDW  
DDW  
DDW  
0.75*VDDW  
0.8  
V
IL  
0.3*V  
V
DDW  
2.0  
V
IH  
0.7*V  
V
DDW  
C
C
C
I
Input capacitance  
2.2 (typical)  
2.2 (typical)  
2.2 (typical)  
pF  
pF  
pF  
µA  
IN  
Output capacitance  
Bi-directional capacitance  
Input leakage current  
OUT  
BI  
No pull up or pull down  
-10  
10  
IN  
Note:  
The capacitances listed above do not include pad capacitance and package capacitance.  
One can estimate pin capacitance by adding pad capacitance of about 0.5 pF; and the  
package capacitance, which is about 0.86 pF max for QFP and 0.42 pF max for BGA.  
Table 6 DC Characteristics, ID Resistance  
Symbol  
B-PLUG-ID  
A-PLUG-ID  
Parameter  
Condition  
Min  
Max  
Unit  
R
R
Resistance to ground on mini-B plug  
100 K  
Ω
Resistance to ground on mini-A plug  
10  
Ω
6
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Table 7 DC Characteristics, Regulator  
Symbol  
Parameter  
Output voltage  
Condition  
Min  
1.8 (typical)  
150  
Max  
Unit  
RV  
Driving current <= 100 mA  
V
out  
RI  
Driving current  
V
= 3.3 V  
DD3.3A  
mA  
drive  
Output voltage = 1.8 V  
= 3.3 V  
Rt  
Start-up time when enabled  
V
25 (typical)  
µs  
st  
DD3.3A  
RV = 1.62 V (90%)  
out  
Note:  
The VDD3.3A pin that corresponds to the regulator supply is QFP pin 106 and BGA pin B7.  
Table 8 DC Characteristics, Charge Pump  
Symbol Parameter  
Output voltage  
Condition  
Min  
Max  
Unit  
CV  
Driving current <= 100 mA  
4.75  
5.07  
V
out  
V
Driving current  
V
= 3.3 V  
CPSUPPLY  
100  
mA  
DD1.8  
Output voltage = 5 V  
= 3.3 V  
V
Start-up time when enabled  
V
400 (typical)  
µs  
DDW  
CPSUPPLY  
RV = 4.5 V (90%)  
out  
Note:  
The charge pump supply VCPSUPPLY supplies the external components of the charge  
pump circuit.  
Table 9 AC Characteristics, High-Speed DP and DM Driver Characteristics  
P
P
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
High-speed differential rise time  
500  
ps  
HSR  
HSF  
t
High-speed differential fall time  
Driver output impedance  
500  
ps  
R
Equivalent resistance used as internal  
chip  
40.5  
49.5  
Ω
DRV  
Table 10 AC Characteristics, Full-Speed DP , DP , DM , DM Driver Characteristics  
1
2
1
2
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
Rise time  
Fall time  
C = 50 pF  
4
20  
ns  
FR  
L
t
t
C = 50 pF  
4
90  
3
20  
110  
9
ns  
%
Ω
FF  
L
T /T matching  
FRFM  
R F  
Z
Driver output resistance  
Steady state drive with external 33 Ω  
DRV  
series resistor  
Table 11 AC Characteristics, Low-Speed DP , DP , DM , DM Driver Characteristics  
1
2
1
2
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
Rise time  
Fall time  
C = 200 - 600 pF  
75  
300  
ns  
LR  
L
t
t
C = 200 - 600 pF  
75  
80  
300  
125  
ns  
%
LF  
L
T /T matching  
FRFM  
R F  
DS-0038 Jul 06  
External--Free Release  
7
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Power  
Table 12 gives typical power consumption figures for the OXU140CM.  
Consumption  
Table 12 OXU140CM Power Consumption  
Condition  
Min  
Max  
30  
Unit  
mA  
mA  
Host operational current  
ENVREG = 1  
Peripheral operational current  
High-speed,  
ENVREG = 1  
75  
Full-speed,  
50  
mA  
ENVREG = 1  
Host suspend state current  
Peripheral suspend state current  
MMC host operational current  
MMC host suspend current  
Power save state current  
ENVREG = 1  
ENVREG = 1  
ENVREG = 1  
ENVREG = 1  
ENVREG = 1  
150 (typical)  
400 (typical)  
45  
µA  
µA  
mA  
µA  
µA  
150 (typical)  
150 (typical)  
The above measurements are at typical process corner and room  
temperature and do not account for process and temperature variations.  
Peripheral operational current is measured with a 5 m cable with  
maximum switching and BULK OUT transfers at 400 Mbps with 92.6%  
bus utilization during one microframe. The actual average current in  
customer applications will be lower.  
MMC host operation current is measured with 8‐bit at 48 MHz writing  
55AA pattern to an MMC 4.1 card at 15 Mbps throughput. The actual  
average operational current will vary base on the data pattern and  
throughput rates supported by the attached device.  
ENVREG = 1 enables the internal voltage regulator.  
8
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Pin Layout  
The OXU140CM is supplied as a 128‐pin LQFP package and as a 100‐ball  
BGA package. Figure 2 shows the chip layout of the 128‐pin LQFP  
package.  
Figure 2 OXU140CM 128-Pin LQFP Package (Top View)  
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65  
64 OSC1  
97  
98  
VSS  
63  
62  
61  
60  
OSC2  
VDD3.3A  
VSSA  
DP2  
NC 99  
100  
NC  
RREF  
DM2  
101  
102  
103  
104  
59 NC  
VDD3.3  
DMP  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
/CE1P8V_EN  
NC  
ENVREG  
DPP  
NC  
VREGOUT 105  
VDD3.3A  
VSSA  
106  
107  
108  
109  
110  
111  
112  
VDD3.3A  
VSSA  
VSS  
VDD1.8  
A5  
VSS  
VDD1.8  
VDDW  
NC  
/CS  
A12  
/RESET  
TEST 113  
114  
DRQ0 115  
116  
GPXA 117  
118  
ACK1 119  
GPXB  
VDDW 121  
122  
D0 123  
A13  
GPIO  
46 A14  
45 A11  
ACK0  
44  
43  
A10  
A9  
OXU140CM-LQBG  
DRQ1  
42 A8  
41 A7  
120  
40 A6  
39 VDDW  
38 VDDCE  
INT  
37  
36 CEDAT6  
CEDAT7  
D1  
D2  
124  
125  
35  
34  
33  
CEDAT5  
VSS  
D3 126  
VDD1.8  
VSS  
127  
128  
VDDCE  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
DS-0038 Jul 06  
External--Free Release  
9
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Table 13 lists the LQFP pin allocations.  
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 1 of 3)  
(1)  
Pin  
No.  
Pins  
Name  
Description  
Type  
Processor Interface (39 pins)  
1, 2, 3, 4, 7, 8, 9, 16  
10, 12, 13, 14, 15,  
123, 124, 125,  
126  
MSBCT  
D - D  
16-bit data bus  
0
15  
18, 19, 20, 21, 40, 14  
41, 42, 43, 44, 45,  
46, 47, 48, 50  
MSI  
A - A  
Address bus for direct address space  
1
14  
16  
1
1
1
1
MSIU  
MSIU  
MSIU  
MOCT  
/WR  
/RD  
/CS  
/INT  
Write strobe  
Read strobe  
Chip select  
17  
49  
122  
Interrupt to the MCU.This pin can be software  
configured as a driven output or open drain. Open  
drain is the default  
112  
1
2
2
MSIVI  
MOCT  
MSI  
/RESET  
DRQ , DRQ  
Hardware reset  
118, 115  
119, 116  
DMA request outputs to support two channels  
DMA acknowledge  
1
0
ACK , ACK  
1
0
General Purpose I/O (3 pins)  
114, 117, 120  
Power & Ground (39 pins)  
3
MSBC  
GPIO, GPX , GPX  
General purpose I/O  
A
B
54, 62, 90, 91, 94,  
106  
6
V
V
Analog +3.3 V power  
Analog ground  
DD3.3A  
SSA  
53, 61, 88, 89, 95,  
107  
6
75, 102  
2
8
V
V
Digital +3.3 V power  
DD3.3  
DD1.8  
5, 24, 51, 66, 76,  
85, 109, 127  
1.8 V core power. VREGOUT may be used for the  
supplies  
6. 22, 39, 110,  
121  
5
V
Wide-range I/O +1.65 V to +3.6 V for the processor  
interface  
DDW  
23, 33, 38  
3
9
V
V
Wide-range I/O +1.65 V to +3.6 V for the media port  
Digital/wide-range I/O ground  
DDCE  
SS  
11, 28, 34, 52, 65,  
84, 97, 108, 128  
USB Interface (13 pins)  
58, 56  
2
B
B
DM , DP  
Data lines for USB peripheral port, which may serve  
as an OTG port in combination with host port 1. If not  
used, these two pins should be left floating  
P
P
73, 68  
2
DM , DP  
Data lines for Host Port 1, which may serve as a USB  
host or an OTG port in combination with the  
peripheral port. If not used, these two pins should be  
left floating  
1
1
10  
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 2 of 3)  
(1)  
Pin  
No.  
Pins  
Name  
Description  
Type  
101, 98  
2
1
B
B
DM , DP  
Data lines for Host Port 2, a dedicated USB host  
port. If not used, these two pins should be left floating  
2
2
60  
93  
R
Connect external reference resistor (12 KΩ +/- 1%)  
REF  
to V  
SSA  
1
5I  
VBUS  
VBUS input used by the voltage comparators of the  
OTG port for connection. This pin should be left  
floating in a host-only application  
79  
78  
1
1
O
O
VBP  
V
pulsing control. This pin is used only when Port  
BUS  
1 is an OTG port for a B-DEVICE.  
Turn on/off the external V (5 V) for OTG  
/EXVBO  
BUS  
operation (1:V  
off, 0: V  
on) when using the  
BUS  
BUS  
external charge pump  
77  
81  
1
1
IU  
IU  
/OC  
ID  
Over current condition indicator for powered host  
ports  
Connected to the ID pin of the mini-AB connector for  
OTG applications. With the help of an internal pull-up  
resistor, this pin determines the chip’s responsibility  
in an OTG application (0: A-device, 1:B-device)  
80  
1
O
I
/PO  
Turn on/off gang power for all host ports  
Clock Interface (3 pins)  
82  
1
CLKCFG  
The state of this pin is used to indicate whether a 12  
MHz or a 30 MHz crystal/oscillator is being used.  
CLKCFG -- Frequency  
0--12-MHz crystal; 12-MHz 3.3 V oscillator input on  
OSC1  
1--30-MHz crystal; 30-MHz 3.3 V oscillator input on  
OSC1  
64  
63  
1
1
I
OSC  
OSC  
A 12-MHz or 30-MHz passive crystal should be  
connected across the two pins. Optionally, a 12 MHz  
or 30-MHz oscillator can be connected to OSC1  
while keeping OSC2 unconnected  
1
2
O
MMC/CE-ATA (13 pins)  
25  
26  
1
1
8
MO  
CECLK  
CECMD  
SD/MMC/CE-ATA CLK output (0-48 MHz)  
SD/MMC/CE-ATA CMD  
MBUS  
MBUS  
37, 36, 35, 32, 31,  
30, 29, 27  
CEDAT[7:0]  
SD/MMC/CE-ATA 1,4 or 8-bit data bus  
67  
1
1
1
O
O
O
/CE3P3V_EN  
/CE1P8V_EN  
/CEMOT_EN  
On/off control for MMC 3.3 V interface power  
On/off control for MMC 1.8 V interface power  
On/off control for HDD motor power  
103  
74  
Internal VBUS Charge Pump (3 pins)  
87  
1
O
PD_PMOS  
Internal charge pump output for P-MOSFET (optional  
switch on the VOUT)  
92  
86  
1
1
O
I
EXT  
Internal charge pump output for N-MOSFET  
VOUT  
Internal charge pump output voltage feedback pin  
DS-0038 Jul 06  
External--Free Release  
11  
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Table 13 OXU140CM 128-Pin LQFP Pin Allocations (Sheet 3 of 3)  
(1)  
Pin  
No.  
Pins  
Name  
Description  
Type  
Internal Voltage Regulator (2 pins)  
104  
1
I
ENVREG  
Enables the internal voltage regulator if asserted. If  
not used, this pin should be tied to V  
SS  
105  
1
O
VREGOUT  
Internal voltage regulator output of 1.8 V. If enabled,  
this output should be connected to the V  
DD1.8  
supplies of the chip. If the regulator is disabled, this  
pin should be treated as another V  
supply input  
DD1.8  
to the chip  
Test (2 pins)  
83  
1
1
I
XMODE  
TEST  
Xcrv test mode. This pin should be grounded for  
normal operation  
113  
ID  
Factory test mode. This pin should be grounded or  
left floating (has an internal pull-down) for normal  
operation  
Miscellaneous (11 pins)  
55, 57, 59, 69, 70,  
71 72, 96, 99,  
100,111  
1
NC  
No connection. These pins should be left floating  
Note to Table 13:  
1
Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
T Tristate  
(2)  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
5
5 V  
I
U
D
M
C
3.3 V  
O
Output  
Pull down  
Normal  
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to 3.3 V, 2.5 V, or 1.8 V by setting the VIO voltage level.  
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14 mA, or 16 mA.  
12  
External--Free Release  
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Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Figure 3 shows the chip layout of the 100‐ball BGA package.  
Figure 3 OXU140CM 100-Ball BGA Package (Top View)  
VSSA  
VSSA  
VSSA  
/CPE1P8V_EN  
ENVREG  
VDD3.3A  
VBUS  
ID  
/OC  
/PO  
/CPE3P3V_EN  
DP1  
OSC2  
10  
9
/EXVBO  
DP  
2
CLKCFG  
XMODE  
/CEMOT_EN  
VDD3.3A  
DM  
2
DPP  
VDD3.3A  
VOUT  
EXT  
VREGOUT  
GPIO  
VDD3.3A  
VBP  
DM 1  
VDD1.8  
A14  
VDD3.3A  
OSC 1  
RREF  
/CS  
DM P  
VSSA  
A12  
8
7
6
5
4
3
2
1
A5  
VDD3.3  
VDD1.8  
VSSA  
/RESET  
DRQ 1  
GPXB  
D3  
PD_PMOS  
VSS  
VDD3.3  
TEST  
NC (GP12)  
A13  
A11  
A7  
VSS  
VDDW  
/INT  
GPX  
A
VSS  
DRQ  
0
A10  
VDDW  
VDDCE  
A9  
A6  
D12  
ACK0  
D1  
VDD1.8  
A8  
ACK  
D0  
1
CEDAT2  
A1  
D13  
D10  
/WR  
A2  
CEDAT0  
CEDAT7  
CEDAT1  
CEDAT6  
CEDAT4  
A4  
D5  
D2  
D8  
D11  
D14  
CECLK  
D7  
D4  
15  
D6  
D9  
D
/RD  
A3  
CECMD  
CEDAT3  
CEDAT5  
A
B
C
D
E
F
G
H
J
K
DS-0038 Jul 06  
External--Free Release  
13  
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Table 14 lists the BGA pin allocations.  
Table 14 OXU140CM 100-Ball BGA Pin Allocations (Sheet 1 of 3)  
(1)  
Pin  
No.  
Pins  
Name  
Description  
Type  
Processor Interface (39 pins)  
B3, A3, B2, C3,  
B1, A2, C1, A1,  
C2, D1, D3, D2,  
E4, E3, E2, E1  
16  
MSBCT  
D - D  
16-bit data bus  
0
15  
G3, F2, G1, G2,  
J7, H4, J4, K4,  
H5, K5, J5, H6,  
J6, G6  
14  
MSID  
A - A  
Address bus for direct address space  
1
14  
F3  
F1  
K6  
D4  
1
1
1
1
MSIU  
MSIU  
MSIU  
MOCT  
/WR  
/RD  
/CS  
/INT  
Write strobe  
Read strobe  
Chip select  
Interrupt to the MCU.This pin can be software  
configured as a driven output or open drain. Open  
drain is the default  
C6  
1
2
2
MSIU  
MOCT  
MSI  
/RESET  
DRQ , DRQ  
Hardware reset  
C5, B5  
B4, A4  
DMA request outputs to support two channels  
DMA acknowledge  
1
0
ACK , ACK  
1
0
General Purpose I/O (3 pins)  
A7, A5, C4  
Power & Ground (21 pins)  
3
MSBC  
GPIO, GPX , GPX  
General purpose I/O  
A
B
B7, C8, C9, J8,  
K9  
5
V
V
Analog +3.3 V power  
Analog ground  
DD3.3A  
SSA  
B10, C7, D10,  
H7, J10  
5
D6, D7  
2
3
V
V
Digital +3.3 V power  
DD3.3  
DD1.8  
F4, F7, G7  
1.8 V core power. VREGOUT may be used for the  
supplies  
D5. E5  
2
V
Wide-range I/O +1.65 V to +3.6 V for the processor  
interface  
DDW  
G5  
1
3
V
V
Wide-range I/O +1.65 V to +3.6 V for the media port  
Digital/wide-range I/O ground  
DDCE  
SS  
E6, F5, F6  
USB Interface (13 pins)  
H8 J9  
2
B
B
DM , DP  
Data lines for USB peripheral port, which may serve  
as an OTG port in combination with host port 1. If not  
used, these two pins should be left floating  
P
P
G8, H9  
2
DM , DP  
Data lines for Host Port 1, which may serve as a USB  
host or an OTG port in combination with the  
peripheral port. If not used, these two pins should be  
left floating  
1
1
14  
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Table 14 OXU140CM 100-Ball BGA Pin Allocations (Sheet 2 of 3)  
(1)  
Pin  
No.  
Pins  
Name  
Description  
Type  
A9, A10  
2
1
B
B
DM , DP  
Data lines for Host Port 2, a dedicated USB host  
port. If not used, these two pins should be left floating  
2
2
K7  
R
Connect external reference resistor (12 KΩ +/- 1%)  
REF  
to V  
SSA  
C10  
1
5I  
VBUS  
VBUS input used by the voltage comparators of the  
OTG port for connection. This pin should be left  
floating in a host-only application  
F8  
1
1
O
O
VBP  
V
pulsing control. This pin is used only when Port  
BUS  
1 is an OTG port for a B-DEVICE.  
Turn on/off the external V (5 V) for OTG  
G10  
/EXVBO  
BUS  
operation (1:V  
off, 0: V  
on) when using the  
BUS  
BUS  
external charge pump  
F10  
E10  
1
1
P5IU  
IU  
/OC  
ID  
Over current condition indicator for powered host  
ports  
Connected to the ID pin of the mini-AB connector for  
OTG applications. With the help of an internal pull-up  
resistor, this pin determines the chip’s responsibility  
in an OTG application (0: A-device, 1:B-device)  
F9  
1
O
I
/PO  
Turn on/off gang power for all host ports  
Clock Interface (3 pins)  
E9  
1
CLKCFG  
The state of this pin is used to indicate whether a 12  
MHz or a 30 MHz crystal/oscillator is being used.  
CLKCFG -- Frequency  
0--12-MHz crystal; 12-MHz 3.3 V oscillator input on  
OSC1  
1--30-MHz crystal; 30-MHz 3.3 V oscillator input on  
OSC1  
K8  
1
1
I
OSC  
OSC  
A 12-MHz or 30-MHz passive crystal should be  
connected across the two pins. Optionally, a 12 MHz  
or 30-MHz oscillator can be connected to OSC1  
while keeping OSC2 unconnected  
1
2
K10  
O
MMC/CE-ATA (13 pins)  
J3, K3, K1, K2,  
J1, G4, J2, H3  
8
MBUS  
CEDAT[7:0]  
SD/MMC/CE-ATA 1,4 or 8-bit data bus  
H10  
B9  
1
1
1
1
1
O
/CE3P3V_EN  
/CE1P8V_EN  
/CEMOT_EN  
CECLK  
On/off control for MMC 3.3 V interface power  
On/off control for MMC 1.8 V interface power  
On/off control for HDD motor power  
SD/MMC/CE-ATA CLK output (0-48 MHz)  
SD/MMC/CE-ATA CMD  
O
G9  
H2  
H1  
O
MO  
MBUS  
CECMD  
Internal VBUS Charge Pump (3 pins)  
E7  
1
O
PD_PMOS  
Internal charge pump output for P-MOSFET (optional  
switch on the VOUT)  
D8  
D9  
1
1
O
I
EXT  
Internal charge pump output for N-MOSFET  
VOUT  
Internal charge pump output voltage feedback pin  
DS-0038 Jul 06  
External--Free Release  
15  
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Table 14 OXU140CM 100-Ball BGA Pin Allocations (Sheet 3 of 3)  
(1)  
Pin  
No.  
Pins  
Name  
Description  
Type  
Internal Voltage Regulator (2 pins)  
B8  
1
I
ENVREG  
Enables the internal voltage regulator if asserted. If  
not used, this pin should be tied to V  
SS  
A8  
1
O
VREGOUT  
Internal voltage regulator output of 1.8 V. If enabled,  
this output should be connected to the V  
DD1.8  
supplies of the chip. If the regulator is disabled, this  
pin should be treated as another V  
supply input  
DD1.8  
to the chip  
Test (2 pins)  
E8  
1
1
I
XMODE  
TEST  
Xcrv test mode. This pin should be grounded for  
normal operation  
A6  
ID  
Factory test mode. This pin should be grounded or  
left floating (has an internal pull-down) for normal  
operation  
Miscellaneous (1 pin)  
B6  
1
NC  
No connection. These pins should be left floating  
Note to Table 14:  
1
Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
T Tristate  
(2)  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
5
5 V  
I
U
D
M
C
3.3 V  
O
Output  
Pull down  
Normal  
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to 3.3 V, 2.5 V, or 1.8 V by setting the VIO voltage level.  
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14 mA, or 16 mA.  
16  
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Package  
Layout  
Figure 4 shows the package layout for the 128‐pin LQFP package.  
Figure 4 128-Pin LQFP Package  
DS-0038 Jul 06  
External--Free Release  
17  
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Figure 5 shows the layout for the 100‐ball TFBGA.  
Figure 5 100-Ball TFBGA Package  
18  
External--Free Release  
DS-0038 Jul 06  
Oxford Semiconductor, Inc.  
OXU140CM Data Sheet  
Figure 5 100-Ball TFBGA Package (continued)  
DS-0038 Jul 06  
External--Free Release  
19  
OXU140CM Data Sheet  
Oxford Semiconductor, Inc.  
Ordering  
Information  
The following conventions are used to identify Oxford Semiconductor  
products:  
OXU140CM - LQBG  
Green (RoHS compliant)  
Revision  
Package Type: LQ 128-Pin LQFP  
Part Number  
OXU140CM - PBBG  
Green (RoHS compliant)  
Revision  
Package Type: PB 100-Ball TF-BGA  
Part Number  
Contacting  
Oxford Semi-  
conductor  
See the Oxford Semiconductor website (http://www.oxsemi.com) for  
further details about Oxford Semiconductor devices, or email  
sales@oxsemi.com.  
Revision  
Table 15 documents the revisions of this guide.  
Information  
Table 15 Revision Information  
Revision  
Jul 06  
Modification  
First publication  
USBLink is a trademark of Oxford Semiconductor, Inc.  
VxWorks is a registered trademark of Wind River Systems.  
ThreadX is a registered trademark of Express Logic, Inc.  
Nucleus is a registered trademark of Mentor Graphics Corporation.  
Symbian OS is a registered trademark of Symbian Ltd.  
Windows is a trademark of Microsoft, Inc., registered in the US and other countries.  
LynxOS is a registered trademark of LynuxWorks, Inc.  
AMX is a trademark of KADAK Products LTD.  
Linux is a registered trademark of Linus Torvalds.  
All other trademarks are the property of their respective owners.  
© Oxford Semiconductor, Inc. 2006  
The content of this paper is furnished for informational use only, is subject to change without notice, and should not be construed  
as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors  
or inaccuracies that may appear in this paper.  
20  
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