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OXU121HP-LQBG

型号：

OXU121HP-LQBG

描述：

USB的On-the -进入全速主机和高速外设控制器[ USB On-The-Go Full-Speed Host and High-Speed Peripheral Controller ]

品牌：

OXFORD[ OXFORD SEMICONDUCTOR ]

页数：

22 页

PDF大小：

530 K

下载PDF手册
Data Sheet  
OXU121HP  
USB On-The-Go Full-Speed Host and High-Speed  
Peripheral Controller  
Features  
„
Single‐chip USB OTG full‐speed host and high‐speed peripheral  
controller  
†
†
†
Replaces two‐chip system  
Reduces system cost and board space  
Minimizes system design complexity and power  
consumption  
†
Simultaneous host and peripheral operation  
„
Compatible with the Universal Serial Bus Specification, Revision 2.0  
and the On‐The‐Go Supplement to the USB Specification 2.0,  
Revision 1.0  
„
„
Single 3.3 V power supply, flexible I/O voltage of 1.65 V to 3.6 V  
(LVCMOS/TTL) to interface to a wide range of MCUs  
Low power operation, suitable for mobile applications  
†
30 mA (max) for host operation  
†
75 mA (max) for peripheral operation  
„
„
„
Power saving mode for the host controller and suspend mode for  
peripheral controller  
Integrated on‐chip charge pump, supports up to 100 mA of  
current, enables support for broad range of USB devices  
Small package and footprint saves board space  
†
7×7 mm BGA, 84‐ball, RoHS compliant  
12×12 mm LQFP, 100‐pin, RoHS compliant  
†
„
„
„
„
„
16‐bit memory mapped interface can gluelessly interface to most  
popular microprocessors and DSPs  
Fast microprocessor access cycle and double/multi‐buffering  
support for all four types of USB transfers  
Two DMA (slave) channels for the high‐speed peripheral  
controller, lowering CPU utilization  
Integrated PLL supports external crystal or crystal oscillators of  
12 MHz and 30 MHz, for system flexibility  
16 Kbytes of on‐chip SRAM, optimized buffer size for  
performance/cost  
DS-0040 Aug 06  
External--Free Release  
1
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
„
„
„
Allows up to 8 bi‐directional endpoints and transfers for support  
of multi‐function systems  
Configurable hardware Host Negotiation Protocol (HNP) and  
Session Request Protocol (SRP)  
Transaction scheduling and transfer level protocol implemented  
in hardware (including data toggle, retry and bandwidth  
management) for high performance  
„
Operating temperature range: ‐40 to 85 degrees C  
Device  
Overview  
The Oxford Semiconductor OXU121HP (formerly TD1120) is a single‐  
chip USB On‐The‐Go (OTG) controller that incorporates a full‐speed host  
and a high‐speed peripheral controller. It enables an embedded system  
to operate as a USB host and a peripheral simultaneously, thereby  
dramatically expanding the degree of interconnectivity and extending  
the applicability of USB into many new areas, especially in mobile  
communication, consumer electronics, and printer applications. The  
combination of the OXU121HP high‐speed peripheral and full‐speed  
host controller enables users to perform high‐speed USB data transfer for  
peripheral connectivity when connected to a host device, and operate at  
full speed in host mode operation to maximize system battery life in a  
mobile environment.  
The OXU121HP is ideal for mobile applications. It enables high‐speed  
PC synchronization to reduce data file transfer time when operating in  
USB peripheral mode. In host mode, it enables the system to connect to a  
wide range of USB devices such as flash drives, keyboards, mice, and  
digital still cameras (DSC). These mobile applications include smart  
phones, PDAs, MP3 players, portable media players, digital photo  
albums, and GPS devices.  
The OXU121HP is well suited for PictBridge printers. It enables high‐  
speed data transfer between PC and printer. While utilizing the host  
port, it adds PictBridge printing capability to the printer to support  
direct photo printing from a DSC. The OXU121HP replaces existing two‐  
chip solutions by combining discrete host and peripheral controllers into  
a single chip, thus minimizing system cost, board space, design  
complexity, and power consumption.  
The OXU121HP allows for simultaneous host and peripheral operation.  
The ports can be configured in one of two modes:  
„
„
1 OTG + 1 Host: one OTG port and one full‐speed host port  
1 Peripheral + 2 Host: one high‐speed peripheral port and two  
full‐speed host ports  
Software solutions for the OXU121HP include USB device drivers and  
the Oxford Semiconductor USBLinkTM product suite. The USBLink host,  
2
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
peripheral, and OTG stacks have been ported to a wide variety of real  
time operating systems including VxWorks®, ThreadX®, and Nucleus®.  
In addition, Oxford Semiconductor also makes available low‐level  
controller drivers for other native USB stacks such as those included with  
Windows® CE and Linux® 2.6.x.  
Figure 1 shows the OXU121HP architectural diagram.  
Figure 1 OXU121HP Architectural Diagram  
Clock/  
Osc Pads  
and Clk  
Div  
OSC1  
OSC2  
ENVREG  
Voltage Regulator  
VREGOUT  
VBUS  
/EXVBO  
/PO  
VBus Control Circuit  
and  
Vbus Charge Pump  
ACK[1:0]  
REQ[1:0]  
/OC  
DMA  
Interface  
System Configuration  
& Control Registers  
HNP/SRP Logic  
ID  
/RESET  
USB Peripheral  
Controller Registers  
/CS  
/WR  
/RD  
INT  
USB  
Peripheral  
Controller  
P_DM  
P_DP  
µP  
Interface  
OTG XCVR  
Memory  
Blocks  
A[12:1]  
D[15:0]  
DM1  
DP1  
Host SIE  
& Root  
Hub  
USB Host  
Control  
Logic  
Test  
Control  
TEST  
DM2  
DP2  
USB Host  
Controller  
Registers  
USB Xcvr  
Development  
Support  
The OXU121HP product suite includes the USB controller as well as the  
protocol stacks and the driver software that enable a wide variety of USB  
applications. This unique ability to deliver a total hardware and software  
solution sets Oxford Semiconductor apart from other semiconductor  
companies and benefits customers by:  
„
„
„
Shortening time to market  
Reducing risk  
Offering a single source for hardware and software, thereby  
reducing the number of suppliers the customer has to deal with  
Oxford Semiconductor is a Microsoft® Windows® Embedded Partner  
and has developed host and peripheral controller drivers for Windows  
CE 5.0. Similar software support is also available for Linux® 2.6.x.  
DS-0040 Aug 06  
External--Free Release  
3
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
For customers using a real time operating system (RTOS) such as  
VxWorks®, ThreadX®, Nucleus®, OSE, LynxOS® and AMXTM among  
others, Oxford Semiconductor offers its USBLink host, peripheral and  
On‐The‐Go software solutions.  
The USBLink Product Suite is a modularized approach to providing USB  
connectivity for a wide variety of embedded products. Due to its flexible  
architecture and broad based support for USB host, peripheral and OTG  
applications, Oxford Semiconductor can tailor the USBLink software  
deliverables to meet each customer’s USB requirements.  
The USBLink solutions are configurable and can support systems with:  
„
„
„
„
Big or little endian processors  
DMA or non‐DMA USB controllers  
A wide variety of USB controllers, including the OXU121HP  
A broad range of operating systems  
Oxford Semiconductor has over eight years of experience developing  
embedded USB technology. Its USBLink software has been ported to  
twenty different operating systems and a wide variety of embedded  
architectures. USBLink is shipping in many millions of units.  
Sample  
Applications  
„
„
„
„
„
„
„
„
„
„
„
„
„
„
Portable media players  
MP3 players  
Car audio & navigation  
Printers  
Smart mobile phones  
Digital televisions  
Home media centers  
Digital video cameras  
Digital still cameras  
External storage products  
Set‐Top Boxes (STB)  
Personal Video Recorders (PVR)  
Personal Digital Assistants (PDA)  
DVD recorders  
4
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Electrical  
Characteristics  
Tables 3 to 11 detail the required operating conditions for the device and  
the DC and AC electrical characteristics.  
Table 1 Absolute Maximum Device Ratings  
Symbol  
DD3.3  
DD1.8  
DDW  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
V
V
T
3.3 V power supply  
-0.3  
4.0  
V
1.8 V power supply  
1.8 V to 3.3 V power supply  
DC input voltage  
-0.3  
-0.3  
-0.3  
-40  
2.16  
4.0  
V
V
4.0  
V
I
Storage temperature  
+150  
°C  
S
Note:  
1
Permanent device damage may occur if absolute maximum ratings are exceeded.  
Functional operation should be restricted to the normal operating conditions speci‐  
fied in the following section. Exposure to absolute maximum rating conditions for  
extended periods may affect device reliability.  
Table 2 Recommended Operating Conditions  
Symbol Parameter  
3.3 V power supply  
Condition  
Min  
Max  
Unit  
V
V
V
2.97  
3.63  
V
DD3.3  
1.8 V power supply  
1.62  
1.62  
1.98  
3.63  
V
V
DD1.8  
DDW  
1.8 - 3.3 V  
wide-range I/O power supply  
V
V
T
DC input voltage of 3.3 V pins  
DC input voltage of wide-range pins  
Operating temperature  
0
0
3.6  
V
V
I3.3  
IW  
1.1*V  
DDW  
-40  
+85  
°C  
O
DS-0040 Aug 06  
External--Free Release  
5
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 3 DC Characteristics, Full-Speed USB I/O Signals: DP , DP , DM , DM  
2
1
2
1
Symbol  
Parameter  
Condition  
V N)| (where N = 1 or 2)  
I(DP -- I(DM  
Min  
Max  
Unit  
V
Diff. input sensitivity  
|V  
0.2  
V
N)  
DI  
V
V
V
V
Diff. comm. mode range  
Static output low  
0.8  
0.0  
2.8  
1.3  
2.5  
0.3  
3.6  
2.0  
20  
V
V
CM  
OL  
Static output high  
V
OH  
CRS  
Output signal crossover  
Input capacitance  
V
C
pF  
IN  
Table 4 DC Characteristics, High-Speed USB I/O Signals: DP and DM Only  
P
P
Symbol  
Parameter  
Condition  
P)|  
I(DP ) -- VI(DM  
Min  
Max  
Unit  
V
High-speed differential input  
sensitivity  
|V  
300  
mV  
P
HSDIFF  
V
V
High-speed data signaling  
common mode range  
-50  
500  
100  
mV  
HSCM  
HSSQ  
High-speed squelch detection  
threshold  
Squelch detected  
mV  
mV  
mV  
No squelch detected  
150  
-10  
V
V
V
V
High-speed idle output voltage  
(differential)  
10  
10  
HSIO  
High-speed low-level output  
voltage (differential)  
-10  
mV  
mV  
mV  
HSOL  
HSOH  
CHIRPK  
High-speed high-level output  
voltage (differential)  
-360  
-900  
400  
-500  
Chirp-K output voltage  
(differential)  
6
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Table 5 DC Characteristics, Logic Signals  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
Low-level output voltage  
0.4  
V
OL  
V
V
V
High-level output voltage  
Low-level input voltage  
High-level input voltage  
V
V
V
V
V
V
= 3.3 V  
= 1.8 V  
= 3.3 V  
= 1.8 V  
= 3.3 V  
= 1.8 V  
2.4  
V
V
OH  
DDW  
DDW  
DDW  
DDW  
DDW  
DDW  
0.75*VDDW  
0.8  
V
IL  
0.3*V  
V
DDW  
2.0  
V
IH  
0.7*V  
V
DDW  
C
C
C
I
Input capacitance  
2.2 (typical)  
2.2 (typical)  
2.2 (typical)  
pF  
pF  
pF  
µA  
IN  
Output capacitance  
Bi-directional capacitance  
Input leakage current  
OUT  
BI  
No pull up or pull down  
-10  
10  
IN  
Note:  
The capacitances listed above do not include pad capacitance and package capacitance.  
One can estimate pin capacitance by adding pad capacitance of about 0.5 pF; and the  
package capacitance, which is about 0.86 pF max for QFP and 0.42 pF max for BGA.  
Table 6 DC Characteristics, ID Resistance  
Symbol  
B-PLUG-ID  
A-PLUG-ID  
Parameter  
Condition  
Min  
Max  
Unit  
R
R
Resistance to ground on mini-B plug  
100 K  
Ω
Resistance to ground on mini-A plug  
10  
Ω
Table 7 DC Characteristics, Regulator  
Symbol Parameter  
Output voltage  
Condition  
Min  
Max  
Unit  
RV  
Driving current <= 100 mA  
1.8 (typical)  
150  
V
out  
RI  
Driving current  
V
= 3.3 V  
DD3.3A  
mA  
drive  
Output voltage = 1.8 V  
= 3.3 V  
Rt  
Start-up time when enabled  
V
25 (typical)  
µs  
st  
DD3.3A  
RV = 1.62 V (90%)  
out  
Note:  
The VDD3.3A pin that corresponds to the regulator supply is QFP pin 81 and BGA pin B9.  
DS-0040 Aug 06  
External--Free Release  
7
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 8 DC Characteristics, Charge Pump  
Symbol  
Parameter  
Output voltage  
Condition  
Min  
Max  
Unit  
CV  
Driving current <= 100 mA  
4.75  
5.07  
V
out  
V
Driving current  
V
= 3.3 V  
CPSUPPLY  
100  
mA  
DD1.8  
Output voltage = 5 V  
= 3.3 V  
V
Start-up time when enabled  
V
400 (typical)  
µs  
DDW  
CPSUPPLY  
RV = 4.5 V (90%)  
out  
Note:  
The charge pump supply VCPSUPPLY supplies the external components of the charge  
pump circuit.  
Table 9 AC Characteristics, High-Speed DP and DM Driver Characteristics  
P
P
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
High-speed differential rise time  
500  
ps  
HSR  
HSF  
t
High-speed differential fall time  
Driver output impedance  
500  
ps  
R
Equivalent resistance used as internal  
chip  
40.5  
49.5  
Ω
DRV  
Table 10 AC Characteristics, Full-Speed DP , DP , DM , DM Driver Characteristics  
1
2
1
2
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
Rise time  
Fall time  
C = 50 pF  
4
20  
ns  
FR  
L
t
t
C = 50 pF  
4
90  
3
20  
110  
9
ns  
%
Ω
FF  
L
T /T matching  
FRFM  
R F  
Z
Driver output resistance  
Steady state drive with external 33 Ω  
DRV  
series resistor  
Table 11 AC Characteristics, Low-Speed DP , DP , DM , DM Driver Characteristics  
1
2
1
2
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
Rise time  
Fall time  
C = 200 - 600 pF  
75  
300  
ns  
LR  
L
t
t
C = 200 - 600 pF  
75  
80  
300  
125  
ns  
%
LF  
L
T /T matching  
FRFM  
R F  
8
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Power  
Table 12 gives typical power consumption figures for the OXU121HP.  
Consumption  
Table 12 OXU121HP Power Consumption  
Condition  
Min  
Max  
30  
Unit  
mA  
mA  
Host operational current  
ENVREG = 1  
Peripheral operational current  
High-speed,  
ENVREG = 1  
75  
Full-speed,  
50  
mA  
ENVREG = 1  
Host suspend state current  
Peripheral suspend state current  
Power save state current  
ENVREG = 1  
ENVREG = 1  
ENVREG = 1  
150 (typical)  
µA  
µA  
µA  
400 (typical)  
150 (typical)  
The above measurements are at typical process corner and room  
temperature and do not account for process and temperature variations.  
Peripheral operational current is measured with 5 m cable with  
maximum switching and BULK OUT transfer at 400 Mbps with 92.6%  
bus utilization during one microframe. The actual average current in  
customer applications will be lower.  
DS-0040 Aug 06  
External--Free Release  
9
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Pin Layout  
The OXU121HP is supplied as a 100‐pin LQFP package and as a 84‐ball  
BGA package. Figure 2 shows the chip layout of the 100‐pin LQFP  
package.  
Figure 2 OXU121HP 100-Pin LQFP Package (Top View)  
73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51  
75 74  
DP2  
76  
77  
78  
50  
49  
48  
OSC1  
OSC2  
VDD3.3A  
DM2  
VDD3.3  
47 VSSA  
46 RREF  
ENVREG 79  
VREGOUT 80  
VDD3.3A  
81  
82  
45  
44 DPP  
DMP  
VSSA  
VSS  
VDD3.3A  
43  
42  
41  
40  
39  
83  
84  
VSSA  
VSS  
VDD1.8  
VDDW  
85  
VDD1.8  
/CS  
/RESET 86  
TEST  
GPIO 88  
87  
38 NC  
DRQ0  
ACK 0  
89  
90  
37  
36  
35  
34  
ATEST13  
A12  
OXU121HP-LQBG  
A11  
A10  
91  
92  
93  
94  
RSVD0  
DRQ1  
ACK1  
33 A9  
32  
31  
A8  
RSVD1  
VDDW  
VDDW 95  
30  
29  
A7  
A6  
A5  
D0  
D1  
D2  
96  
97  
98  
28  
27  
26  
D3  
VSS  
99  
VDD1.8  
100  
VDDW  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
24 25  
10  
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Table 13 lists the LQFP pin allocations.  
Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 1 of 3)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
MSBCT  
MSID  
Processor Interface (37 pins)  
2, 3, 4, 5, 8, 9, 10, 16  
11, 13, 14, 15, 16,  
96, 97, 98, 99  
D - D  
16-bit data bus. Pull-up/pull-down can be controlled  
through register 0x034, bits 2:1. Default is none  
0
15  
22, 23, 24, 25, 28, 12  
29, 30 32, 33, 34,  
35, 36  
A - A  
Address bus for direct address space of 8 Kbytes.  
Pull-up can be enabled through register 0x034, bits  
9:8. Default is pull-down  
1
12  
20  
21  
39  
19  
1
1
1
1
MSIU  
MSIU  
MSIU  
MOCT  
/WR  
/RD  
/CS  
/INT  
Write strobe. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Read strobe. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Chip select. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Interrupt to the MCU.This pin can be software  
configured as a driven output or open drain. Open  
drain is the default  
86  
1
2
MSIU  
/RESET  
DRQ , DRQ  
Hardware reset. Pull-up is always enabled  
DMA request outputs to support two channels  
89, 92  
MOCT  
1
0
90, 93  
2
MSI  
ACK , ACK  
DMA acknowledge. Pull-up/pull-down can be  
controlled through register 0x03A, bits 1:0. Default is  
none  
1
0
General Purpose I/O (1 pin)  
88  
Power & Ground (34 pins)  
1
BC  
GPIO  
General purpose I/O  
1, 12, 27, 41, 51,  
65, 75, 83  
8
V
Digital/wide-range ground  
Analog ground  
SS  
42, 47, 69, 74, 82  
5
8
V
V
SSA  
6, 18, 40, 53, 57,  
66, 84, 100  
1.8 V core power. VREGOUT may be used for the  
supplies  
DD1.8  
43, 48, 70, 73, 81  
56, 78  
5
2
6
V
V
V
Analog +3.3 V power  
Digital +3.3 V power  
DD3.3A  
DD3.3  
DDW  
7, 17, 26, 31, 85,  
95  
Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V,  
VREGOUT may be used for these supplies  
USB Interface (13 pins)  
76, 77  
2
B
B
DP , DM  
Data lines for host port 2, a dedicated USB host port.  
If not used, these pins should be left floating  
2
2
1
54, 55  
2
DP , DM  
Data lines for host port 1, which can serve as a USB  
host or an OTG port in combination with the  
peripheral port. If not used, these pins should be left  
floating  
1
DS-0040 Aug 06  
External--Free Release  
11  
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 2 of 3)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
44, 45  
2
B
DP , DM  
Data lines for USB peripheral port, which can serve  
as an OTG port in combination with host port 1. If not  
used, these pins should be left floating  
P
P
46  
72  
1
1
B
R
Connect external reference resistor (12 KΩ +/- 1%) to  
REF  
V
SSA  
5I  
VBUS  
VBUS input used by the voltage comparators of the  
OTG port for connection. This pin should be left  
floating in a host-only application  
60  
59  
1
1
OC  
O
VBP  
VBUS pulsing control. This pin is used only when the  
OTG port is operating as a B-device  
/EXVBO  
Turn on/off the external V  
(5 V) for OTG operation  
BUS  
(1:V  
off, 0: V  
on) when using the external  
BUS  
BUS  
VBUS source  
58  
62  
1
1
IU  
IU  
/OC  
ID  
Over current condition indicator for powered host  
ports. Pull-up is always enabled  
Connected to the ID pin of the mini-AB connector for  
OTG applications. With the help of an internal pull-up  
resistor, this pin determines the chip’s responsibility in  
an OTG application (0: A-device, 1:B-device). Pull-up  
can be disabled through register 0x038, bits 7:6.  
Default is pull-up  
61  
1
O
I
/PO  
Turn on/off gang power for all host ports  
Clock Interface (3 pins)  
50  
1
OSC  
Input. A 12 MHz or 30 MHz passive crystal should be  
1
2
connected across the two pins (OSC and OSC ).  
1
2
Optionally, a 12 MHz or 30 MHz oscillator can be  
connected to OSC while keeping OSC unconnected  
1
2
49  
63  
1
1
O
I
OSC  
Output  
CLKCFG  
Indicates whether a 12 MHz or a 30 MHz crystal/  
oscillator is being used.  
0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on  
OSC  
1
1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on  
OSC  
1
Internal VBUS Charge Pump (3 pins)  
68  
1
O
PD_PMOS  
Internal charge pump output for P-MOSFET (optional  
switch on the VOUT)  
71  
67  
1
1
O
I
EXT  
Internal charge pump output for N-MOSFET  
VOUT  
Internal charge pump output voltage feedback pin  
Internal Voltage Regulator (2 pins)  
79  
1
I
ENVREG  
Enables the internal voltage regulator if asserted. If  
not used, this pin should be tied to V  
SS  
12  
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Table 13 OXU121HP 100-Pin LQFP Pin Allocations (Sheet 3 of 3)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
80  
1
O
VREGOUT  
Internal voltage regulator output of 1.8 V. If enabled,  
this output should be connected to the V (and  
DD1.8  
V
if wide-range IO is at 1.8 V) supplies of the  
DDW  
chip. If the regulator is disabled, then this pin should  
be treated as another V supply input to the chip  
DD1.8  
Test (3 pins)  
87  
1
1
1
ID  
ID  
I
TEST  
Factory test mode. This pin should be grounded or  
left floating (has an internal pull-down) for normal  
operation. Pull-down is always enabled  
37  
64  
ATEST13  
XMODE  
Additional address pin for debug use. Should be  
grounded or left floating (has an internal pull down)  
for normal use. Pull-down is always enabled  
This pin must be grounded for normal operation  
Miscellaneous (4 pins)  
91, 94  
38, 52  
2
2
-
-
RSVD , RSVD  
Reserved  
0
1
NC  
No connection. This pin should be left floating  
Note to Table 13:  
1
Type key: format is [(L)(W_)X(Y)(_Z(A))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
Tristate  
Normal  
(2)  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
5
5 V  
I
U
D
T
M
C
3.3 V  
O
Output  
Pull down  
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.  
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configura‐  
tion Register (0x034).  
DS-0040 Aug 06  
External--Free Release  
13  
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Figure 3 shows the chip layout of the 84‐ball BGA package.  
Figure 3 OXU121HP 84-Ball BGA Package (Top View)  
VSSA  
VSSA  
EXT  
VOUT  
PD_PMOS  
VSSA  
XMODE  
CLKCFG  
ID  
/PO  
VBP  
/OC  
DM 1  
VDD3.3  
VDD3.3A  
VSS  
DP1  
OSC2  
RREF  
DPP  
/CS  
OSC1  
VDD3.3A  
VSSA  
10  
9
DM  
2
VDD3.3A  
VBUS  
DP  
2
V
DD3.3A  
ENVREG  
GPIO  
V
DD3.3A  
VREGOUT  
TEST  
VSS  
/EXVBO  
8
7
6
5
4
3
2
1
DRQ 0  
VDD3.3  
VDD1.8  
D1  
DM P  
DRQ1  
/RESET  
VSSA  
OXU121HP-PBBG  
ACK  
0
VDDW  
RSVD  
0
1
A12  
ATEST13  
ACK1  
D0  
A10  
9
A
A
A
A
A
11  
RSVD  
D2  
VSS  
VDD1.8  
VDDW  
/WR  
INT  
VDD1.8  
A7  
A3  
8
D11  
D10  
D3  
D6  
D8  
D13  
D14  
A2  
5
D4  
D5  
12  
D15  
D7  
D9  
D
/RD  
A1  
A4  
6
A
B
C
D
E
F
G
H
J
K
14  
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Table 14 lists the BGA pin allocations.  
Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 1 of 3)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Processor Interface (37 pins)  
A3, C4, B3, A2, A1,  
B1, B2, C1, C2, D1,  
D2, D3, E1, E2, F2,  
F1  
16  
MSBCT  
D - D  
16-bit data bus. Pull-up/pull-down can be controlled  
through register 0x034, bits 2:1. Default is none  
0
15  
H1, H2, J2, J1, K2,  
K1, J3, K3, J4, H4,  
K4, J5  
12  
MSID  
A - A  
Address bus for direct address space of 8 Kbytes. Pull-up  
can be enabled through register 0x034, bits 9:8. Default  
is pull-down  
1
12  
G3  
G1  
J6  
1
1
1
1
MSIU  
MSIU  
MSIU  
MOCT  
/WR  
/RD  
/CS  
/INT  
Write strobe. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Read strobe. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
Chip select. Pull-up can be disabled through register  
0x034, bit 13. Default is pull-up  
G2  
Interrupt to the MCU.This pin can be software configured  
as a driven output or open drain. Open drain is the  
default  
B6  
1
2
MSIU  
/RESET  
DRQ , DRQ  
Hardware reset. Pull-up is always enabled  
DMA request outputs to support two channels  
C7, A6  
MOCT  
0
1
A5, A4  
2
MSI  
ACK , ACK  
DMA acknowledge. Pull-up/pull-down can be controlled  
through register 0x03A, bits 1:0. Default is none  
1
0
General Purpose I/O (1 pin)  
B7  
Power & Ground (20 pins)  
1
B
GPIO  
General purpose I/O  
C3, C8, H6  
3
5
3
V
V
V
Digital ground  
Analog ground  
SS  
B10, C10, E8,K6, K8  
C5, E3, H3  
SSA  
DD1.8  
1.8 V core power. VREGOUT may be used for these  
supplies  
B9, C9, D9, H7, K9  
C6, H8  
5
2
2
V
V
V
Analog +3.3 V power  
Digital +3.3 V power  
DD3.3A  
DD3.3  
DDW  
F3, H5  
Wide-range I/O +1.8 V to +3.3 V. If using +1.8 V,  
VREGOUT may be used for these supplies  
USB Interface (13 pins)  
A9, A10  
2
2
B
B
DP , DM  
Data lines for host port 2, a dedicated USB host port. If  
not used, these pins should be left floating  
2
2
1
J10, H9  
J7, K7  
DP , DM  
Data lines for host port 1, which can serve as a USB host  
or an OTG port in combination with the peripheral port. If  
not used, these pins should be left floating  
1
2
B
DP , DM  
Data lines for USB peripheral port, which can serve as an  
OTG port in combination with host port 1. If not used,  
these pins should be left floating  
P
P
DS-0040 Aug 06  
External--Free Release  
15  
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 2 of 3)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
D8  
1
5I  
VBUS  
VBUS input used by the voltage comparators of the OTG  
port for connection. This pin should be left floating in a  
host only application  
G9  
G8  
1
1
OC  
VBP  
VBUS pulsing control. This pin is used only when the  
OTG port is operating as a B-device  
P5O  
/EXVBO  
Turn on/off the external V  
(5 V) for OTG operation  
BUS  
(1:V  
off, 0:V  
on) when using the external charge  
BUS  
BUS  
pump  
H10  
J8  
1
1
IU  
B
/OC  
Over current condition indicator for powered host ports.  
Pull-up is always enabled  
R
Connect external reference resistor (12 KΩ +/- 1%) to  
REF  
V
SSA  
F8  
1
IU  
ID  
Connected to the ID pin of the mini-AB connector for  
OTG applications. With the help of an internal pull-up  
resistor, this pin determines the chip’s responsibility in an  
OTG application (0: A-device, 1:B-device). Pull-up can be  
disabled through register 0x038, bits 7:6. Default is pull-  
up  
G10  
1
1
P5O  
I
/PO  
Turn on/off gang power for all host ports  
Clock Interface (3 pins)  
K10  
OSC  
Input. A 12 MHz or 30 MHz passive crystal should be  
1
2
connected across the two pins (OSC and OSC ).  
1
2
Optionally, a 12 MHz or 30 MHz oscillator can be  
connected to OSC while keeping OSC unconnected  
1
2
J9  
1
1
O
I
OSC  
Output  
F9  
CLKCFG  
Indicates whether a 12 MHz or a 30 MHz crystal/oscillator  
is being used.  
0 = 12 MHz crystal or 12 MHz 3.3 V oscillator input on  
OSC  
1
1 = 30 MHz crystal or 30 MHz 3.3 V oscillator input on  
OSC  
1
Internal VBUS Charge Pump (3 pins)  
E9  
1
O
PD_PMOS  
Internal charge pump output for P-MOSFET (optional  
switch on the VOUT)  
D10  
E10  
1
1
O
I
EXT  
Internal charge pump output for N-MOSFET  
VOUT  
Internal charge pump output voltage feedback pin  
Internal Voltage Regulator (2 pins)  
B8  
1
I
ENVREG  
Enables the internal voltage regulator if asserted. If not  
used, this pin should be tied to V  
SS  
A8  
1
O
VREGOUT  
Internal voltage regulator output of 1.8 V. If enabled, this  
output should be connected to the V , (and V if  
DD1.8  
DDW  
wide-range IO is at 1.8 V) supplies of the chip. If the  
regulator is disabled, then this pin should be treated as  
another V supply input to the chip  
DD1.8  
16  
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Table 14 OXU121HP 84-Ball BGA Pin Allocations (Sheet 3 of 3)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Test (3 pins)  
A7  
1
ID  
TEST  
Factory test mode. This pin should be grounded or left  
floating (has an internal pull-down) for normal operation.  
Pull-down is always enabled  
K5  
1
ID  
ATEST13  
XMODE  
Additional address pin for debug use. Should be  
grounded or left floating (has an internal pull down) for  
normal use. Pull-down is always enabled  
F10  
1
2
I
This pin must be grounded for normal operation  
Miscellaneous (2 pins)  
B5, B4  
-
RSVD , RSVD  
0 1  
Reserved  
Note to Table 14:  
1
Type key: format is [(L)(W_)X(Y)(_Z(A))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Input  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
Tristate  
Normal  
(2)  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
5
5 V  
I
U
D
T
M
C
3.3 V  
O
Output  
Pull down  
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.  
Program to 2 mA, 4 mA, 6 mA, 8 mA, 10 mA, 12 mA, 14, mA, or 16 mA via the I/O Configura‐  
tion Register (0x034).  
DS-0040 Aug 06  
External--Free Release  
17  
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Package  
Layout  
Figure 4 shows the package layout for the 100‐pin LQFP package.  
Figure 4 100-Pin LQFP  
18  
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Figure 5 shows the layout for the 84‐ball TFBGA.  
Figure 5 84-Ball TFBGA Package  
1 of 2  
DS-0040 Aug 06  
External--Free Release  
19  
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
Figure 5 84-Ball TFBGA Package (continued)  
2 of 2  
20  
External--Free Release  
DS-0040 Aug 06  
Oxford Semiconductor, Inc.  
OXU121HP Data Sheet  
Ordering  
Information  
The following conventions are used to identify Oxford Semiconductor  
products.  
OXU121HP - LQBG  
Green (RoHS compliant)  
Revision  
Package Type: LQ 100-Pin LQFP  
Part Number  
OXU121HP - PBBG  
Green (RoHS compliant)  
Revision  
Package Type: PB 84-Ball TF-BGA  
Part Number  
Contacting  
Oxford Semi-  
conductor  
See the Oxford Semiconductor website (http://www.oxsemi.com) for  
further detail about Oxford Semiconductor devices, or email  
sales@oxsemi.com.  
Revision  
Table 15 documents the revisions of this guide.  
Information  
Table 15 Revision Information  
Revision  
Modification  
August 06  
First publication  
DS-0040 Aug 06  
External--Free Release  
21  
OXU121HP Data Sheet  
Oxford Semiconductor, Inc.  
USBLink is a trademark of Oxford Semiconductor, Inc.  
VxWorks is a registered trademark of Wind River Systems.  
ThreadX is a registered trademark of Express Logic, Inc.  
Nucleus is a registered trademark of Mentor Graphics Corporation.  
Symbian OS is a registered trademark of Symbian Ltd.  
Windows is a trademark of Microsoft, Inc., registered in the US and other countries.  
LynxOS is a registered trademark of LynuxWorks, Inc.  
AMX is a trademark of KADAK Products LTD.  
Linux is a registered trademark of Linus Torvalds.  
All other trademarks are the property of their respective owners.  
© Oxford Semiconductor, Inc. 2006  
The content of this document is furnished for informational use only, is subject to change without notice, and should not be  
construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for  
any errors or inaccuracies that may appear in this document.  
22  
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