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OXU210HP-LQAG

型号：

OXU210HP-LQAG

品牌：

OXFORD[ OXFORD SEMICONDUCTOR ]

页数：

18 页

PDF大小：

398 K

下载PDF手册
Data Sheet  
OXU210HP  
USB2.0 High-Speed Host, Peripheral and OTG Controller  
Features  
„
„
High‐performance, high‐speed USB dual‐role (host/peripheral)  
controller  
Compatible with the Universal Serial Bus Specification, Revision 2.0  
for high‐speed (480 Mb/s), full‐speed (12 Mb/s), and low‐speed  
(1.5 Mb/s) operations  
„
„
High‐speed optimized host controller with transaction translator  
for complete backward compatibility with full‐speed and  
low‐speed products  
Two high‐speed USB ports; one port remains host while the other  
can be configured as peripheral, host or OTG (dual role)  
„
„
Simultaneous operation of both ports  
Processor interface is either 16 bits (BGA) or configurable 16 or 32  
bits (LQFP)  
„
„
„
Fast microprocessor access cycle and double/multi buffering  
support for USB transfers  
Host interface contains support for common SoC DMA modes  
including bursting and slave request/acknowledge protocols  
Complete host, peripheral and OTG software solutions for  
popular microprocessors using many of the most popular  
operating systems  
„
„
„
„
Advanced power management controls chip clocking and PHY  
function for very low power consumption  
Integrated on‐chip VBUS voltage comparator and 100 mA charge  
pump  
72 Kbytes of single‐port SRAM provides space for data structures  
and buffer space for transfer data  
True transfer level operation, with transaction scheduling and  
handling (data sequence toggle, error retry, etc.), implemented in  
hardware  
„
Integrated PLL runs from a single 12‐MHz crystal or an external  
12‐MHz clock source  
DS-0037 Jun 06  
External--Free Release  
1
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
„
„
Packaging  
†
7×7 mm BGA, 84‐ball, RoHS compliant  
14×14 mm LQFP, 128‐pin, RoHS compliant  
†
Operating temperature range: ‐40° to 85° C  
Device  
Overview  
The Oxford Semiconductor OXU210HP is a single‐chip, high‐speed USB  
host and high‐speed USB peripheral controller with integrated  
transceivers. It is the fourth controller in the family of integrated  
low‐cost, high‐performance, OTG controllers that have been specifically  
designed for embedded systems.  
The OXU210HP operates at up to 480 Mb/s, using a compatible  
EHCI‐based core. It also includes an integrated transaction translator  
that supports full‐speed (12 Mb/s) and low‐speed (1.5 Mb/s) USB  
peripherals.  
The selectable 16‐ and 32‐bit processor interface is compatible with a  
variety of CPUs. A large 72‐Kbyte buffer has also been integrated to  
reduce interrupts and minimize CPU overhead.  
The OXU210HP supports all USB transfer modes (control, interrupt,  
bulk and isochronous) and is supported with USB device drivers and the  
Oxford Semiconductor USBLink product suite. The USBLink host,  
peripheral and OTG stacks have been ported to a wide variety of real  
time operating systems including VxWorks®, ThreadX®, and Nucleus®.  
In addition, Oxford Semiconductor also makes available low‐level  
controller drivers for other native USB stacks such as those included with  
Windows® CE and Linux® 2.6.x.  
2
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Figure 1 shows the OXU210HP block diagram.  
Figure 1 OXU210HP Block Diagram  
XSCI  
PLL/  
72 KB  
Buffer  
Test  
Superior  
TEST  
Clock  
Control  
Performance  
Large internal RAM  
allows for multi-  
buffering  
XSCO  
Memory  
Transaction  
Translator  
ACK  
DRQ  
simultaneous  
DMA  
streams. Retries due  
to USB NAKs are  
done in hardware -  
decreasing interrupts  
and lowering CPU  
and bus utilization.  
Interface  
HS  
OTG  
Xcvr  
Host  
Controller  
2 Ports  
Power  
allow multiple usage  
models:  
Management  
Transaction  
Translator  
2 Hosts  
Low Power  
Host + Peripheral, or  
Host + OTG  
Design  
Multiple power and  
clock regions are  
available with  
software-controlled  
power saving modes.  
PLL and oscillator  
can be disabled for  
deep-sleep state.  
Clock control block  
produces the lowest  
of four primary clock  
16/32-bit  
Microprocessor  
Interface  
ADDR  
DATA  
Host  
Controller  
HS  
OTG  
Xcvr  
Peripheral  
Controller  
System  
Configuration &  
Control Registers  
CNTRL  
INT  
OTG  
Controller  
frequesncies that meet  
the application’s  
operational  
Simultaneous Operation  
Full host controller and peripheral  
controller implementations allow both  
to operate at the same time.  
requirements.  
OTG Logic  
Integrated hardware or software  
HNP options allw for more  
control of your software  
development.  
Sample  
Applications  
„
„
„
„
„
„
„
„
„
„
„
„
„
Digital televisions  
Home media centers  
Portable media centers  
Digital video cameras  
Digital still cameras  
Printers  
MP3 players  
External storage products  
Set‐Top Boxes (STB)  
Personal Video Recorders (PVR)  
Personal Digital Assistants (PDA)  
3G mobile phones  
DVD recorders  
DS-0037 Jun 06  
External--Free Release  
3
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Development  
Support  
The OXU210HP product suite includes the USB controller as well as the  
protocol stacks and the driver software that enable a wide variety of USB  
applications. This unique ability to deliver a total hardware and software  
solution sets Oxford Semiconductor apart from other semiconductor  
companies and benefits customers by:  
„
„
„
Shortening time to market  
Reducing risk  
Offering a single source for hardware and software, thereby  
reducing the number of suppliers the customer has to deal with  
Oxford Semiconductor is a Microsoft® Windows® Embedded Partner  
and has developed host and peripheral controller drivers for Windows  
CE 5.0. Similar software support is also available for Linux® 2.6.x.  
For customers using an RTOS such as VxWorks®, ThreadX®, Nucleus®,  
OSE, LynxOS®, and AMXTM, among others, Oxford Semiconductor  
offers its USBLinkTM host, peripheral and On‐The‐Go software solutions.  
The USBLink Product Suite is a modularized approach to providing USB  
connectivity for a wide variety of embedded products. Due to its flexible  
architecture and broad based support for USB host, peripheral and OTG  
applications, Oxford Semiconductor can tailor the USBLink software  
deliverables to meet each customer’s USB requirements.  
The USBLink solutions are configurable and can support systems with:  
„
„
„
„
Big or little endian processors  
DMA or non‐DMA USB controllers  
A wide variety of USB controllers, including the OXU210HP  
Complex to simple operating systems  
Oxford Semiconductor has over eight years of experience developing  
embedded USB technology. Its USBLink software has been ported to  
twenty different operating systems and a wide variety of embedded  
architectures. USBLink is shipping in many millions of units.  
4
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Electrical  
Characteristics  
Table 1 to Table 10 detail the required operating conditions for the  
device and the DC and AC electrical characteristics.  
Table 1 Absolute Maximum Device Ratings  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
3.3 V digital power supply  
-0.3  
4.0  
V
PWM3,  
DD3IO  
V
V
V
3.3 V analog power supply  
1.8 V power supply  
-0.3  
-0.3  
-0.3  
4.0  
2.16  
4.0  
V
V
V
DD3.3A  
DD1.8  
IO  
1.65 V to 3.3 V power  
supply  
V
T
DC input voltage  
-0.3  
-40  
4.0  
V
I
Storage temperature  
+150  
°C  
S
Note:  
1
Permanent device damage may occur if absolute maximum ratings are exceeded.  
Functional operation should be restricted to the normal operating conditions speci‐  
fied in the following section. Exposure to absolute maximum rating conditions for  
extended periods may affect device reliability.  
Table 2 Recommended Operating Conditions  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
3.3 V digital power supply  
3.0  
3.6  
V
PWM3,  
DD3IO  
DD3.3A  
DD1.8  
IO  
V
V
V
3.3 V analog power supply  
1.8 V power supply  
3.0  
3.6  
1.98  
3.6  
V
V
V
1.62  
1.65  
1.65 - 3.3 V  
wide-range I/O power supply  
V
V
T
DC input voltage of 3.3 V pins  
DC input voltage of wide-range pins  
Operating temperature  
0
0
3.6  
V
V
I3.3  
IW  
V
+ 0.3  
IO  
-40  
+85  
°C  
O
Table 3 DC Characteristics, Full-Speed USB I/O Signals: DP_HOST, DM_HOST, DP_OTG, DM_OTG  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
V
V
V
Diff. input sensitivity  
|V  
– V |  
I(DM)  
0.2  
--  
V
DI  
I(DP)  
Diff. comm. mode range  
Static output low  
0.8  
--  
2.5  
0.3  
3.6  
2.0  
20  
V
V
CM  
OL  
Static output high  
2.8  
1.3  
V
OH  
CRS  
Output signal crossover  
Input capacitance  
V
C
pF  
IN  
DS-0037 Jun 06  
External--Free Release  
5
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 4 DC Characteristics, High-Speed USB I/O Signals: DP_HOST, DM_HOST, DP_OTG, DM_OTG  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
V
High-speed differential input |V  
sensitivity  
– V |  
I(DM)  
300  
--  
mV  
HSDIFF  
I(DP)  
High-speed data signaling  
common mode range  
-50  
500  
mV  
HSCM  
HSSQ  
High-speed squelch  
detection threshold  
Squelch detected  
--  
100  
--  
mV  
mV  
mV  
No squelch detected  
150  
-10  
V
V
V
V
V
High-speed idle output  
voltage (differential)  
10  
HSOI  
High speed low level output  
voltage (differential)  
-10  
-360  
700  
10  
mV  
mV  
mV  
mV  
HSOL  
High speed high level  
output voltage (differential)  
400  
HSOH  
CHIRPJ  
CHIRPK  
Chirp-J output voltage  
(differential)  
1100  
-500  
Chirp-K output voltage  
(differential)  
-900  
Table 5 DC Characteristics, Logic Signals  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
V
V
Low level output voltage  
--  
0.4  
V
OL  
High level output voltage  
Low level input voltage  
High level input voltage  
V
2.4  
1.85  
0.75 * V  
--  
--  
--  
V
V
OH  
IL  
IO = 3.3 V  
IO = 2.5 V  
IO = 1.8 V  
IO = 3.3 V  
IO = 2.5 V  
IO = 1.8 V  
IO = 3.3 V  
IO = 2.5 V  
IO = 1.8 V  
V
V
V
V
V
V
V
V
IO  
V
V
0.8  
V
V
--  
0.25 * V  
IO  
0.3 * V  
2.0  
--  
--  
--  
--  
IO  
V
V
IH  
0.625 * V  
IO  
0.7 * V  
IO  
C
C
C
I
Input Capacitance  
2.2 (typical)  
2.2 (typical)  
2.2 (typical)  
pF  
pF  
IN  
Output Capacitance  
Bi-directional Capacitance  
Input leakage current  
OUT  
BI  
pF  
No pull up or pull down  
-10  
10  
µA  
IN  
Note:  
1
The chargepump supply VCPSUPPLY supplies the external components of the chargepump cir‐  
cuit. This is not a pin on the chip.  
6
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Table 6 DC Characteristics, ID Resistance  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
R
R
Resistance to ground on  
Mini-B plug  
100 K  
--  
Ω
B-PLUG-ID  
Resistance to ground on  
Mini-B plug  
--  
10  
Ω
A-PLUG-ID  
Table 7 DC Characteristics, Chargepump  
Symbol Parameter  
Output voltage  
Condition  
Min  
Max  
Unit  
CV  
4.75  
5.07  
V
out  
Driving current <= 100 mA  
CI  
Driving current  
--  
100  
mA  
drive  
V
= 3.3 V  
CPSUPPLY  
Output Voltage = 5 V  
V = 3.3 V  
CPSUPPLY  
Ct  
Start-up time when enabled  
400 (typical)  
µs  
st  
RV = 4.5 V (90%)  
out  
Table 8 AC Characteristics, DP_HOST, DM_HOST, DP_OTG, DM_OTG Driver Characteristics (High Speed)  
Symbol  
Parameter  
Condition  
Min  
Max  
Unit  
t
t
High speed differential rise  
time  
500  
--  
ps  
HSRt  
High speed differential fall  
time  
500  
--  
ps  
HSF  
R
Driver output impedance  
40.5  
49.5  
Ω
DRV  
Equivalent resistance used as internal  
chip  
Table 9 AC Characteristics, DP_HOST, DM_HOST, DP_OTG, DM_OTG Driver Characteristics (Full Speed)  
Symbol  
Parameter  
Rise time  
Fall time  
T /T matching  
Condition  
Min  
Max  
Unit  
t
t
t
4
20  
ns  
FR  
C = 50 pF  
L
4
20  
ns  
FF  
C = 50 pF  
L
90  
3
110  
9
%
FRFM  
R F  
Z
Driver output resistance  
Ω
DRV  
Steady state drive with external 33 Ω  
series resistor  
Table 10 AC Characteristics, DP_HOST, DM_HOST, DP_OTG, DM_OTG Driver Characteristics (Low Speed)  
Symbol  
Parameter  
Rise time  
Fall time  
T /T matching  
Condition  
C = 200 - 600 pF  
Min  
Max  
Unit  
t
t
t
75  
300  
ns  
LR  
L
75  
80  
300  
125  
ns  
%
FF  
C = 200 - 600 pF  
L
FRFM  
R F  
DS-0037 Jun 06  
External--Free Release  
7
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Power  
Table 11 gives the power consumption figures for the OXU210HP.  
Consumption  
Table 11 OXU210HP Power Consumption  
Mode  
3.3 V (mA)  
0.06  
1.8 V (mA)  
0.2  
Power (mW)  
0.56  
Full-power down  
Power down, remote wakeup enabled (PHY PLL enabled during power  
down)  
0.66  
0.24  
2.61  
Idle but clocking @ 120 MHz (port suspend)  
23  
33  
25  
61  
56  
91  
56  
60  
35  
70  
59  
59  
177  
217  
146  
327  
291  
407  
FS bulk in/out transfers @ OTG port, peak current (120 MHz), SPH idle  
FS transmit of test packet, both ports (60 MHz)  
HS bulk in/out transfers @ OTG port, peak current (120 MHz), SPH idle  
HS transmit of test packet, OTG port only (120 MHz)  
HS transmit of test packet, both ports (120 MHz)  
The above measurements are at typical process corner and room  
temperature and do not account for process and temperature variations.  
Bulk transfer current measurements are made at the peak of each  
transfer. Actual average current in customer application will be lower.  
Transmit of test packet measurements are taken in test mode and  
represent maximum switching on the bus.  
8
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Pin Layout  
The device is supplied as a 128‐pin LQFP package and as an 84‐ball BGA  
package. Figure 2 shows the chip layout of the 128‐pin LQFP package.  
Figure 3 shows the chip layout of the 84‐ball BGA package.  
Figure 2 OXU210HP 128-Pin LQFP Package (Top View)  
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65  
96 95 94 93 92 91 90 89 88  
GPIO  
VDD3.3A  
1
97  
64  
63  
GPIO  
98  
2
DP_OTG  
62 DM_OTG  
GPIO  
99  
3
DEBUG4  
61  
60  
REF_OTG  
VSSA  
100  
DEBUG5 101  
DEBUG6  
DEBUG7  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
59 VDD3.3A  
58 XSCO  
V
IO  
57  
56  
55  
54  
53  
52  
51  
XSCI  
VSS  
VSS  
A1  
A2  
A3  
VSS  
VDD1.8  
VDD1.8  
VDD3.3A  
VSSA  
A4  
A5  
A6  
50 REF_HOST  
49 DM_HOST  
A7  
A8  
VDD1.8  
48  
47 VDD3.3A  
VSSA  
45 BE  
DP_HOST  
VSS  
46  
A9  
A10  
A11  
A12  
A13  
3
BE  
44  
43  
42  
2
BE  
1
BE  
0
41 D23  
40  
39 D21  
V
IO  
D22  
VSS  
A14  
A15  
A16  
38  
37  
D20  
D19  
36 D18  
35 D17  
34 D16  
/CS  
/WR  
VSS  
33  
128  
D15  
16  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
7
1
2
3
4
5
6
8
9
10 11 12 13 14 15  
DS-0037 Jun 06  
External--Free Release  
9
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 12 lists the LQFP pin allocations.  
Table 12 OXU210HP 128-Pin LQFP Pin Allocations (Sheet 1 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
Processor Interface (61 pins)  
14, 15, 16, 17, 19, 16  
20, 21, 22, 23, 24,  
25, 26, 30, 31, 32,  
33  
MSBCT  
D - D  
16-bit data bus  
0
15  
2, 3, 4, 5, 8, 9, 10, 16  
11, 34, 35, 36, 37,  
38, 39, 40, 41  
MSBCT  
MSI  
D
- D  
Additional 16-bits of data bus for optional 32-bit  
mode. In 16-bit mode, these signals have an internal  
pull down  
16  
31  
106, 107, 108,  
109, 110, 111,  
112, 113, 116,  
117, 118, 119,  
120, 123, 124,  
125  
16  
A - A  
Address bus for direct address space of 72 Kbytes  
plus memory mapped registers  
1
16  
127  
1
1
1
1
1
MSIU  
MSIU  
MSIU  
MOCT  
/WR  
/RD  
/CS  
/INT  
Write strobe  
Read strobe  
Chip select  
126  
83  
Interrupt to the MCU.This pin can be software  
configured as a driven output or WO. WO is the  
default  
84  
1
2
2
2
2
I
/RESET  
DRQ , DRQ  
Hardware reset  
90, 91  
92, 93  
42, 43  
44, 45  
MOCT  
SI  
DMA request outputs to support two channels  
DMA acknowledge  
1
0
ACK , ACK  
1
0
MSI  
MSID  
BE , BE  
Byte enables  
0
1
3
BE , BE  
Byte enables. These signals have an internal pull  
down.  
2
General Purpose I/O (4 pins)  
96, 97, 98, 99  
4
BC  
GPIO - GPIO  
General purpose I/O  
Digital ground  
0
3
Power and Ground (38 pins)  
7, 13, 28, 29, 55, 13  
56, 79, 82, 95,  
105, 115, 122,  
128  
V
SS  
46, 51, 60, 65, 68,  
73  
6
V
V
Analog ground  
SSA  
18, 53, 54, 81,  
114  
5
1.8 V core power. VREGOUT may be used for the  
supplies  
DD1.8  
47, 52, 59, 64, 72  
5
7
V
V
Analog +3.3 V power  
DD3.3A  
IO  
6, 12, 27, 80, 94,  
104, 121  
Wide-range I/O voltage. If using +1.8 V, VREGOUT  
may be used for the supplies  
74  
1
V
Digital +3.3 V power  
DD3IO  
10  
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Table 12 OXU210HP 128-Pin LQFP Pin Allocations (Sheet 2 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
67  
1
V
Analog 3.3 V power for the charge pump Pulse Width  
Modulator (PWM)  
PWM3  
USB Interface (9 pins)  
48, 49  
62, 63  
71  
2
2
1
B
B
DP_HOST, DM_HOST  
DP_OTG, DM_OTG  
VBUS  
Data lines for host port. If not used, these pins should  
be left floating  
Data lines for OTG port. If not used, these pins  
should be left floating  
5I  
VBUS input used by the voltage comparators of the  
OTG port for connection. This pin should be left  
floating in a host-only application  
75  
1
P5O  
/EXVBO  
Turn on/off the external V  
(5 V) for OTG  
BUS  
operation (1:V  
off, 0: V  
on) when using the  
BUS  
BUS  
external VBUS source  
76  
77  
1
1
P5IU  
P5IU  
/OC  
ID  
Over current condition indicator for powered host  
ports  
Connected to the ID pin of the mini-AB connector for  
OTG applications. With the help of an internal pull-up  
resistor, this pin determines the chip’s responsibility  
in an OTG application (0: A-device, 1:B-device)  
78  
1
P5OT  
I
/PO  
Turn on/off gang power for all host ports  
Clock Interface (2 pins)  
57  
1
XSCI  
Input. A 12 MHz passive crystal should be connected  
across the two pins (XSCI and XSCO). Optionally, a  
12 MHz oscillator can be sourced through XSCI  
while keeping XSCO unconnected  
58  
1
O
XSCO  
Output  
Internal VBUS Charge Pump (3 pins)  
69  
1
O
PD_PMOS  
Internal charge pump output for P-MOSFET (optional  
switch on the VOUT)  
66  
1
1
O
I
EXT  
Internal charge pump output for N-MOSFET  
70  
VOUT  
Internal charge pump output voltage feedback pin  
Test (9 pins)  
85, 86, 87, 88,  
100, 101, 102,  
103  
8
1
OC  
I
DEBUG - DEBUG  
Debug outputs  
0
7
89  
TEST  
Factory test mode. This pin should be grounded or  
left floating (has an internal pull-down) for normal  
operation  
Miscellaneous (2 pins)  
50  
61  
1
1
B
B
REF_HOST  
REF_OTG  
Connect external reference resistor (12 KW +/‐  
1%) to V . One per port  
SSA  
DS-0037 Jun 06  
External--Free Release  
11  
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Note to Table 12:  
1
Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
T Tristate  
(2)  
(4)  
OD  
5
5 V  
I
Input  
U
D
P
C
3.3 CMOS  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
3.3 V  
O
Output  
Pull down  
Normal  
M
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to OD or 3.3 V CMOS via the ASO register (0x0068).  
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.  
4
Program to 2 mA, 4 mA, 6 mA, or 8 mA via the I/O Control register (0x006C).  
12  
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Figure 3 OXU210HP 84-Ball BGA Package (Top View)  
1
2
3
4
5
6
7
8
9
10  
A15  
A13  
A11  
A10  
A7  
A6  
A4  
A2  
ACK0  
/CS  
A
B
C
D
E
F
A14  
A12  
A9  
A8  
A5  
A3  
VDD1.8  
VIO  
GPIO0  
A1  
DRQ0  
TEST  
/RD  
D0  
/WR  
A16  
D2  
VSS  
VIO  
VSS  
VDD1.8  
VSS  
D1  
VSS  
/INT  
/RESET  
/PO  
D3  
D4  
VDD1.8  
VSS  
ID  
OXU210HP-PBAG  
D6  
D5  
D7  
VSSA  
/EXVBO  
VBUS  
VPWM3  
VSSA  
/OC  
D8  
D9  
VSS  
VDD3.3A  
VOUT  
G
H
J
D11  
D13  
D15  
D10  
D12  
D14  
VSSA  
VDD3.3A  
VDD3.3A  
VDD3.3A  
VDD3IO  
XSCI  
VSSA  
VSSA  
PD_PMOS  
EXT  
BE1  
BE0  
VSSA  
VIO  
VDD3.3A  
DM_OTG  
DM_HOST  
DP_HOST  
REF_HOST  
XSCO  
DP_OTG  
REF_OTG  
K
DS-0037 Jun 06  
External--Free Release  
13  
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Table 13 lists the BGA pin allocations.  
Table 13 OXU210HP 84-Ball BGA Pin Allocations (Sheet 1 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Type  
MSBCT  
MSI  
Processor Interface (41 pins)  
C1, D1, D2, E1, E2, 16  
F2, F1, F3, G1, G2,  
H2, H1, J2, J1, K2, K1  
D - D  
16-bit data bus  
0
15  
C9, A9, B8, A8, B7,  
A7, A6, B6, B5, A5,  
A4, B4, A3, B3, A2,  
C2  
16  
A - A  
Address bus for direct address space of 72 Kbytes plus  
memory mapped registers  
1
16  
B2  
B1  
A1  
D9  
1
1
1
1
MSIU  
MSIU  
MSIU  
MOCT  
/WR  
/RD  
/CS  
/INT  
Write strobe  
Read strobe  
Chip select  
Interrupt to the MCU.This pin can be software configured  
as a driven output or WO. WO is the default  
D10  
B10  
1
1
I
/RESET  
DRQ  
Hardware reset  
MOT  
DMA request outputs to support two channels  
0
A10  
1
2
SI  
ACK  
DMA acknowledge  
Byte enables  
0
J4, J3  
MSI  
BE , BE  
0 1  
General Purpose I/O (1 pin)  
B9  
Power and Ground (25 pins)  
1
B
GPIO  
General purpose I/O  
0
C3, C5, C7, D3, E8,  
G3  
6
V
Digital ground  
Analog ground  
SS  
F8, H3, H7, H8, J5, J9 6  
V
V
SSA  
C6, C8, E3  
3
1.8 V core power. VREGOUT may be used for the  
supplies  
DD1.8  
G8, H4, H5, H6, J8  
C4, D8, J7  
5
3
V
V
Analog +3.3 V power  
DD3.3A  
IO  
Wide-range I/O voltage. If using +1.8 V, VREGOUT may  
be used for the supplies  
J6  
1
1
V
V
Digital +3.3 V power  
DD3IO  
PWM3  
H9  
Analog 3.3 V power for the charge pump Pulse Width  
Modulator (PWM)  
USB Interface (9 pins)  
K4, K3  
2
2
1
B
B
5I  
DP_HOST, DM_HOST Data lines for host port. If not used, these pins should be  
left floating  
K8, K9  
G9  
DM_OTG, DP_OTG  
Data lines for OTG port. If not used, these pins should be  
left floating.  
VBUS  
VBUS input used by the voltage comparators of the OTG  
port for connection. This pin should be left floating in a  
host only application  
14  
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Table 13 OXU210HP 84-Ball BGA Pin Allocations (Sheet 2 of 2)  
(1)  
Pin  
No.  
Bits  
Name  
Description  
Turn on/off the external V (5 V) for OTG operation  
Type  
P5O  
F9  
1
/EXVBO  
BUS  
(1:V  
off, 0:V  
on) when using the external charge  
BUS  
BUS  
pump  
F10  
E9  
1
1
P5IU  
P5IU  
/OC  
ID  
Over current condition indicator for powered host ports  
Connected to the ID pin of the mini-AB connector for  
OTG applications. With the help of an internal pull-up  
resistor, this pin determines the chip’s responsibility in an  
OTG application (0: A-peripheral, 1:B-peripheral)  
E10  
1
1
P5O  
I
/PO  
Turn on/off the gang power for all host ports  
Clock Interface (2 pins)  
K6  
XSCI  
Input. A 12 MHz passive crystal should be connected  
across the two pins (XSCI and XSCO). Optionally, a 12  
MHz oscillator can be connected to XSCI while keeping  
XSCO unconnected  
K7  
1
O
XSCO  
Output  
Internal VBUS Charge Pump (3 pins)  
H10  
1
O
PD_PMOS  
Internal charge pump output for P-MOSFET (optional  
switch on the VOUT)  
J10  
1
1
O
I
EXT  
Internal charge pump output for N-MOSFET  
G10  
VOUT  
Internal charge pump output voltage feedback pin  
Test (1 pin)  
C10  
1
SIUC  
TEST  
Factory test mode. This pin should be grounded or left  
floating (has an internal pull-down) for normal operation  
Miscellaneous (2 pins)  
K5  
1
1
B
B
REF_HOST  
REF_OTG  
Connect external reference resistor (12 KΩ +/- 1%) to  
V
. One per port  
SSA  
K10  
Note to Table 13:  
1
Type key: format is [(L)(W_)X(Y)(_Z(T))] where the following conventions apply:  
L—Logic Level  
W—Tolerance  
X—Type  
Y—Pull  
Pull up  
Z—Drive  
T—Tristate  
T Tristate  
(2)  
(4)  
OD  
5
5 V  
I
Input  
U
D
P
C
3.3 CMOS  
(3)  
Multi-voltage:  
3.3 V CMOS  
2.5 V CMOS  
1.8 V CMOS  
3.3 V  
O
Output  
Pull down  
Normal  
M
S
Schmitt Trigger  
B
Bidirectional  
None  
2
3
Program to OD or 3.3 V CMOS via the ASO register (0x0068).  
Program to 3.3, 2.5, or 1.8 V by setting the VIO voltage level.  
4
Program to 2 mA, 4 mA, 6 mA, or 8 mA via the I/O Control register (0x006C).  
DS-0037 Jun 06  
External--Free Release  
15  
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Package  
Layout  
Figure 4 shows the package layout for the 128‐pin LQFP package.  
Figure 5 on page 17 shows the layout for the 84‐ball TFBGA.  
Figure 4 128-Pin LQFP  
16  
External--Free Release  
DS-0037 Jun 06  
Oxford Semiconductor, Inc.  
OXU210HP Data Sheet  
Figure 5 84-Ball TFBGA Package  
Ordering  
Information  
The following conventions are used to identify Oxford Semiconductor  
products:  
OXU210HP - LQAG  
Green (RoHS compliant)  
Revision  
Package Type: LQ 128-Pin LQFP  
Part Number  
OXU210HP - PBAG  
Green (RoHS compliant)  
Revision  
Package Type: PB 84-Ball TF-BGA  
Part Number  
DS-0037 Jun 06  
External--Free Release  
17  
OXU210HP Data Sheet  
Oxford Semiconductor, Inc.  
Contacting  
Oxford Semi-  
conductor  
See the Oxford Semiconductor website (http://www.oxsemi.com) for  
further detail about Oxford Semiconductor devices, or email  
sales@oxsemi.com.  
Revision  
Table 14 documents the revisions of this data sheet.  
Information  
Table 14 Revision Information  
Revision  
Modification  
Jun 06  
First publication  
USBLink is a trademark of Oxford Semiconductor, Inc.  
VxWorks is a registered trademark of Wind River Systems.  
ThreadX is a registered trademark of Express Logic, Inc.  
Nucleus is a registered trademark of Mentor Graphics Corporation.  
Symbian OS is a registered trademark of Symbian Ltd.  
Windows is a trademark of Microsoft, Inc., registered in the US and other countries.  
LynxOS is a registered trademark of LynuxWorks, Inc.  
AMX is a trademark of KADAK Products LTD.  
Linux is a registered trademark of Linus Torvalds.  
All other trademarks are the property of their respective owners.  
© Oxford Semiconductor, Inc. 2006  
The content of this document is furnished for informational use only, is subject to change without notice, and should not be  
construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for  
any errors or inaccuracies that may appear in this document.  
18  
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DS-0037 Jun 06  
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