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PXA210

型号：

PXA210

描述：

英特尔-R PXA250和PXA210应用处理器[ Intel-R PXA250 and PXA210 Applications Processors ]

品牌：

INTEL[ INTEL ]

页数：

46 页

PDF大小：

410 K

下载PDF手册
Intel® PXA250 and PXA210 Applications  
Processors  
Electrical, Mechanical, and Thermal Specification  
Datasheet  
Product Features  
High Performance Processor  
—Intel® XScale™ Microarchitecture  
—32 KB Instruction Cache  
—32 KB Data Cache  
Low Power  
—Less than 500 mW Typical Internal  
Dissipation  
—Supply Voltage may be Reduced to  
0.85 V  
—2 KB “mini” Data Cache  
—Extensive Data Buffering  
Intel® Media Processing Technology  
—Enhanced 16-bit Multiply  
—40-bit Accumulator  
—Low Power/Sleep Modes  
High Performance Memory Controller  
—Four Banks of SDRAM - up to 100 MHz  
—Five Static Chip Selects  
—Support for PCMCIA or Compact Flash  
—Companion Chip interface  
Flexible Clocking  
—CPU clock from 66 to 300 MHz  
—Flexible memory clock ratios  
—Frequency change modes  
Rich Serial Peripheral Set  
—AC97 Audio Port  
Additional Peripherals for system  
connectivity  
—Multimedia Card Controller (MMC)  
—SSP Controller  
—I2C Controller  
—I2S Audio Port  
—Two Pulse Width Modulators (PWMs)  
—All peripheral pins double as GPIOs.  
Hardware debug features  
—USB Client Controller  
—High Speed UART  
—Second UART with flow control  
—FIR and SIR infrared comm ports  
Hardware Performance Monitoring features  
Order Number: 278524-001  
February, 2002  
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual  
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability  
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to  
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not  
intended for use in medical, life saving, or life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for  
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.  
The Intel® PXA250 and PXA210 Applications Processors may contain design defects or errors known as errata which may cause the product to  
deviate from published specifications. Current characterized errata are available on request.  
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled  
platforms may require licenses from various entities, including Intel Corporation.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling  
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.  
Copyright © Intel Corporation, 2002  
*Other names and brands may be claimed as the property of others.  
2
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Contents  
1.0 About this Document.............................................................................................7  
2.0 Functional Overview..............................................................................................7  
3.0 Package Information..............................................................................................8  
3.1  
Package Introduction.....................................................................................8  
3.1.1 Functional Signal Definitions............................................................9  
3.1.1.1 PXA250 Signal Pin Descriptions ......................................9  
3.1.1.2 PXA210 Signal Pin Descriptions ....................................19  
Package Power Ratings..............................................................................29  
3.2  
4.0 Electrical Specifications......................................................................................29  
4.1  
4.2  
4.3  
4.4  
4.5  
Absolute Maximum Ratings.........................................................................29  
Operating Conditions...................................................................................30  
Targeted DC Specifications.........................................................................31  
Targeted AC Specifications.........................................................................32  
Oscillator Electrical Specifications...............................................................33  
4.5.1 32.768 kHz Oscillator Specifications..............................................33  
4.5.2 3.6864 MHz Oscillator Specifications.............................................34  
Reset and Power AC Timing Specifications................................................35  
4.6.1 Power On Timing............................................................................35  
4.6.2 Hardware Reset Timing..................................................................36  
4.6.3 Watchdog Reset Timing.................................................................37  
4.6.4 GPIO Reset Timing ........................................................................37  
4.6.5 Sleep Mode Timing ........................................................................38  
Memory Bus and PCMCIA AC Specifications.............................................39  
Peripheral Module AC Specifications..........................................................42  
4.8.1 LCD Module AC Timing..................................................................43  
4.8.2 SSP Module AC Timing..................................................................43  
4.8.3 Boundary Scan Test Signal Timings ..............................................44  
AC Test Conditions .....................................................................................45  
4.6  
4.7  
4.8  
4.9  
Datasheet  
3
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Figures  
1
2
3
4
5
6
7
8
9
Applications Processor Block Diagram .................................................................8  
PXA250 Applications Processor .........................................................................16  
PXA210 Applications Processor .........................................................................26  
Power-On Reset Timing......................................................................................36  
Hardware Reset Timing ......................................................................................37  
GPIO Reset Timing.............................................................................................37  
Sleep Mode Timing .............................................................................................38  
LCD AC Timing Definitions .................................................................................43  
SSP AC Timing Definitions .................................................................................44  
10 AC Test Load ......................................................................................................45  
Tables  
1
2
3
4
5
6
7
8
9
Related Documentation.........................................................................................7  
Pin and Signal Descriptions for the PXA250 Applications Processor ...................9  
PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order..............17  
Pin and Signal Descriptions for the PXA210 Applications Processor .................19  
PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order............27  
JA and Maximum Power Ratings........................................................................29  
Absolute Maximum Ratings ................................................................................29  
Voltage, Temperature, and Frequency Electrical Specifications.........................30  
Standard Input, Output, and I/O Pin DC Operating Conditions...........................31  
10 Standard Input, Output, and I/O Pin AC Operating Conditions...........................32  
11 32.768 kHz Oscillator Specifications...................................................................33  
12 3.6864 MHz Oscillator Specifications..................................................................34  
13 Power-On Timing Specifications.........................................................................36  
14 Hardware Reset Timing Specifications ...............................................................37  
15 GPIO Reset Timing Specifications......................................................................38  
16 Sleep Mode Timing Specifications......................................................................39  
17 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications....................39  
18 Variable Latency I/O Interface AC Specifications ...............................................40  
19 Card Interface (PCMCIA or Compact Flash) AC Specifications .........................41  
20 Synchronous Memory Interface AC Specifications1............................................42  
21 LCD AC Timing Specifications............................................................................43  
22 SSP AC Timing Specifications............................................................................44  
23 Boundary Scan Test Signal Timing.....................................................................44  
4
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Revision History  
Date  
Revision  
Description  
7/6/01  
2/8/02  
0.5  
First Release  
-001  
First public release of the EMTS  
Datasheet  
5
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
6
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
1.0  
About this Document  
This is the Electrical, Mechanical, and Thermal Specification datasheet for the Intel® PXA250 and  
PXA210 applications processors. This datasheet contains a functional overview, mechanical data,  
package signal locations, targeted electrical specifications (simulated), and bus functional  
waveforms. Detailed functional descriptions other than parametric performance is published in the  
Intel® PXA250 and PXA210 Applications Processors Developer's Manual. Refer to Table 1,  
“Related Documentation” for a list of documents that support the PXA250 and PXA210  
applications processors.  
Table 1. Related Documentation  
Document Title  
Order / Contact  
Intel Order # 278522  
Intel® PXA250 and PXA210 Applications  
Processors Developer's Manual  
Intel® XScaleTM Microarchitecture for the PXA250  
and PXA210 Applications Processors Developer's  
Manual  
Intel Order # 278525  
Intel Order # 278523  
Intel® PXA250 and PXA210 Applications  
Processors Design Guide  
2.0  
Functional Overview  
The PXA250 and PXA210 applications processors provide high integration, high performance and  
low power consumption for portable handheld and handset devices. These applications processors  
incorporate Intel’s XScaleTM Microarchitecture based on the ARM* V5TE architecture. Refer to  
the Intel® XScaleTM Microarchitecture for the Intel® PXA250 and PXA210 Applications  
Processors Developer's Manual for implementation details, extensions, and options implemented  
by Intel’s XScaleTM Microarchitecture.  
The applications processor’s memory interface supports a variety of memory types that allow  
flexibility in design requirements. Hooks for connection to two companion chips permit glueless  
connection to external devices. An integrated LCD display controller provides support for displays,  
and permits 1, 2 and 4 bit grayscale and 8 or 16 bit color pixels. A 256-byte palette RAM provides  
flexibility in color mapping.  
A rich set of serial devices as well as general system resources provide enough compute and  
connectivity capability for many applications. For details on the programming model and theory of  
operation of each of these units, refer to the Intel® PXA250 and PXA210 Applications Processors  
Developer's Manual. For the applications processor’s block diagram refer to Figure 1,  
“Applications Processor Block Diagram” on page 8.  
Datasheet  
7
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Figure 1. Applications Processor Block Diagram  
RTC  
Color or  
Grayscale  
LCD  
Memory  
Controller  
OS Timer  
PWM(2)  
Int Contr.  
Controller  
Clocks &  
Pwr Man.  
Variable  
Latency I/O  
Control  
ASIC  
I2 S  
System Bus  
DMA  
Controller  
And  
I2 C  
Socket 0  
Socket 1  
PCMCIA & CF  
Control  
AC97  
XCVR  
Bridge  
UART1  
UART2  
Dynamic  
Memory  
Control  
SDRAM/  
SMROM  
4 banks  
Megacell  
Core  
Slow IrDA  
Fast IrDA  
SSP  
ROM/  
Flash/  
SRAM  
Static  
Memory  
Control  
USB  
Client  
MMC  
3.6864 32.768  
MHz  
Osc  
KHz  
Osc  
4 Banks  
3.0  
Package Information  
3.1  
Package Introduction  
The applications processor is offered in two packages;  
• The PXA250 applications processor, 256-pin mBGA (refer to Figure 2, “PXA250  
Applications Processor” on page 16)  
• The PXA210 applications processor, 225-pin TPBGA package (refer to Figure 3, “PXA210  
Applications Processor” on page 26)  
8
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
3.1.1  
Functional Signal Definitions  
3.1.1.1  
PXA250 Signal Pin Descriptions  
Signal definitions for the PXA250 applications processor are described in Table 2, “Pin and Signal  
Descriptions for the PXA250 Applications Processor” on page 9. The physical characteristics of  
the PXA250 applications processor are shown in Figure 2, “PXA250 Applications Processor” on  
page 16. The pinout for the PXA250 applications processor is described in Table 3, “PXA250 256-  
Lead 17x17mm mBGA Pinout — Ballpad Number Order” on page 17.  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 1 of 7)  
Name  
Type  
Description  
Memory Controller Pins  
Memory address bus. This bus signals the address requested for memory  
accesses.  
MA[25:0]  
MD[15:0]  
OCZ  
ICOCZ Memory data bus. D[15:0] are used for 16-bit data mode.  
Memory data bus. D[31:16]: These data bits are used for the PXA250 applications  
ICOCZ processor 32-bit memories and are not pinned out for the PXA210 applications  
processor, 16-bit package option.  
MD[31:16]  
Memory output enable. This signal should be connected to the output enables of  
memory devices to control their data bus drivers.  
nOE  
OCZ  
Memory write enable. Connect this signal should to the write enables of memory  
devices.  
nWE  
OCZ  
SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS)  
pins for SDRAM. nSDCS0 is three-stateable nSDCS1-3 are not  
nSDCS[3:0]  
DQM[3:0]  
nSDRAS  
nSDCAS  
OCZ  
SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output  
mask enables (DQM) for SDRAM.  
OCZ  
SDRAM RAS. Connect this signal should to the row address strobe (RAS) pins for  
all banks of SDRAM.  
OCZ  
SDRAM CAS. Connect this signal should to the column address strobe (CAS)  
pins for all banks of SDRAM.  
OCZ  
SDRAM and/or Synchronous Static Memory clock enable.  
Connect SDCKE[0] to the CKE pins of SMROM and SDRAM-timing Synchronous  
SDCKE[0]  
SDCKE[1]  
OC  
OC  
Flash.  
The memory controller provides control register bits for deassertion of each  
SDCKE pin.  
SDRAM and/or Synchronous Static Memory clock enable.  
Connect SDCKE[1] to the SDRAM clock enable pins. It is de-asserted (held low)  
during sleep. SDCKE[1] is always deasserted upon reset.  
The memory controller provides control register bits for deassertion of each  
SDCKE pin.  
Datasheet  
9
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 2 of 7)  
Name  
Type  
Description  
SDRAM and/or Synchronous Static Memory clocks. Connect SDCLK[0] to the  
clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. SDCLK[1]  
and SDCLK[2] should be connected to the clock pins of SDRAM in bank pairs 0/1  
and 2/3, respectively. They are driven by either the internal memory controller  
clock, or the internal memory controller clock divided by 2. At reset, all clock pins  
are free running at the divide by 2 clock speed and may be turned off via free  
running control register bits in the memory controller. The memory controller also  
provides control register bits for clock division and deassertion of each SDCLK  
pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static  
memory bank 0 is configured for SMROM or SDRAM-timing Synchronous Flash.  
SDCLK[2:1] control register assertion bits are always deasserted upon reset.  
SDCLK[2:0]  
OCZ  
0 and 2 are not three-stateable, SDCLK1 is three-stateable  
Static chip selects. These signals are chip selects for static memory devices such  
as ROM and Flash. They are individually programmable in the memory  
configuration registers. nCS[5:3] may be used with variable data latency variable  
latency I/O devices.  
nCS[5]/  
ICOCZ  
GPIO[33]  
See Note [1]  
nCS[4]/  
ICOCZ Static chip select 4.  
ICOCZ Static chip select 3.  
ICOCZ Static chip select 2.  
ICOCZ Static chip select 1.  
GPIO[80]  
nCS[3]/  
GPIO[79]  
nCS[2]/  
GPIO[78]  
nCS[1]/  
GPIO[15]  
Static chip select 0. This is the boot memory chip select. nCS[0] is a dedicated  
pin.  
nCS[0]  
ICOCZ  
OCZ  
Read/Write for static interface. Intended for use as a steering signal for buffering  
logic  
RD/nWR  
RDY/  
Variable Latency I/O Ready pin (input)  
See Note [1]  
ICOCZ  
GPIO[18]  
PCMCIA/CF Control Pins  
PCMCIA Output Enable. This PCMCIA signal is an output and performs reads  
from memory and attribute space.  
nPOE/  
ICOCZ  
GPIO[48]  
See Note [1]  
PCMCIA Write Enable. This signal is an output and performs writes to memory  
and attribute space.  
nPWE/  
ICOCZ  
GPIO[49]  
See Note [1]  
PCMCIA I/O Write. This signal is an output and performs write transactions to the  
PCMCIA I/O space.  
nPIOW/  
ICOCZ  
GPIO[51]  
See Note [1]  
PCMCIA I/O Read. This signal is an output and performs read transactions from  
the PCMCIA I/O space.  
nPIOR/  
ICOCZ  
GPIO[50]  
See Note [1]  
PCMCIA Card Enable. These signals are outputs and select a PCMCIA card. Bit  
one enables the high byte lane and bit zero enables the low byte lane.  
nPCE[2:1]/  
ICOCZ  
GPIO[53, 52]  
See Note [1]  
10  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 3 of 7)  
Name  
Type  
Description  
I/O Select 16. This signal is an input and is an acknowledge from the PCMCIA  
card that the current address is a valid 16 bit wide I/O address.  
nIOIS16/  
ICOCZ  
GPIO[57]  
See Note [1]  
PCMCIA Wait. This signal is an input and is driven low by the PCMCIA card to  
extend the length of the transfers to/from applications processor.  
nPWAIT/  
GPIO[56]  
ICOCZ  
ICOCZ  
See Note [1]  
PCMCIA Socket Select. This signal is an output and is used by external steering  
logic to route control, address and data signals to one of the two PCMCIA  
sockets. When PSKTSEL is low, socket zero is selected. When PSKTSEL is high,  
socket one is selected. This signal has the same timing as an address.  
nPSKTSEL/  
GPIO[54]  
See Note [1]  
PCMCIA Register Select. This signal is an output and indicates that, on a memory  
transaction, the target address is attribute space. This signal has the same timing  
as address.  
nPREG/  
ICOCZ  
GPIO[55]  
See Note [1]  
LCD Controller Pins  
L_DD(15:0)/  
LCD Controller display data  
See Note [1]  
ICOCZ  
GPIO[73:58]  
L_FCLK/  
GPIO[74]  
LCD Frame clock  
See Note [1]  
ICOCZ  
ICOCZ  
ICOCZ  
ICOCZ  
L_LCLK/  
GPIO[75]  
LCD Line clock  
See Note [1]  
L_PCLK/  
GPIO[76]  
LCD pixel clock  
See Note [1]  
L_BIAS/  
AC Bias Drive  
See Note [1]  
GPIO[77]  
Full Function UART Pins  
FFRXD/  
ICOCZ  
Full Function UART Receive pin  
See Note [1]  
GPIO[34]  
FFTXD/  
ICOCZ  
Full Function UART Transmit pin  
See Note [1]  
GPIO[39]  
FFCTS/  
ICOCZ  
Full Function UART Clear-to-Send pin  
See Note [1]  
GPIO[35]  
FFDCD/  
ICOCZ  
Full Function UART Data-Carrier-Detect Pin  
See Note [1]  
GPIO[36]  
FFDSR/  
ICOCZ  
Full Function UART Data-Set-Ready Pin:  
See Note [1]  
GPIO[37]  
FFRI/  
Full Function UART Ring Indicator Pin  
See Note [1]  
ICOCZ  
GPIO[38]  
FFDTR/  
ICOCZ  
Full Function UART Data-Terminal-Ready pin  
See Note [1]  
GPIO[40]  
FFRTS/  
ICOCZ  
Full Function UART Ready-to-Send pin  
See Note [1]  
GPIO[41]  
Datasheet  
11  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 4 of 7)  
Name  
Type  
Description  
Bluetooth UART Pins  
BTRXD/  
Bluetooth UART Receive pin  
See Note [1]  
ICOCZ  
GPIO[42]  
BTTXD/  
Bluetooth UART Transmit pin  
See Note [1]  
ICOCZ  
ICOCZ  
ICOCZ  
GPIO[43]  
BTCTS/  
Bluetooth UART Clear-to-Send pin  
See Note [1]  
GPIO[44]  
BTRTS/  
Bluetooth UART Data-Terminal-Ready pin  
See Note [1]  
GPIO[45]  
MMC Controller Pins  
MMCMD  
MMDAT  
SSP Pins  
ICOCZ Multimedia Card Command pin (I/O)  
ICOCZ Multimedia Card Data Pin (I/O)  
SSPSCLK/  
GPIO[23]  
Synchronous Serial Port Clock (output)  
ICOCZ  
See Note [1]  
SSPSFRM/  
GPIO[24]  
Synchronous serial port Frame Signal (output)  
ICOCZ  
See Note [1]  
SSPTXD/  
GPIO[25]  
Synchronous serial port transmit (output)  
ICOCZ  
See Note [1]  
SSPRXD/  
GPIO[26]  
Synchronous serial port receive (input)  
ICOCZ  
See Note [1]  
SSPEXTCLK/  
GPIO[27]  
Synchronous Serial port external clock (input)  
ICOCZ  
See Note [1]  
USB Client Pins  
USB_P  
IAOA  
IAOA  
USB Client port positive Pin of differential pair.  
USB Client port negative Pin of differential pair.  
USB_N  
AC97 Controller Pins  
BITCLK/  
AC97 Audio Port bit clock (output)  
See Note [1]  
ICOCZ  
GPIO[28]  
SDATA_IN0/  
GPIO[29]  
AC97 Audio Port data in (input)  
See Note [1]  
ICOCZ  
ICOCZ  
ICOCZ  
ICOCZ  
OC  
SDATA_IN1/  
GPIO[32]  
AC97 Audio Port data in (input)  
See Note [1]  
SDATA_OUT/  
GPIO[30]  
AC97 Audio Port data out (output)  
See Note [1]  
SYNC/  
AC97 Audio Port sync signal (output)  
See Note [1]  
GPIO[31]  
AC97 Audio Port reset signal (output)  
This pin is a dedicated output.  
nACRESET  
12  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 5 of 7)  
Name  
Type  
Description  
Standard UART and ICP Pins  
IRRXD/  
IrDA Receive signal (input).  
ICOCZ  
GPIO[46]  
See Note [1]  
IrDA Transmit signal (output).  
IRTXD/  
ICOCZ This pin is the transmit pin for both the SIR and FIR functions.  
See Note [1]  
GPIO[47]  
I2C Controller Pins  
I2C clock (Bidirectional)  
This signal is bidirectional. When it is driving, it functions as an open collector  
ICOCZ  
SCL  
device and requires a pull up resistor. As an input, it expects standard CMOS  
levels.  
I2C Data signal (bidirectional).  
SDA  
ICOCZ  
Bidirectional signal. When it is driving, it functions as an open collector device and  
requires a pull up resistor. As an input, it expects standard CMOS levels.  
PWM Pins  
Pulse Width Modulation channels 0 and 1 (outputs)  
PWM[1:0]/  
ICOCZ See Note [1]  
GPIO[17,16]  
Dedicated GPIO Pins  
General Purpose I/O. These two pins are contained in both the PXA250 and  
PXA210 Applications Processors. They are preconfigured at a hard reset  
(nRESET) as wakeup sources for both rising and falling edge detects.  
GPIO[1:0]  
ICOCZ  
These GPIOs do not have alternate functions and are intended to be used as the  
main external sleep wakeup stimulus.  
General Purpose I/O: These pins are not included in the PXA210 Applications  
Processor.  
GPIO[14:2])  
ICOCZ  
See Note [1]  
Crystal Pins  
PXTAL  
IA  
OA  
IA  
Input connection for 3.6864 Mhz crystal  
Output connection for 3.6846 Mhz crystal  
Input connection for external oscillator  
PEXTAL  
TXTAL  
Input connection for 32.768 Khz crystal  
Output connection for 32.768 Khz crystal  
Input connection for external oscillator  
TEXTAL  
OA  
Datasheet  
13  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 6 of 7)  
Name  
Type  
Description  
Miscellaneous Pins  
Boot programming select pins. These pins are sampled to indicate the type of  
boot device present per the following table;  
BOOT_SEL[2:0]  
Description  
000  
001  
010  
011  
100  
101  
110  
111  
Asynchronous 32-bit ROM  
Asynchronous 16-bit ROM  
Reserved  
BOOT_SEL  
[2:0]  
IC  
Reserved  
One 32-bit SMROM  
One 16 bit SMROM  
Two 16 bit SMROMs (32 bit bus)  
Reserved  
Power Enable. Active high output.  
PWR_EN enables the external power supply. Negating it signals the power supply  
that the system is going into sleep mode and that the VDD power supply should  
be removed.  
PWR_EN  
OCZ  
IC  
Battery Fault. Active low input.  
Signals the applications processor that the main power source is going away  
(battery is low or is removed from the system.) The assertion of nBATT_FAULT  
causes the applications processor to enter Sleep Mode. The device will not  
recognize a wakeup event while this signal is asserted.  
nBATT_FAUL T  
VDD Fault. Active low input.  
Signals the applications processor that the main power source is going out of  
regulation (i.e. shorted card is inserted). nVDD_FAULT causes the device to enter  
Sleep Mode. nVDD_FAULT is ignored after a wakeup event until the power supply  
timer completes (approximately 10 ms).  
nVDD_FAULT  
IC  
IC  
Hard reset. Active low input.  
nRESET is a level sensitive input which starts the processor from a known  
address. A LOW level causes the current instruction to terminate abnormally, and  
all on-chip states to be reset. When nRESET is driven HIGH, the processor re-  
starts from address 0. nRESET must remain LOW until the power supply is stable  
and the internal 3.6864 MHz oscillator has come up to speed. While nRESET is  
LOW the processor performs idle cycles.  
nRESET  
Reset Out. Active low output.  
This signal is asserted when nRESET is asserted and deasserts after nRESET is  
negated but before the first instruction fetch. nRESET_OUT is also asserted for  
“soft” reset events (sleep, watchdog reset, GPIO reset)  
nRESET_OUT  
OC  
IC  
JTAG Pins  
nTRST  
JTAG Test interface reset. If JTAG is used, then you must drive nTRST from low  
to high either before or at the same time as nRESET  
If JTAG is not used, then tie nTRST to either nRESET or low.  
TDI  
IC  
OCZ  
IC  
JTAG test interface data input. Note this pin has an internal pullup resistor.  
JTAG test interface data output. Note this pin does NOT have an internal pullup  
resistor.  
TDO  
TMS  
TCK  
TEST  
JTAG test interface mode select. Note this pin has an internal pullup resistor.  
JTAG test interface reference Clock. TCK is the reference clock for all transfers  
on the JTAG test interface. Note this pin has an internal pulldown resistor.  
IC  
IC  
Test Mode. You must ground this pin. This pin is for manufacturing purposes only.  
14  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 7 of 7)  
Name  
Type  
Description  
Test Clock. This pin should be used for test purposes only. An end user should  
ground this pin.  
TESTCLK  
IC  
Power and Ground Pins  
Positive supply for the applications processor internal Logic. Connect this supply  
to the low voltage (.85 - 1.3v) supply on the PCB.  
VCC  
VSS  
SUP  
SUP  
Ground supply for the applications processor internal logic. Connect these pins to  
the common ground plane on the PCB.  
Positive supply for the PLLs and Oscillators. It is recommended that you connect  
this pin to the common low voltage supply.  
PLL_VCC  
PLL_VSS  
VCCQ  
SUP  
SUP  
SUP  
Ground signal for PLLs.  
Positive supply for all CMOS I/O, except memory bus and PCMCIA pins. Connect  
these pins to the common 3.3 volt supply on the PCB.  
Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Connect  
these pins to the common ground plane on the PCB.  
VSSQ  
VCCN  
VSSN  
SUP  
SUP  
SUP  
Positive supply for memory bus and PCMCIA pins. Connect these pins to the  
common 3.3 volt supply on the PCB.  
Ground supply for memory bus and PCMCIA pins. Connect these pins to the  
common ground plane on the PCB.  
Backup battery connection. Connect this pin to the backup battery supply. If a  
backup battery is not required, then this pin may be connected to the common  
3.3 volt supply on the PCB.  
BATT_VCC  
SUP  
NOTE:  
1. GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these  
pins are disabled to prevent current drain.  
Datasheet  
15  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Figure 2. PXA250 Applications Processor  
16  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 1 of 3)  
Ball #  
Signal  
Ball #  
Signal  
Ball #  
Signal  
A1  
A2  
VCCN  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
D1  
VCCQ  
VSSQ  
USB_P  
VCCQ  
VSSQ  
F3  
F4  
nSDCAS  
VCCN  
L_DD[13]/GPIO[71]  
L_DD[12]/GPIO[70]  
L_DD[11]/GPIO[69]  
L_DD[9]/GPIO[67]  
L_DD[7]/GPIO[65]  
GPIO[11]  
A3  
F5  
SDCLK[1]  
VSSQ  
A4  
F6  
A5  
F7  
GPIO[10]  
FRTS/GPIO[41]  
SSPSCLK/GPIO[23]  
FFDTR/GPIO[40]  
VCC  
A6  
IRTXD/GPIO[47]  
VSS  
F8  
A7  
F9  
A8  
L_BIAS/GPIO[77]  
SSPRXD/GPIO[26]  
SDATA_OUT/GPIO[30]  
SDA  
SDCLK[2]  
F10  
F11  
F12  
F13  
F14  
F15  
F16  
G1  
A9  
D2  
SDCLK[0]  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
B1  
D3  
RDnWR  
GPIO[9]  
BOOT_SEL[2]  
GPIO[8]  
VSSQ  
D4  
VCCN  
FFDCD/GPIO[36]  
FFRXD/GPIO[34]  
FFCTS/GPIO[35]  
BTCTS/GPIO[44]  
SDATA_IN1/GPIO[32]  
DQM[1]  
D5  
L_DD[10]/GPIO[68]  
L_DD[5]/GPIO[63]  
L_DD[1]/GPIO[59]  
L_LCLK/GPIO[75]  
SSPTXD/GPIO[25]  
nACRESET  
D6  
D7  
VSSQ  
D8  
MA[0]  
D9  
G2  
VSSN  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
E1  
G3  
nSDCS[2]  
nWE  
B2  
DQM[2]  
SCL  
G4  
B3  
L_DD[15]/GPIO[73]  
GPIO[14]  
PWM[1]/GPIO[17]  
BTTXD/GPIO[43]  
MMCMD  
G5  
nOE  
B4  
G6  
nSDCS[1]  
VCC  
B5  
GPIO[13]  
G7  
B6  
GPIO[12]  
VCCQ  
G8  
VSSQ  
B7  
L_DD[3]/GPIO[61]  
L_PCLK/GPIO[76]  
SSPEXTCLK/GPIO[27]  
FFRI/GPIO[38]  
FFDSR/GPIO[37]  
USB_N  
VSSQ  
G9  
VCC  
B8  
nSDRAS  
G10  
G11  
G12  
G13  
G14  
G15  
G16  
H1  
VSSQ  
B9  
E2  
VSSN  
TESTCLK  
TEST  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
C1  
E3  
SDCKE[1]  
E4  
SDCKE[0]  
BOOT_SEL[1]  
VCCQ  
E5  
L_DD[6]/GPIO[64]  
L_DD[4]/GPIO[62]  
L_DD[[0]/GPIO[58]  
L_FCLK/GPIO[74]  
SSPSFRM/GPIO[24]  
SDATA_IN0/GPIO[29]  
SYNC/GPIO[31]  
PWM[0]/GPIO[16]  
FFTXD/GPIO[39]  
VCCQ  
BTRXD/GPIO[42]  
BTRTS/GPIO[45]  
IRRXD/GPIO[46]  
MMDAT  
E6  
GPIO[7]  
BOOT_SEL[0]  
MA[2]  
E7  
E8  
E9  
H2  
MA[1]  
RDY/GPIO[18]  
VSSN  
E10  
E11  
E12  
E13  
E14  
H3  
MD[16]  
C2  
H4  
VCCN  
C3  
L_DD[14]/GPIO[72]  
VSSQ  
H5  
MD[17]  
C4  
H6  
MA[3]  
C5  
L_DD[8]/GPIO[66]  
H7  
VSSQ  
Datasheet  
17  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 2 of 3)  
Ball #  
Signal  
Ball #  
Signal  
Ball #  
Signal  
C6  
C7  
VCCQ  
E15  
E16  
F1  
VSSQ  
VSSQ  
H8  
H9  
VSS  
L_DD[2]/GPIO[60]  
VSSQ  
VSS  
C8  
nSDCS[0]  
nSDCS[3]  
VCC  
H10  
H11  
P6  
VCC  
C9  
BITCLK/GPIO[28]  
TCK  
F2  
nTRST  
MD[24]  
MD26]  
MD[27]  
H12  
H13  
H14  
H15  
H16  
J1  
L9  
TMS  
L10  
L11  
L12  
L13  
L14  
L15  
L16  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
GPIO[0]  
PWR_EN  
GPIO[1]  
GPIO[2]  
VSSQ  
P7  
GPIO[6]  
TDI  
P8  
P9  
nCS[2]/GPIO[78]  
MD[29]  
TDO  
P10  
P11  
P12  
P13  
P14  
P15  
P16  
R1  
MA[7]  
MD[12]  
J2  
VSSN  
TEXTAL  
TXTAL  
MD[31]  
J3  
MA[6]  
nPOE/GPIO[48]  
nPCE[1]/GPIO[52]  
VSSN  
J4  
MD[18]  
MA[5]  
MA[14]  
MD[21]  
MA[15]  
VCCN  
J5  
J6  
MA[4]  
nPSKTSEL/GPIO[54]  
MA[18]  
J7  
VCC  
J8  
VSS  
MD[1]  
R2  
VSSN  
J9  
VSS  
MD[6]  
R3  
MA[20]  
J10  
J11  
J12  
J13  
J14  
J15  
J16  
K1  
VSSQ  
MD[7]  
R4  
VSSN  
GPIO[5]  
GPIO[4]  
nRESET  
VSSQ  
M8  
DQM[0]  
MD[8]  
R5  
MA[22]  
M9  
M10  
M11  
M12  
M13  
M14  
M15  
M16  
N1  
R6  
VSSN  
MD[15]  
BATT_VCC  
GPIO[22]  
nPREG/GPIO[55]  
VCCN  
R7  
MD[25]  
R8  
VSSN  
PLL_VCC  
PLL_VSS  
MA[8]  
R9  
MD[10]  
R10  
R11  
R12  
R13  
R14  
R15  
R16  
T1  
VSSN  
MD[30]  
K2  
MA[9]  
VSSN  
VSSN  
K3  
MD[19]  
VCCN  
nIOIS16/GPIO[57]  
MD[22]  
VSSN  
nCS[4]/GPIO[80]  
VSSN  
K4  
K5  
MA[10]  
MA[11]  
VSSQ  
N2  
nPIOW/GPIO[51]  
nPCE[2]/GPIO[53]  
VSS  
K6  
N3  
MA[16]  
K7  
N4  
MD[0]  
K8  
VCC  
N5  
VCCN  
T2  
VCCN  
K9  
VSSQ  
N6  
MD[4]  
T3  
MD[23]  
K10  
K11  
K12  
K13  
VCC  
N7  
VCCN  
T4  
MA[21]  
nRESET_OUT  
nBATT_FAULT  
nVDD_FAULT  
N8  
nCS[0]  
T5  
MA[24]  
N9  
VCCN  
T6  
MD[3]  
N10  
MD[13]  
T7  
MD[5]  
18  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 3 of 3)  
Ball #  
Signal  
Ball #  
Signal  
Ball #  
Signal  
K14  
K15  
K16  
L1  
GPIO[3]  
PXTAL  
PEXTAL  
MA[12]  
VSSN  
N11  
N12  
N13  
N14  
N15  
N16  
P1  
VCCN  
T8  
T9  
nCS[1]/GPIO[15]  
nCS[3]/GPIO[79]  
MD[9]  
DREQ[0]/GPIO[20]  
VCCN  
T10  
T11  
T12  
T13  
T14  
T15  
T16  
DREQ[1]/GPIO[19]  
GPIO[21]  
MD[11]  
L2  
MD[14]  
L3  
MA[13]  
MD[20]  
MD[2]  
nPWAIT/GPIO[56]  
MA[17]  
nCS[5]/GPIO[33]  
nPWE/GPIO[49]  
nPIOR/GPIO[50]  
VCCN  
L4  
L5  
P2  
MA[19]  
L6  
VCC  
P3  
VCCN  
L7  
DQM[3]  
MD[28]  
P4  
MA[25]  
L8  
P5  
MA[23]  
3.1.1.2  
PXA210 Signal Pin Descriptions  
Signal definitions for the PXA210 applications processor are described in Table 4. The physical  
characteristics of the PXA210 applications processor are shown in Figure 3, “PXA210  
Applications Processor” on page 26. The pinout for the PXA210 applications processor is  
described in Table 5, “PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order” on  
page 27.  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 1 of 7)  
Pin Name  
Type  
Signal Descriptions  
Memory Controller Pins  
Memory address bus. (output) Signals the address requested for memory  
accesses.  
MA[25:0]  
MD[15:0]  
nOE  
OCZ  
ICOCZ Memory data bus. (input/output) Lower 16 bits of the data bus.  
Memory output enable. (output) Connect to the output enables of memory  
devices to control data bus drivers.  
OCZ  
nWE  
OCZ  
OCZ  
Memory write enable. (output) Connect to the write enables of memory devices.  
SDRAM CS for banks 1 and 0. (output) Connect to the chip select (CS) pins for  
SDRAM. For the PXA210 applications processor nSDCS0 can be Hi-Z, nSDCS1  
cannot.  
nSDCS[1:0]  
SDRAM DQM for data bytes 1 and 0. (output) Connect to the data output mask  
enables (DQM) for SDRAM.  
DQM[1:0]  
nSDRAS  
nSDCAS  
OCZ  
OCZ  
OCZ  
SDRAM RAS. (output) Connect to the row address strobe (RAS) pins for all banks  
of SDRAM.  
SDRAM CAS. (output) Connect to the column address strobe (CAS) pins for all  
banks of SDRAM.  
SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to  
the CKE pins of SMROM and SDRAM-timing Synchronous Flash. The memory  
controller provides control register bits for deassertion.  
SDCKE[0]  
OC  
Datasheet  
19  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 2 of 7)  
Pin Name  
Type  
Signal Descriptions  
SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to  
the clock enable pins of SDRAM. It is deasserted during sleep. SDCKE[1] is  
always deasserted upon reset. The memory controller provides control register bits  
for deassertion.  
SDCKE[1]  
SDCLK[0]  
OC  
OC  
SDRAM and/or Synchronous Static Memory clocks. (output) Connect to the  
clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. Connect  
SDCLK[1] to the clock pins of SDRAM in bank pairs 0/1. It is driven by either the  
internal memory controller clock or the internal memory controller clock divided by  
2. At reset, all clock pins are free running at the divide by 2 clock speed and may  
be turned off via free running control register bits in the memory controller. The  
memory controller also provides control register bits for clock division and  
deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to  
on if the boot-time static memory bank 0 is configured for SMROM or SDRAM-  
timing Synchronous Flash. SDCLK[1] control register assertion bit is always  
deasserted on reset. SDCLK[1] can be Hi-Z, SDCLK[0] cannot.  
SDCLK[1]  
OCZ  
nCS[5]/  
ICOCZ  
ICOCZ  
GPIO[33]  
nCS[4]/  
GPIO[80]  
Static chip selects. (output) Chip selects to static memory devices such as ROM  
ICOCZ and Flash. Individually programmable in the memory configuration registers.  
nCS[5:3] can be used with variable latency I/O devices.  
nCS[3]/  
GPIO[79]  
nCS[2]/  
ICOCZ  
ICOCZ  
GPIO[78]  
nCS[1]/  
GPIO[15]  
nPWE/  
VLIO write enable (output). Used as the write enable signal for Variable Latency  
ICOCZ  
I/O.  
GPIO[49]  
Static chip select 0. (output) Chip select for the boot memory. nCS[0] is a  
dedicated pin.  
nCS[0]  
ICOCZ  
Read/Write for static interface. (output) Signals that the current transaction is a  
read or write.  
RD/nWR  
OCZ  
RDY/  
Variable Latency I/O Ready pin. (input) Notifies the memory controller when an  
external bus device is ready to transfer data.  
ICOCZ  
GPIO[18]  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
L_DD[8]/  
GPIO[66]  
the external LCD panel.  
ICOCZ  
Memory Controller alternate bus master request. (input) Allows an external  
device to request the system bus from the Memory Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
L_DD[15]/  
GPIO[73]  
the external LCD panel.  
ICOCZ  
Memory Controller grant. (output) Notifies an external device that it has been  
granted the system bus.  
LCD Controller Pins  
L_DD(7:0)/  
LCD display data. (outputs) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
ICOCZ  
GPIO[65:58]  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
L_DD[8]/  
GPIO[66]  
the external LCD panel.  
ICOCZ  
Memory Controller alternate bus master request. (input) Allows an external  
device to request the system bus from the Memory Controller.  
20  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 3 of 7)  
Pin Name  
Type  
Signal Descriptions  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[9]/  
ICOCZ  
GPIO[67]  
MMC chip select 0. (output) Chip select 0 for the MMC Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[10]/  
GPIO[68]  
ICOCZ  
ICOCZ  
ICOCZ  
ICOCZ  
ICOCZ  
MMC chip select 1. (output) Chip select 1 for the MMC Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[11]/  
GPIO[69]  
MMC clock. (output) Clock for the MMC Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[12]/  
GPIO[70]  
RTC clock. (output) Real time clock 1 Hz tick.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[13]/  
GPIO[71]  
3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[14]/  
GPIO[72]  
32 kHz clock. (output) Output from the 32 kHz oscillator.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
L_DD[15]/  
GPIO[73]  
the external LCD panel.  
ICOCZ  
Memory Controller grant. (output) Notifies an external device it has been granted  
the system bus.  
L_FCLK/  
GPIO[74]  
LCD frame clock. (output) Indicates the start of a new frame. Also referred to as  
Vsync.  
ICOCZ  
ICOCZ  
L_LCLK/  
GPIO[75]  
LCD line clock. (output) Indicates the start of a new line. Also referred to as  
Hsync.  
L_PCLK/  
GPIO[76]  
ICOCZ LCD pixel clock. (output) Clocks valid pixel data into the LCD’s line shift buffer.  
L_BIAS/  
AC bias drive. (output) Notifies the panel to change the polarity for some passive  
ICOCZ  
LCD panel. For TFT panels, this signal indicates valid pixel data.  
GPIO[77]  
Full Function UART Pins  
FFRXD/  
ICOCZ  
Full Function UART Receive. (input)  
GPIO[34]  
MMC chip select 0. (output) Chip select 0 for the MMC Controller.  
FFTXD/  
ICOCZ  
Full Function UART Transmit. (output)  
GPIO[39]  
MMC chip select 1. (output) Chip select 1 for the MMC Controller.  
Bluetooth UART Pins  
BTRXD/  
ICOCZ Bluetooth UART Receive. (input)  
GPIO[42]  
BTTXD/  
ICOCZ Bluetooth UART Transmit. (output)  
ICOCZ Bluetooth UART Clear-to-Send. (input)  
ICOCZ Bluetooth UART Data-Terminal-Ready. (output)  
GPIO[43]  
BTCTS/  
GPIO[44]  
BTRTS/  
GPIO[45]  
Datasheet  
21  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 4 of 7)  
Pin Name  
Type  
Signal Descriptions  
Standard UART and ICP Pins  
IRRXD/  
IrDA receive signal. (input) Receive pin for the FIR function.  
Standard UART receive. (input)  
ICOCZ  
ICOCZ  
GPIO[46]  
IrDA transmit signal. (output) Transmit pin for the Standard UART, SIR and FIR  
functions.  
IRTXD/  
GPIO[47]  
Standard UART transmit. (output)  
MMC Controller Pins  
MMCMD  
MMDAT  
GPIO[53]  
ICOCZ Multimedia Card Command. (bidirectional)  
ICOCZ Multimedia Card Data. (bidirectional)  
ICOCZ MMC clock. (output) Clock signal for the MMC Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
L_DD[9]/  
GPIO[67]  
the external LCD panel.  
ICOCZ  
ICOCZ  
ICOCZ  
MMC chip select 0. (output) Chip select 0 for the MMC Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[10]/  
GPIO[68]  
MMC chip select 1. (output) Chip select 1 for the MMC Controller.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[11]/  
GPIO[69]  
MMC clock. (output) Clock for the MMC Controller.  
FFRXD/  
Full Function UART Receive. (input)  
ICOCZ  
ICOCZ  
GPIO[34]  
MMC chip select 0. (output) Chip select 0 for the MMC Controller.  
FFTXD/  
Full Function UART Transmit. (output)  
GPIO[39]  
MMC chip select 1. (output) Chip select 1 for the MMC Controller.  
SSP Pins  
SSPSCLK/  
GPIO[23]  
ICOCZ Synchronous Serial Port Clock. (output)  
ICOCZ Synchronous Serial Port Frame. (output)  
ICOCZ Synchronous Serial Port Transmit. (output)  
ICOCZ Synchronous Serial Port Receive. (input)  
ICOCZ Synchronous Serial Port External Clock. (input)  
SSPSFRM/  
GPIO[24]  
SSPTXD/  
GPIO[25]  
SSPRXD/  
GPIO[26]  
SSPEXTCLK/  
GPIO[27]  
USB Client Pins  
USB_P  
IAOAZ USB Client Positive. (bidirectional)  
USB_N  
IAOAZ USB Client Negative pin. (bidirectional)  
22  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 5 of 7)  
Pin Name  
Type  
Signal Descriptions  
AC97 Controller and I2S Controller Pins  
AC97 Audio Port bit clock. (input) AC97 clock is generated by Codec 0 and fed  
into the PXA210 applications processor and Codec 1.  
AC97 Audio Port bit clock. (output) AC97 clock is generated by the PXA210  
BITCLK/  
applications processor.  
I2S bit clock. (input) I2S clock is generated externally and fed into PXA210  
ICOCZ  
GPIO[28]  
applications processor.  
I2S bit clock. (output) I2S clock is generated by the PXA210 applications  
processor.  
SDATA_IN0/  
GPIO[29]  
AC97 Audio Port data in. (input) Input line for Codec 0.  
I2S data in. (input) Input line for the I2S Controller.  
ICOCZ  
ICOCZ  
ICOCZ  
SDATA_IN1/  
GPIO[32]  
AC97 Audio Port data in. (input) Input line for Codec 1.  
I2S system clock. (output) System clock from I2S Controller.  
SDATA_OUT/  
GPIO[30]  
AC97 Audio Port data out. (output) Output from the PXA210 to Codecs 0 and 1.  
I2S data out. (output) Output line for the I2S Controller.  
AC97 Audio Port sync signal. (output) Frame sync signal for the AC97  
Controller.  
I2S sync. (output) Frame sync signal for the I2S Controller.  
SYNC/  
ICOCZ  
OC  
GPIO[31]  
nACRESET  
AC97 Audio Port reset signal. (output)  
I2C Controller Pins  
SCL  
ICOCZ I2C clock. (bidirectional)  
ICOCZ I2C data. (bidirectional).  
SDA  
PWM Pins  
PWM[1:0]/  
ICOCZ Pulse Width Modulation channels 0 and 1. (outputs)  
GPIO[17:16]  
GPIO Pins  
GPIO[1:0]  
General Purpose I/O. Wakeup sources on both rising and falling edges on  
nRESET.  
ICOCZ  
General Purpose I/O. Wakeup sources on both rising and falling edges on  
nRESET.  
GPIO[57:48]  
ICOCZ  
Crystal and Clock Pins  
PXTAL  
PEXTAL  
TXTAL  
IA  
3.6864 Mhz crystal input.  
3.6864 Mhz crystal output.  
32.768 khz crystal input.  
32.768 khz crystal output.  
OA  
IA  
TEXTAL  
OA  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[12]/  
GPIO[70]  
ICOCZ  
ICOCZ  
ICOCZ  
RTC clock. (output) Real time clock 1 Hz tick.  
LCD display data. (output) Transfers the pixel information from the LCD Controller  
to the external LCD panel.  
L_DD[13]/  
GPIO[71]  
3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.  
LCD display data. (output) Transfers pixel information from the LCD Controller to  
the external LCD panel.  
L_DD[14]/  
GPIO[72]  
32 kHz clock. (output) Output from the 32 kHz oscillator.  
Datasheet  
23  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 6 of 7)  
Pin Name  
Type  
Signal Descriptions  
Miscellaneous Pins  
BOOT_SEL  
IC  
Boot select pins. (input) Indicates type of boot device.  
[2:0]  
Power Enable for the power supply. (output) When negated, it signals the power  
supply to remove power because the system is entering Sleep Mode.  
PWR_EN  
OC  
Main Battery Fault. (input) Signals that main battery is low or removed. Assertion  
causes the PXA210 applications processor to enter Sleep Mode or force an  
Imprecise Data Exception, which cannot be masked. The PXA210 applications  
processor will not recognize a wakeup event while this signal is asserted.  
nBATT_FAULT IC  
VDD Fault. (input) Signals that the main power source is going out of regulation.  
nVDD_FAULT causes the PXA210 applications processor to enter Sleep Mode or  
force an Imprecise Data Exception, which cannot be masked. nVDD_FAULT is  
ignored after a wakeup event until the power supply timer completes  
(approximately 10 ms).  
nVDD_FAULT IC  
Hard reset. (input) Level sensitive input used to start the processor from a known  
address. Assertion causes the current instruction to terminate abnormally and  
causes a reset. When nRESET is driven high, the processor starts execution from  
address 0. nRESET must remain low until the power supply is stable and the  
internal 3.6864 MHz oscillator has stabilized.  
nRESET  
IC  
Reset Out. (output) Asserted when nRESET is asserted and deasserts after  
nRESET is deasserted but before the first instruction fetch. nRESET_OUT is also  
asserted for “soft” reset events: sleep, watchdog reset, or GPIO reset.  
nRESET_OUT OC  
JTAG and Test Pins  
JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used,  
drive nTRST from low to high either before or at the same time as nRESET. If  
JTAG is not used, nTRST must be either tied to nRESET or tied low. Intel  
recommends that a JTAG/Debug port be added to all systems for debug and  
download. See Chapter 9 in the “Intel® PXA250 and PXA210 Applications  
Processor Design Guide” for details.  
nTRST  
IC  
JTAG test data input. (input) Data from the JTAG controller is sent to the PXA210  
using this pin. This pin has an internal pull-up resistor.  
TDI  
IC  
JTAG test data output. (output) Data from the PXA210 applications processor is  
returned to the JTAG controller using this pin.  
TDO  
TMS  
OCZ  
IC  
JTAG test mode select. (input) Selects the test mode required from the JTAG  
controller. This pin has an internal pull-up resistor.  
TCK  
IC  
IC  
IC  
JTAG test clock. (input) Clock for all transfers on the JTAG test interface.  
Test Mode. (input) Reserved. Must be grounded.  
TEST  
TESTCLK  
Test Clock. (input) Reserved. Must be grounded.  
Power and Ground Pins  
Positive supply for internal logic. Must be connected to the low voltage (.85 -  
1.3v) supply on the PCB.  
VCC  
VSS  
SUP  
SUP  
Ground supply for internal logic. Must be connected to the common ground  
plane on the PCB.  
Positive supply for PLLs and oscillators. Must be connected to a separate quiet  
supply plane on the PCB but may be connected to the common low voltage supply.  
PLL_VCC  
PLL_VSS  
VCCQ  
SUP  
SUP  
SUP  
Ground signal for PLLs.  
Positive supply for all CMOS I/O except memory bus. Must be connected to the  
common 3.3 V supply on the PCB.  
24  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 7 of 7)  
Pin Name  
VSSQ  
Type  
SUP  
Signal Descriptions  
Ground supply for all CMOS I/O except memory bus. Must be connected to the  
common ground plane on the PCB.  
Positive supply for memory bus. Must be connected to the common 3.3 V or  
2.5 V supply on the PCB.  
VCCN  
VSSN  
SUP  
SUP  
Ground supply for memory bus and some GPIO pins. Must be connected to  
the common ground plane on the PCB.  
Backup battery supply. Connect to the backup battery supply. If a backup battery  
is not required then this pin may be connected to the common 3.3 V supply on the  
PCB.  
BATT_VCC  
SUP  
Datasheet  
25  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Figure 3. PXA210 Applications Processor  
26  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 1 of 3)  
Ball #  
Signal  
Ball #  
Signal  
Ball #  
Signal  
A1  
A2  
DQM[1]  
C12  
C13  
C14  
C15  
D1  
BTTXD/GPIO[43]  
VSSQ  
F8  
F9  
SSPRXD/GPIO[26]  
VCC  
L_DD[14]/GPIO[72]  
L_DD[10]/GPIO[68]  
VSSQ  
A3  
VSS  
F10  
F11  
F12  
F13  
F14  
F15  
G1  
FFTXD/GPIO[39]  
VCC  
A4  
VCCQ  
A5  
L_DD[6]/GPIO[64]  
L_DD[2]/GPIO[60]  
L_LCLK/GPIO[75]  
SSPSCLK/GPIO[23]  
SSPEXTCLK/GPIO[27]  
nACRESET  
VCC  
VSSQ  
TESTCLK  
BOOT_SEL[0]  
TEST  
A6  
D2  
VSSQ  
A7  
D3  
SDCLK[1]  
A8  
D4  
L_DD[15]/GPIO[73]  
VCC  
A9  
D5  
MA[0]  
A10  
A11  
A12  
A13  
A14  
A15  
B1  
D6  
L_DD[5]/GPIO[63]  
L_DD[0]/GPIO[58]  
SSPSFRM/GPIO[24]  
SDATA_OUT/GPIO[30]  
SCL  
G2  
nOE  
PWM[1]/GPIO[17]  
VSSQ  
D7  
G3  
nWE  
D8  
G4  
VCCN  
VSSN  
FFRXD/GPIO[34]  
BTCTS/GPIO[44]  
IRRXD/GPIO[46]  
RDY/GPIO[18]  
VSSN  
D9  
G5  
D10  
D11  
D12  
D13  
D14  
D15  
E1  
G6  
RDnWR  
VSS  
SDATA_IN1/GPIO[32]  
BOOT_SEL[1]  
VSSQ  
G7  
G8  
VSS  
B2  
G9  
VSS  
B3  
L_DD[13]/GPIO[71]  
L_DD[9]/GPIO[67]  
VSSQ  
VSSQ  
G10  
G11  
G12  
G13  
G14  
G15  
H1  
BTRXD/GPIO[42]  
nTRST  
TDI  
B4  
VSSQ  
B5  
nSDCAS  
B6  
L_DD[3]/GPIO[61]  
L_PCLK/GPIO[76]  
VSSQ  
E2  
VCCN  
TCK  
B7  
E3  
VSSN  
TMS  
B8  
E4  
SDCLK[0]  
TDO  
B9  
BITCLK/GPIO[28]  
SDA  
E5  
L_DD[11]/GPIO[69]  
L_DD[7]/GPIO[65]  
L_DD[1]/GPIO[59]  
SSPTXD/GPIO[25]  
SYNC/GPIO[31]  
VCCQ  
VCCN  
VSSN  
B10  
B11  
B12  
B13  
B14  
B15  
C1  
E6  
H2  
VSSQ  
E7  
H3  
MA[2]  
USB_N  
E8  
H4  
MA[1]  
BTRTS/GPIO[45]  
IRTXD/GPIO[47]  
MMDAT  
E9  
H5  
VCC  
E10  
E11  
E12  
E13  
E14  
E15  
F1  
H6  
VSSQ  
MMCMD  
H7  
VSS  
SDCKE[1]  
VCCQ  
H8  
VSS  
C2  
SDCKE[0]  
VSSQ  
H9  
VSS  
C3  
VCCN  
VSSQ  
H10  
H11  
H12  
H13  
H14  
VSSQ  
VCC  
C4  
L_DD[12]/GPIO[70]  
VCCQ  
BOOT_SEL[2]  
VSSN  
C5  
VSSQ  
VCC  
C6  
L_DD[4]/GPIO[62]  
L_BIAS/GPIO[77]  
F2  
NSDCS[0]  
NSDRAS  
C7  
F3  
PLL_VCC  
Datasheet  
27  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 2 of 3)  
Ball #  
Signal  
Ball #  
Signal  
NSDCS[1]  
Ball #  
Signal  
PLL_VSS  
C8  
C9  
C10  
C11  
J4  
VCCQ  
F4  
F5  
H15  
J1  
SDATA_IN0/GPIO[29]  
PWM[0]/GPIO[16]  
USB_P  
MA[4]  
VCC  
MA[5]  
F6  
L_DD[8]/GPIO[66]  
L_FCLK/GPIO[74]  
GPIO[0]  
MA[14]  
J2  
MA[6]  
F7  
J3  
VSSN  
L15  
M1  
M2  
M3  
M4  
M5  
M6  
M7  
M8  
M9  
M10  
M11  
M12  
M13  
M14  
M15  
N1  
P11  
P12  
P13  
P14  
P15  
R1  
VCCN  
J5  
MA[3]  
MD[15]  
J6  
VSSQ  
MA[15]  
VCCN  
J7  
VSS  
VCCN  
GPIO[50]  
VSSQ  
J8  
VSS  
MA[16]  
J9  
VSS  
VCCN  
MA[19]  
J10  
J11  
J12  
J13  
J14  
J15  
K1  
VSSQ  
VSSN  
R2  
MA[20]  
nRESET  
nRESET_OUT  
PWR_EN  
nVDD_FAULT  
nBATT_FAULT  
MA[8]  
MD[3]  
R3  
MA[21]  
MD[7]  
R4  
MA[25]  
nCS[1]/GPIO[15]  
MD[10]  
R5  
MD[1]  
R6  
VCCN  
MD[13]  
R7  
MD[5]  
GPIO[48]  
GPIO[52]  
VSSN  
R8  
nCS[0]  
K2  
MA[9]  
R9  
nCS[3]/GPIO[79]  
MD[9]  
K3  
MA[10]  
MA[7]  
R10  
R11  
R12  
R13  
R14  
R15  
K4  
GPIO[56]  
VSSN  
VSSN  
K5  
VCCN  
MD[14]  
K6  
VCC  
N2  
MA[18]  
nCS[4]/GPIO[80]  
nPWE/GPIO[49]  
GPIO[51]  
K7  
VSSQ  
N3  
VSS  
K8  
VCC  
N4  
MA[22]  
K9  
VSSQ  
N5  
MA[24]  
K10  
K11  
K12  
K13  
K14  
K15  
L1  
VCC  
N6  
VCCN  
GPIO[1]  
TEXTAL  
TXTAL  
N7  
VCC  
N8  
VSSN  
N9  
DQM[0]  
VCCN  
PEXTAL  
PXTAL  
N10  
N11  
N12  
N13  
N14  
N15  
P1  
MD[12]  
VSSN  
VSSN  
L2  
VCCN  
nCS[5]/GPIO[33]  
GPIO[53]  
VCCN  
L3  
MA[12]  
MA[13]  
MA[11]  
L4  
L5  
MA[17]  
L6  
VSSQ  
P2  
VSSN  
L7  
MD[2]  
P3  
VCCN  
28  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 3 of 3)  
Ball #  
Signal  
Ball #  
Signal  
Ball #  
Signal  
L8  
MD[6]  
VSSN  
MD[11]  
P4  
P5  
MA[23]  
MD[0]  
VSSN  
MD[4]  
VCCN  
L9  
L10  
L11  
L12  
L13  
L14  
P6  
P7  
P8  
P9  
P10  
BATT_VCC  
GPIO[54]  
GPIO[55]  
GPIO[57]  
nCS[2]/GPIO[78]  
MD[8]  
3.2  
Package Power Ratings  
Table 6.  
JA and Maximum Power Ratings  
Processor  
Max Power  
JA  
PXA250  
PXA210  
33 C /w  
44 C /w  
1.4W  
888W  
4.0  
Electrical Specifications  
4.1  
Absolute Maximum Ratings  
This section provide the Absolute Maximum ratings for the applications processors. Do not exceed  
these parameters. If you do the part may be permanently damaged. Operation at Absolute  
Maximum Ratings is not guaranteed.  
Table 7. Absolute Maximum Ratings (Sheet 1 of 2)  
Symbol  
Description  
Min  
Max  
Units  
TS  
Storage Temperature  
-40  
125  
deg C  
Offset Voltage between any two VSS pins (VSS, VSSQ,  
VSSN)  
VSS_O  
VCC_O  
-0.3  
-0.3  
0.3  
0.3  
V
V
Offset Voltage between any of the following pins:  
VCCQ and VCCN  
Voltage Applied to High Voltage Supplies (VCCQ, VCCN,  
BATT_VCC)  
VCC_HV  
VCC_LV  
VSS-0.3  
VSS-0.3  
VSS+4.0  
V
V
Voltage Applied to Low Voltage Supplies (VCC,  
PLL_VCC)  
VSS+1.65  
max of  
VCCQ+0.3,  
VSS+4.0  
VIP  
Voltage Applied to non-Supply pins except XTAL pins  
VSS-0.3  
V
Datasheet  
29  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 7. Absolute Maximum Ratings (Sheet 2 of 2)  
Symbol  
Description  
Min  
Max  
Units  
max of  
VCC+0.3,  
VSS+1.65  
Voltage Applied to XTAL pins (PXTAL, PEXTAL, TXTAL,  
TEXTAL)  
VIP_X  
VSS-0.3  
V
Maximum ESD stress voltage, Human Body Model; Any  
pin to any supply pin, either polarity, or Any pin to all non-  
supply pins together, either polarity. Three stresses  
maximum.  
VESD  
IEOS  
2000  
5
V
Maximum DC Input Current (Electrical Overstress) for any  
non-supply pin  
mA  
4.2  
Operating Conditions  
This section shows voltage, frequency, and temperature specifications for the applications  
processor for four different ranges (shown in Table 8, “Voltage, Temperature, and Frequency  
Electrical Specifications”.) The temperature specification for each range is constant; the frequency  
range is dependent on the operation voltage.  
Note: The parameters in Table 8 are preliminary and subject to change.  
Table 8. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2)  
Symbol  
Description  
Min  
Typical  
Max  
Units  
tA  
Ambient Temperature - Extended Temp  
Ambient Temperature - Nominal Temp  
VSS, VSSN, VSSQ Voltage  
VCCQ Voltage  
-40  
0
-
-
85  
70  
°C  
°C  
V
tA  
VVSS  
VVCCQ  
VVCCN  
VBATT  
-0.3  
3.0  
0
0.3  
3.6  
3.6  
3.8  
3.3  
2.5/3.3  
3.0  
V
VCCN Voltage  
2.375  
2.2  
V
BATT_VCC Voltage  
V
Low Voltage Range (PXA250 and PXA210)  
VVCC_L  
VCC, PLL_VCC Voltage, Low Range  
0.765  
99.5  
0.85  
1.00  
1.10  
0.935  
132.7  
V
fTURBO_L  
Turbo Mode Frequency, Low Range  
MHz  
External Synchronous Memory  
Frequency, Low Range  
fSDRAM_L  
50  
99.5  
MHz  
Medium Voltage Range (PXA250 and PXA210)  
VVCC_M  
VCC, PLL_VCC Voltage, Mid Range  
Turbo Mode Frequency, Mid Range  
0.90  
99.5  
1.10  
V
fTURBO_M  
199.1  
MHz  
External Synchronous Memory  
Frequency, Mid Range  
fSDRAM_M  
50  
99.5  
MHz  
High Voltage Range (PXA250)  
VVCC_H  
VCC, PLL_VCC Voltage, High Range  
0.99  
99.5  
1.21  
V
fTURBO_H  
Turbo Mode Frequency, High Range  
298.7  
MHz  
External Synchronous Memory  
Frequency, High Range  
fSDRAM_H  
50  
99.5  
MHz  
30  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 8. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2)  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Peak Voltage Range (PXA250)  
VVCC_P  
VCC, PLL_VCC Voltage, Peak Range  
Turbo Mode Frequency, Peak Range  
1.17  
99.5  
1.30  
1.43  
V
fTURBO_P  
398.2  
MHz  
External Synchronous Memory  
Frequency, Peak Range  
fSDRAM_P  
50  
99.5  
MHz  
4.3  
Targeted DC Specifications  
The DC Characteristics for each pin include input sense levels and output drive levels and currents.  
These parameters can be used to determine maximum DC loading, and also to determine maximum  
transition times for a given load. The DC Operating Conditions for the High- and Low-Strength  
Input, Output, and I/O pins are shown in Table 9, “Standard Input, Output, and I/O Pin DC  
Operating Conditions”. All DC specification values are valid for the entire temperature range of the  
device.  
Table 9. Standard Input, Output, and I/O Pin DC Operating Conditions  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Input DC Operating Conditions  
Input High Voltage, all standard input and  
I/O pins  
VIH  
VIL  
IIN  
0.8*VCCQ  
VSS  
VCCQ  
0.2*VCCQ  
10  
V
V
A
Input Low Voltage, all standard input and  
I/O pins  
Input Leakage, all standard input and IO  
pins  
Output DC Operating Conditions  
Output High Voltage, all standard output  
and I/O pins  
VOH  
VOL  
VCCQ-0.6  
VCCQ  
V
Output Low Voltage, all standard output  
and I/O pins  
VSS  
-10  
-3  
VSS+0.4  
V
Output High Current, all standard, high-  
strength output and I/O pins (VO=VOH)  
IOH_H  
IOH_L  
IOL_H  
IOL_L  
mA  
mA  
mA  
mA  
Output High Current, all standard, low-  
strength output and I/O pins (VO=VOH)  
Output Low Current, all standard, high-  
strength output and I/O pins (VO=VOH)  
10  
3
Output Low Current, all standard, low-  
strength output and I/O pins (VO=VOH)  
Datasheet  
31  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
4.4  
Targeted AC Specifications  
All the non-analog input, output, and I/O pins on the applications processor can be divided into one  
of two categories:  
1. High Strength Input, Output, and I/O pins:  
• nCS[5:1] (GP 33, 80, 79, 78, 15 respectively), nCS[0]  
• MD[31:0], MA[25:0]  
• DQM[3:0]  
• nOE, nWE, nSDRAS, nSDCAS, nSDCS[3:0]  
• SDCLK[2:0], SDCKE[1:0]  
• RDnWR, RDY (GP[18])  
• nPWE, nPOE pins (GP[49:48])  
• MMCLK (GP[53]), MMCMD, MMDAT  
• TDO  
• nACRESET  
2. Low Strength Input, Output, and I/O pins - all remaining non-supply pins  
A pin’s AC Characteristics include input and output capacitance. These determine loading for  
external drivers or other load analysis. The AC Characteristics also include a de-rating factor,  
which indicates how much faster or slower the AC timings get with different loads. The AC  
Operating Conditions for the high- and low-strength input, output, and I/O pins are shown in  
Table 10, “Standard Input, Output, and I/O Pin AC Operating Conditions”. All AC specification  
values are valid for entire temperature range of the device.  
Table 10. Standard Input, Output, and I/O Pin AC Operating Conditions  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Input Capacitance, all standard input and  
IO pins  
CIN  
10  
pF  
Output Capacitance, all standard high-  
strength output and IO pins  
COUT_H  
tdF_H  
251  
501  
pF  
Output de-rating, falling edge on all  
standard, high-strength output and I/O  
pins, from 50pF load.  
ns/pF  
Output de-rating, rising edge on all  
standard, high-strength output and I/O  
pins, from 50pF load.  
tdR_H  
ns/pF  
NOTE: AC Specifications guaranteed for loads in this range. All testing is done at 50pF  
32  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
4.5  
Oscillator Electrical Specifications  
The applications processor contains two oscillators: a 32.768 kHz oscillator and a 3.6864 MHz  
oscillator. Each is for a specific crystal. When choosing a crystal, match the crystal parameters as  
closely as possible.  
4.5.1  
32.768 kHz Oscillator Specifications  
The 32.768 kHz Oscillator is connected between the TXTAL (amplifier input) and TEXTAL  
(amplified output). The 32.768 kHz specifications are shown in Table 11, “32.768 kHz Oscillator  
Specifications”.  
Table 11. 32.768 kHz Oscillator Specifications  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Crystal Specifications - Typical is FOX NC38  
FXT  
LMT  
CMT  
RMT  
COT  
CLT  
Crystal Frequency, TXTAL/TEXTAL  
Motional Inductance, TXTAL/TEXTAL  
Motional Capacitance, TXTAL/TEXTAL  
Motional Resistance, TXTAL/TEXTAL  
Shunt Capacitance TXTAL to TEXTAL  
Load Capacitance TXTAL/TEXTAL  
32.768  
6827.81  
3.455  
16  
kHz  
H
fF  
6
35  
k
1.6  
pF  
pF  
12.5  
Amplifier Specifications  
VIH_X  
VIL_X  
Input High Voltage, TXTAL  
0.8*VCC  
VSS  
VCC  
V
V
Input Low Voltage, TXTAL  
Input Leakage, TXTAL  
0.2*VCC  
IIN_XT  
CIN_XT  
tS_XT  
1
A
Input Capacitance, TXTAL/TEXTAL  
Stabilization Time  
18  
-
25  
10  
pF  
s
2
Board Specifications  
Parasitic Resistance, TXTAL/TEXTAL to  
any node  
RP_XT  
CP_XT  
20  
M
Parasitic Capacitance, TXTAL/TEXTAL,  
total  
5
pF  
pF  
Parasitic Shunt Capacitance, TXTAL to  
TEXTAL  
COP_XT  
0.4  
To drive the 32.768 kHz crystal pins from an external source:  
• Drive the TEXTAL pin with a digital signal that has a low level near 0 volts and a high level  
near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew  
rate is 1 volt per 1 µs. The maximum current sourced by the external clock source when the  
clock is at its maximum positive voltage should be approximately 1 mA.  
• Float the TXTAL pin or drive it complementary to the TEXTAL pin, with the same voltage  
level, slew rate, and input current restrictions.  
Datasheet  
33  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
4.5.2  
3.6864 MHz Oscillator Specifications  
The 3.6864 MHz Oscillator is connected between the PXTAL (amplifier input) and PEXTAL  
(amplified output). The 3.6864 MHz specifications are shown in Table 12, “3.6864 MHz Oscillator  
Specifications”.  
Table 12. 3.6864 MHz Oscillator Specifications  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Crystal Specifications - Typical is FOX HC49S  
FXP  
LMP  
CMP  
RMP  
COP  
CLP  
Crystal Frequency, PXTAL/PEXTAL  
Motional Inductance, PXTAL/PEXTAL  
Motional Capacitance, PXTAL/PEXTAL  
Motional Resistance, PXTAL/PEXTAL  
Shunt Capacitance PXTAL to PEXTAL  
Load Capacitance PXTAL/PEXTAL  
3.6864  
0.50593  
3.68488  
99.3  
MHz  
H
fF  
50  
200  
W
1.7  
pF  
pF  
20  
Amplifier Specifications  
VIH_X  
VIL_X  
Input High Voltage, PXTAL  
0.8*VCC  
VSS  
VCC  
0.2*VCC  
10  
V
V
Input Low Voltage, PXTAL  
Input Leakage, PXTAL  
IIN_XP  
CIN_XP  
tS_XP  
A
Input Capacitance, PXTAL/PEXTAL  
Stabilization Time  
40  
50  
pF  
ms  
17.8  
20  
67.8  
Board Specifications  
Parasitic Resistance, PXTAL/PEXTAL to  
any node  
RP_XP  
CP_XP  
M
Parasitic Capacitance, PXTAL/PEXTAL,  
total  
5
pF  
pF  
Parasitic Shunt Capacitance, PXTAL to  
PEXTAL  
COP_XP  
0.4  
To drive the 3.6864 MHz crystal pins from an external source:  
• Drive the PEXTAL pin with a digital signal with a low level near 0 volts and a high level near  
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is  
1 volt / 100 ns. The maximum current sourced by the external clock source when the clock is  
at its maximum positive voltage should be approximately 1 mA.  
• Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage  
level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility  
will be introduced in the system, and it is therefore not recommended.  
34  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
4.6  
Reset and Power AC Timing Specifications  
The applications processor asserts the nRESET_OUT pin in one of several different modes:  
• Power On  
• Hardware Reset  
• Watchdog Reset  
• GPIO Reset  
• Sleep Mode  
The following sections give the timing and specifications for the entry and exit of these modes.  
4.6.1  
Power On Timing  
The External Voltage Regulator and other power-on devices must provide the applications  
processor with a specific sequence of power and resets to ensure proper operation. This sequence is  
shown in Figure 4, “Power-On Reset Timing” on page 36, and detailed in Table 13, “Power-On  
Timing Specifications” on page 36.  
On the applications processor, it is important that the power supplies be powered-up in a certain  
order to avoid high current situations. The required order is:  
1. BATT_VCC  
2. VCCQ  
3. VCCN  
4. VCC and PLL_VCC  
The supply in step 3 may be powered at the same time as those in step 2, however, VCCN should  
not be powered before VCCQ.  
Datasheet  
35  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Note: If Hardware Reset is entered during Sleep Mode, follow the proper power-supply stabilization  
times and nRESET timing requirements indicated in Table 13.  
Figure 4. Power-On Reset Timing  
t
R_BA  
T T  
t
R_VCCQ  
BATT_VCC  
VCCQ  
t
D_VCCQ  
t
R_VCC  
N
N
t
D_VCC  
t
R_VCC  
VCCN  
t
D_VCC  
VCC  
t
D_NTRST  
nTRST  
t
D_JT  
A G  
JTAG PINS  
nRESET  
t
D_NRESET  
t
D_OUT  
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is  
deasserted or the PXA250 applications processor enters Sleep Mode.  
Table 13. Power-On Timing Specifications  
Symbol  
Description  
Min  
Typical  
Max  
Units  
tR_BATT  
tR_VCCQ  
tR_VCC  
BATT_VCC Rise / Stabilization time  
VCCQ, VCCN Rise / Stabilization time  
VCC, PLL_VCC Rise / Stabilization time  
0.01  
0.01  
0.01  
100  
100  
10  
ms  
ms  
ms  
Delay between BATT_VCC at voltage  
and before VCCQ and VCCN applied  
tD_VCCQ  
tD_VCC  
0
0
ms  
ms  
ms  
ms  
ms  
ms  
Delay from VCCQ, VCCN at voltage and  
before VCC, PLL_VCC applied  
—
Delay between VCC, PLL_VCC stable  
and nTRST deasserted  
tD_NTRST  
tD_JTAG  
50  
Delay between nTRST deasserted and  
JTAG pins active, with nRESET asserted  
0.03  
50  
Delay between VCC, PLL_VCC stable  
and nRESET deasserted  
tD_NRESET  
tD_OUT  
Delay between nRESET deasserted and  
nRESET_OUT deasserted  
18.1  
18.2  
4.6.2  
Hardware Reset Timing  
The timing sequences shown in Hardware Reset Timing for hardware reset assumes stable power  
supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings  
indicated in Section 4.6.1, “Power On Timing” on page 35.  
36  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Figure 5. Hardware Reset Timing  
t
DHW_NRESET  
nRESET  
t
DHW_OUT  
nRESET_OUT  
t
DHW_OUT_A  
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is  
deasserted or the PXA250 applications processor enters Sleep Mode.  
Table 14. Hardware Reset Timing Specifications  
Symbol  
Description  
Min  
Typical  
Max  
Units  
tDHW_NRESET Minimum assertion time of nRESET  
0.001  
ms  
Delay between nRESET Asserted and  
tDHW_OUT_A  
0
0.001  
18.2  
ms  
ms  
nRESET_OUT Asserted  
Delay between nRESET deasserted and  
tDHW_OUT  
18.1  
nRESET_OUT deasserted  
4.6.3  
4.6.4  
Watchdog Reset Timing  
Watchdog Reset is an internally generated reset and therefore has no external pin dependencies.  
The nRESETOUT pin is the only indicator of Watchdog Reset, and it stays asserted for tDHW_OUT  
Refer to Figure 5, “Hardware Reset Timing” on page 37.  
.
GPIO Reset Timing  
GPIO Reset is generated externally, and the source is reconfigured as a standard GPIO as soon as  
the reset propagates internally. The clocks module is not reset by GPIO Reset, so the timing varies  
based on the frequency of clock selected and if the Clocks and Power Manager is in the Frequency  
Change Sequence when GPIO Reset is asserted (see Section 4.5.1, “32.768 kHz Oscillator  
Specifications” on page 33.) Figure 6, “GPIO Reset Timing” on page 37 shows the possible timing  
of GPIO Reset.  
Figure 6. GPIO Reset Timing  
t
A_GP[1]  
GP[1]  
nRESET_OUT  
t
DHW_OUT  
t
DHW_OUT_A  
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is  
deasserted or the application processor will enter Sleep Mode  
Datasheet  
37  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 15. GPIO Reset Timing Specifications  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Minimum assert time of GP[1]1 in  
3.6864MHz input clock cycles  
tA_GP[1]  
4
-
cycles  
Delay between GP[1] Asserted and  
tDHW_OUT_A nRESET_OUT Asserted in 3.6864MHz  
input clock cycles  
6
5
5
8
cycles  
Delay between nRESET_OUT asserted  
tDHW_OUT  
and nRESET_OUT deasserted, Run or  
Turbo Mode2  
28  
s
s
Delay between nRESET_OUT asserted  
tDHW_OUT_F and nRESET_OUT deasserted, during  
380  
Frequency Change Sequence3  
NOTES:  
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check  
the state of GP[1] before configuring as a Reset to ensure no spurious reset is generated.  
2. Time is 512*N Processor Clock Cycles plus up to 4 cycles of the 3.6864MHz input clock.  
3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the  
assertion of GPIO Reset. The Lock Detector has a maximum time of 350µs plus synchronization.  
4.6.5  
Sleep Mode Timing  
Sleep Mode is internally asserted, it and asserts the nRESET_OUT and PWR_EN signals. The  
sequence indicated in Figure 7, “Sleep Mode Timing” on page 38 and detailed in Figure 16, “Sleep  
Mode Timing Specifications” on page 39 is the required timing parameters for Sleep Mode.  
Figure 7. Sleep Mode Timing  
t
A_GP[x]  
GP[x]  
PWR_EN  
t
t
D_PWR_R  
D_PWR_F  
t
DSM_VCC  
VCC  
t
D_F  
A UL T  
nVDD_FAULT  
nRESET_OUT  
t
DSM_OUT  
Note: nBATT_FAULT must be high or the PXA250 applications processor  
will not exit Sleep Mode.  
38  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 16. Sleep Mode Timing Specifications  
Symbol  
Description  
Min  
Typical  
Max  
Units  
Assert Time of GPIO Wake up Source  
(x=[15:0])  
tA_GP[x}  
91.6  
s
Delay from nRESET_OUT asserted to  
PWR_EN deasserted  
tD_PWR_F  
tD_PWR_R  
tDSM_VCC  
tD_FAULT  
61  
91.6  
122.1  
10  
s
s
Delay between GP[x] asserted to  
PWR_EN asserted  
30.5  
Delay between PWR_EN asserted and  
VCC stable  
ms  
ms  
ms  
ms  
Delay between PWR_EN asserted and  
nVDD_FAULT deasserted  
10  
Delay between PWR_EN asserted and  
nRESET_OUT deasserted, OPDE Set  
tDSM_OUT  
tDSM_OUT_O  
28.0  
80  
Delay between PWR_EN asserted and  
nRESET_OUT deasserted, OPDE Clear  
10.35  
10.5  
4.7  
Memory Bus and PCMCIA AC Specifications  
This section gives the timing information for these types of memory:  
• SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 17, “SRAM /  
ROM / Flash / Synchronous Fast Flash AC Specifications” on page 39)  
• Variable Latency I/O (Table 18, “Variable Latency I/O Interface AC Specifications” on  
page 40)  
• Card Interface (PCMCIA or Compact Flash) (Table 19, “Card Interface (PCMCIA or Compact  
Flash) AC Specifications” on page 41)  
• Synchronous Memories (Table 20, “Synchronous Memory Interface AC Specifications1” on  
page 42)  
Table 17. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (Sheet 1 of 2)  
MEMCLK Frequency (MHz)  
Units,  
Symbol  
Description  
Notes  
99.5  
118.0  
132.7  
147.5  
165.9  
MA(25:0) setup to nCS, nOE, nSDCAS  
(as nADV) asserted  
tromAS  
tromAH  
10  
8.5  
7.5  
6.8  
6
ns, 1  
ns, 1  
MA(25:0) hold after nCS, nOE,  
nSDCAS (as nADV) deasserted  
10  
8.5  
7.5  
6.8  
6
tromASW  
tromAHW  
tromCES  
tromCEH  
MA(25:0) setup to nWE asserted  
MA(25:0) hold after nWE deasserted  
nCS setup to nWE asserted  
30  
10  
20  
10  
25.5  
8.5  
17  
22.5  
7.5  
15  
20.4  
6.8  
18  
6
ns, 3  
ns, 1  
ns, 2  
ns, 1  
13.6  
6.8  
12  
6
nCS hold after nWE deasserted  
8.5  
7.5  
MD(31:0), DQM(3:0) write data setup to  
nWE asserted  
tromDS  
10  
8.5  
7.5  
6.8  
6
ns, 1  
Datasheet  
39  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 17. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (Sheet 2 of 2)  
MEMCLK Frequency (MHz)  
Units,  
Symbol  
Description  
Notes  
99.5  
118.0  
132.7  
147.5  
165.9  
MD(31:0), DQM(3:0) write data setup to  
nWE deasserted  
tromDSWH  
tromDH  
20  
17  
15  
13.6  
12  
ns, 2  
ns, 1  
ns, 2  
MD(31:0), DQM(3:0) write data hold  
after nWE deasserted  
10  
20  
8.5  
17  
7.5  
15  
6.8  
6
nWE high time between beats of write  
data  
tromNWE  
13.6  
12  
NOTES:  
1. This number represents 1 MEMCLK period  
2. This number represents 2 MEMCLK periods  
3. This number represents 3 MEMCLK periods  
Table 18. Variable Latency I/O Interface AC Specifications  
MEMCLK Frequency (MHz)  
Units,  
Notes  
Symbol  
Description  
99.5  
118.0  
132.7  
147.5  
165.9  
tvlioAS  
MA(25:0) setup to nCS asserted  
10  
8.5  
7.5  
6.8  
6
ns, 1  
ns, 1  
MA(25:0) setup to nOE or nPWE  
asserted  
tvlioASRW  
10  
8.5  
7.5  
6.8  
6
MA(25:0) hold after nOE or nPWE  
deasserted  
tvlioAH  
tvlioCES  
tvlioCEH  
10  
20  
10  
8.5  
17  
7.5  
15  
6.8  
13.6  
6.8  
6
12  
6
ns, 1  
ns, 2  
ns, 1  
nCS setup to nOE or nPWE asserted  
nCS hold after nOE or nPWE  
deasserted  
8.5  
7.5  
MD(31:0), DQM(3:0) write data setup to  
nPWE asserted  
tvlioDSW  
tvlioDSWH  
tvlioDHW  
tvlioDHR  
10  
20  
10  
8.5  
17  
7.5  
15  
6.8  
13.6  
6.8  
6
12  
6
ns, 1  
ns, 2  
ns, 1  
MD(31:0), DQM(3:0) write data setup to  
nPWE deasserted  
MD(31:0), DQM(3:0) hold after nPWE  
deasserted  
8.5  
7.5  
MD(31:0) read data hold after nOE  
deasserted  
0
0
0
0
0
0
0
0
0
0
ns  
ns  
tvlioRDYH RDY hold after nOE, nPWE deasserted  
nPWE, nOE high time between beats of  
write or read data  
tvlioNPWE  
20  
17  
15  
13.6  
12  
ns, 2  
NOTES:  
1. This number represents 1 MEMCLK period  
2. This number represents 2 MEMCLK periods  
40  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 19. Card Interface (PCMCIA or Compact Flash) AC Specifications  
MEMCLK Frequency (MHz)  
Units,  
Notes  
Symbol  
Description  
99.5  
118.0  
132.7  
147.5  
165.9  
MA(25:0), nPREG, PSKTSEL, nPCE  
setup to nPWE, nPOE, nPIOW, or  
nPIOR asserted  
tcardAS  
tcardAH  
20  
17  
15  
13.6  
12  
ns, 1  
ns, 1  
MA(25:0), nPREG, PSKTSEL, nPCE  
hold after nPWE, nPOE, nPIOW, or  
nPIOR deasserted  
10  
8.5  
7.5  
6.8  
6
MD(31:0) setup to nPWE, nPOE,  
nPIOW, or nPIOR asserted  
tcardDS  
tcardDH  
10  
10  
30  
8.5  
8.5  
7.5  
7.5  
6.8  
6.8  
6
6
ns, 1  
ns, 1  
ns, 1  
MD(31:0) hold after nPWE, nPOE,  
nPIOW, or nPIOR deasserted  
nPWE, nPOE, nPIOW, or nPIOR  
command assertion  
tcardCMD  
25.5  
22.5  
20.4  
18  
NOTE: These numbers are minimums. They can be much longer based on the programmable Card Interface  
timing registers.  
Datasheet  
41  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Table 20. Synchronous Memory Interface AC Specifications1  
Units,  
Notes  
Symbol  
Description  
MIN  
MAX  
SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous)  
tsynCLK  
tsynCMD  
tsynRCD  
tsynCAS  
SDCLK period  
10  
1
20  
ns, 2  
sdclk  
sdclk  
sdclk  
nSDCAS, nSDRAS, nWE, nSDCS assert time  
nSDRAS to nSDCAS assert time  
1
nSDCAS to nSDCAS assert time  
2
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,  
tsynSDOS nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0)  
rise  
3.8  
3.6  
ns, 3  
ns, 3  
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,  
tsynSDOH nWE, nOE, SDCKE(1:0), RDnWR output hold time from  
SDCLK(2:0) rise  
tsynSDIS  
tsynDIH  
MD(31:0) read data input setup time from SDCLK(2:0) rise  
MD(31:0) read data input hold time from SDCLK(2:0) rise  
0.5  
1.5  
ns  
ns  
Fast Flash (Synchronous READS only)  
tffCLK  
tffAS  
SDCLK period  
15  
0.5  
0.5  
1
20  
ns, 4  
sdclk  
sdclk  
sdclk  
sdclk  
sdclk  
MA(25:0) setup to nSDCAS (as nADV) asserted  
nCS setup to nSDCAS (as nADV) asserted  
nSDCAS (as nADV) pulse width  
tffCES  
tffADV  
tffOS  
nSDCAS (as nADV) deassertion to nOE assertion  
nOE deassertion to nCS deassertion  
3
tffCEH  
4
NOTES:  
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.  
2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of  
the 99.5 MHz MEMCLK. It can be 99.5MHz at the fastest.  
3. This number represents 1/2 SDCLK period.  
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of  
the 132.7 MHz MEMCLK at its fastest.  
4.8  
Peripheral Module AC Specifications  
This section describes the AC Specifications for these peripheral units:  
• LCD  
• SSP  
42  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
4.8.1  
LCD Module AC Timing  
Figure 8 describes the LCD timing parameters. The LCD pin timing specifications are referenced  
to the pixel clock (L_PCLK). Values for the parameters are given in Table 21.  
Figure 8. LCD AC Timing Definitions  
L_PCLK  
T
pclkdv  
L_LDD[7:0]  
(rise)  
T
pclkdv  
L_LDD[7:0]  
(fall)  
T
pclklv  
L_LCLK  
L_BIAS  
L_FCLK  
T
pclkbv  
T
pclkfv  
A4775-01  
Table 21. LCD AC Timing Specifications  
Symbol  
Description  
Min  
Max  
Units  
Notes  
L_PCLK rise/fall to L_LDD<7:0> driven  
valid  
Tpclkdv  
14  
ns  
1
Tpclklv  
Tpclkfv  
Tpclkbv  
L_PCLK fall to L_LCLK driven valid  
L_PCLK fall to L_LFCLK driven valid  
L_PCLK rise to L_BIAS driven valid  
14  
14  
14  
ns  
ns  
ns  
2
2
2
NOTES:  
1. You can program the LCD data pins to be driven on either the rising or falling edge of the pixel clock  
(L_PCLK).  
2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time,  
they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin.  
4.8.2  
SSP Module AC Timing  
Figure 9, “SSP AC Timing Definitions” on page 44 describes the SSP timing parameters. The SSP  
pin timing specifications are referenced to SCLK_C. Values for the parameters are given in  
Table 22, “SSP AC Timing Specifications” on page 44.  
Datasheet  
43  
PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification  
Figure 9. SSP AC Timing Definitions  
SCLK_C  
T
sfmv  
SFRM_C  
TXD_C  
RXD_C  
T
sfmv  
T
T
rxdh  
rxds  
A4774-01  
Table 22. SSP AC Timing Specifications  
Symbol  
Description  
SCLK_C rise to SFRM_C driven valid  
Min  
Max  
Units  
Notes  
Tsfmv  
Trxds  
21  
ns  
ns  
RXD_C valid to SCLK_C fall (input setup)  
11  
0
SCLK_C fall to RXD_C invalid (input  
hold)  
Trxdh  
Tsfmv  
ns  
ns  
SCLK_C rise to TXD_C valid  
22  
4.8.3  
Boundary Scan Test Signal Timings  
Boundary scan test signal timing is shown in Table 23, “Boundary Scan Test Signal Timing”.  
Table 23. Boundary Scan Test Signal Timing (Sheet 1 of 2)  
Symbol  
Parameter  
TCK Frequency  
Min  
Max  
Units  
Notes  
TBSF  
0.0  
33.33  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TBSCH TCK High Time  
15.0  
15.0  
Measured at 1.5 V  
TBSCL TCK Low Time  
Measured at 1.5 V  
0.8 V to 2.0 V  
TBSCR TCK Rise Time  
5.0  
5.0  
TBSCF TCK Fall Time  
2.0 V to 0.8 V  
TBSIS1 Input Setup to TCK TDI, TMS  
TBSIH1 Input Hold from TCK TDI, TMS  
TBSIS2 Input Setup to TCK nTRST  
TBSIH2 Input Hold from TCK nTRST  
TBSOV1 TDO Valid Delay  
4.0  
6.0  
25.0  
3.0  
1.5  
1.1  
6.9  
5.4  
Relative to falling edge of TCK  
Relative to falling edge of TCK  
TOF1  
TDO Float Delay  
All Outputs (Non-Test) Valid  
Delay  
TOV12  
1.5  
6.9  
ns  
Relative to falling edge of TCK  
44  
Datasheet  
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210  
Table 23. Boundary Scan Test Signal Timing (Sheet 2 of 2)  
Symbol  
Parameter  
Min  
Max  
Units  
Notes  
All Outputs (Non-Test) Float  
Delay  
TOF2  
1.1  
5.4  
ns  
Relative to falling edge of TCK  
Input Setup to TCK All Inputs  
(Non-Test)  
TIS10  
TIH8  
4.0  
6.0  
ns  
ns  
Input Hold from TCK All Inputs  
(Non-Test)  
4.9  
AC Test Conditions  
The AC specifications in Section 4.4, “Targeted AC Specifications” on page 32 are tested with a  
50 pF load indicated in Figure 10.  
Figure 10. AC Test Load  
Output Ball  
C = 50pF  
L
C
L
Datasheet  
45  
厂商 型号 描述 页数 下载

ETC

 		PXA.M0.5GG.NB [ CONN RCPT FMALE 5POS GOLD SOLDER ] 76 页

MARVELL

 		PXA1088 WCDMA / TD -SCDMA通信处理器[ WCDMA/TD-SCDMA Communication Processor ] 2 页

MARVELL

 		PXA168 高性能，高集成度处理器可扩展到1.2 GHz的对成本敏感的，智能消费类和嵌入式设备[ High Performance, Highly Integrated Processor Scalable to 1.2 GHz for Cost-Sensitive, Intelligent Consumer and Embedded Devices ] 2 页

INTEL

 		PXA250 英特尔-R PXA250和PXA210应用处理器[ Intel-R PXA250 and PXA210 Applications Processors ] 46 页

INTEL

 		PXA255 PXA255处理器[ PXA255 Processor ] 40 页

INTEL

 		PXA270 电气，机械和热规格[ Electrical, Mechanical, and Thermal Specification ] 126 页

ACTEL

 		PXA270 为PXA270平台的存储解决方案[ Storage solution for PXA270 platform ] 2 页

ACTEL

 		PXA300 为Marvell公司的PXA300 / 310平台存储解决方案[ Storage Solution for Marvell’s PXA300/310 Platform ] 2 页

MARVELL

 		PXA300 可扩展性能高达624兆赫的高性价比和高能效的智能手机，嵌入式解决方案，以及手持设备[ Scalable Performance up to 624 MHz for Cost-Effective and Power-Efficient Smartphones, Embedded Solutions, and Handheld Devices ] 4 页

ACTEL

 		PXA310 为Marvell公司的PXA300 / 310平台存储解决方案[ Storage Solution for Marvell’s PXA300/310 Platform ] 2 页

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