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Intel® PXA255 Processor

Electrical, Mechanical, and Thermal Specification

Data Sheet

Product Features

■ High Performance Processor

—Intel® XScale™ Microarchitecture

—32 KB Instruction Cache

—32 KB Data Cache

■ Low Power

—Less than 500 mW Typical Internal

Dissipation

—Supply Voltage may be Reduced to

1.00 V

—2 KB “mini” Data Cache

—Extensive Data Buffering

■ Intel® Media Processing Technology

—Enhanced 16-bit Multiply

—40-bit Accumulator

—Low Power/Sleep Modes

■ High Performance Memory Controller

—Four Banks of SDRAM - up to 100 MHz

—Five Static Chip Selects

—Support for PCMCIA or Compact Flash

—Companion Chip interface

■ Flexible Clocking

—CPU clock from 100 to 400 MHz

—Flexible memory clock ratios

—Frequency change modes

■ Rich Serial Peripheral Set

—AC97 Audio Port

■ Additional Peripherals for system

connectivity

—Multimedia Card Controller (MMC)

—SSP Controller

—Network SSP controller for baseband

—I2C Controller

—I²S Audio Port

—USB Client Controller

—Two Pulse Width Modulators (PWMs)

—All peripheral pins double as GPIOs

■ Hardware debug features

—High Speed UART

—Second UART with flow control

—UART with hardware flow control

—FIR and SIR infrared comm ports

■ Hardware Performance Monitoring features

Order Number: 278805-002

February, 2004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The PXA255 processor EMTS Data Sheet may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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*Other names and brands may be claimed as the property of others.

2

Data Sheet

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

Contents

1.0 About This Document............................................................................................7

2.0 Functional Overview ..............................................................................................7

3.0 Package Information..............................................................................................8

3.1

Package Introduction.....................................................................................8

3.1.1 Functional Signal Definitions ............................................................8

3.1.1.1 PXA255 Processor Signal Pin Descriptions .....................8

Package Power Ratings ..............................................................................22

3.2

4.0 Electrical Specifications......................................................................................22

4.1

4.2

4.3

4.4

4.5

4.6

Absolute Maximum Ratings.........................................................................22

Power Consumption Specifications.............................................................23

Operating Conditions...................................................................................25

Targeted DC Specifications.........................................................................26

Targeted AC Specifications.........................................................................27

Oscillator Electrical Specifications...............................................................28

4.6.1 32.768-kHz Oscillator Specifications..............................................28

4.6.2 3.6864 MHz Oscillator Specifications.............................................29

Reset and Power AC Timing Specifications................................................30

4.7.1 Power-On Timing ...........................................................................30

4.7.2 Hardware Reset Timing..................................................................32

4.7.3 Watchdog Reset Timing.................................................................32

4.7.4 GPIO Reset Timing ........................................................................32

4.7.5 Sleep Mode Timing ........................................................................33

Memory Bus and PCMCIA AC Specifications .............................................35

Peripheral Module AC Specifications ..........................................................37

4.9.1 LCD Module AC Timing..................................................................37

4.9.2 SSP Module AC Timing..................................................................37

4.9.3 Boundary Scan Test Signal Timings ..............................................38

4.7

4.8

4.9

4.10 AC Test Conditions .....................................................................................39

Data Sheet

3

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

Figures

1

2

3

4

5

6

7

8

9

Processor Block Diagram......................................................................................8

PXA255 processor ..............................................................................................19

Power-On Reset Timing......................................................................................31

Hardware Reset Timing ......................................................................................32

GPIO Reset Timing.............................................................................................33

Sleep Mode Timing .............................................................................................34

LCD AC Timing Definitions .................................................................................37

SSP AC Timing Definitions .................................................................................38

AC Test Load ......................................................................................................39

Tables

1

2

3

4

5

6

7

8

9

Related Documentation.........................................................................................7

Processor Pin Types.............................................................................................9

Pin and Signal Descriptions for the PXA255 Processor........................................9

Pin Description Notes..........................................................................................18

PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order....20

θ

_JAand Maximum Power Ratings........................................................................22

Absolute Maximum Ratings ................................................................................23

Power Consumption Specifications for PXA255 processor ................................24

Voltage, Temperature, and Frequency Electrical Specifications.........................25

10 Standard Input, Output, and I/O Pin DC Operating Conditions...........................26

11 Standard Input, Output, I/O Pin DC Operating Conditions for 2.5-V Memory .....27

12 Standard Input, Output, and I/O Pin AC Operating Conditions ...........................28

13 32.768-kHz Oscillator Specifications...................................................................28

14 3.6864-MHz Oscillator Specifications .................................................................29

15 Power-On Timing Specifications .........................................................................31

16 Hardware Reset Timing Specifications ...............................................................32

17 GPIO Reset Timing Specifications......................................................................33

18 Sleep Mode Timing Specifications ......................................................................34

19 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications....................35

20 Variable Latency I/O Interface AC Specifications ...............................................35

21 Card Interface (PCMCIA or Compact Flash) AC Specifications .........................36

22 Synchronous Memory Interface AC Specifications 1 ..........................................36

23 LCD AC Timing Specifications ............................................................................37

24 SSP AC Timing Specifications ............................................................................38

25 Boundary Scan Test Signal Timing.....................................................................38

4

Data Sheet

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

Revision History

Date

Revision

Description

March 2003

-001

-002

First public release of the EMTS

Updated 400 MHz Idle mode power.

February 2004

Data Sheet

5

PXA255 Processor — Electrical, Mechanical, and Thermal Specification

6

Data Sheet

About This Document

1.0

About This Document

This is the electrical, mechanical, and thermal specification data sheet for the Intel® PXA255

Processor. This data sheet contains a functional overview, mechanical data, package signal

locations, targeted electrical specifications (simulated), and bus functional waveforms. Detailed

functional descriptions other than parametric performance is published in the Intel® PXA255

Processor Developer's Manual. Refer to Table 1, “Related Documentation” for a list of documents

that support the PXA255 processor.

Table 1. Related Documentation

Document Title

Order / Contact

Intel® PXA255 Processor Developer's Manual

278693

Intel® XScale^TMMicroarchitecture for the PXA250 and PXA210 Applications

Processors Developer's Manual

278525

278694

Intel® PXA255 Processor Design Guide

2.0

Functional Overview

The PXA255 processor provides high integration, high performance and low power consumption

for portable handheld and handset devices. These processors incorporate the Intel® XScale^™

Microarchitecture based on the ARM* V5TE architecture. Refer to the Intel® XScale^™

Microarchitecture for the Intel® PXA250 and PXA210 Applications Processors User’s Manual for

implementation details, extensions, and options implemented by the XScale microarchitecture.

The processor memory interface supports a variety of memory types that allow flexible design

requirements. Hooks for connection to two companion chips permit glueless connection to external

devices. An integrated LCD display controller supports displays and permits 1, 2, and 4-bit

grayscale, and 8- or 16-bit color pixels. A 256-byte palette RAM provides flexible color mapping

capabilities.

A rich set of serial devices as well as general-system resources provide enough compute and

connectivity capability for many applications. For details on the programming model and theory of

operation of each of these units, refer to the Intel® PXA255 Processor Developer's Manual. For the

processor block diagram, refer to Figure 1, “Processor Block Diagram” on page 8.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

7

Package Information

Figure 1. Processor Block Diagram

RTC

Color or

Grayscale

LCD

Memory

Controller

OS Timer

PWM(2)

Controller

Int.

Controller

Clocks &

Power Man.

Variable

Latency I/O

Control

ASIC

I²S

System Bus

I²C

AC97

PCMCIA

& CF

Control

Socket 0

Socket 1

XCVR

SDRAM/

SMROM

4 banks

UARTs

NSSP

Dynamic

Memory

Control

Intelﬁ XScale

Microarchitecture

ROM/

Flash/

SRAM

4 banks

Slow IrDA

Fast IrDA

SSP

Static

Memory

Control

3.6864 32.768

USB

Client

MHz

Osc

KHz

Osc

MMC

3.0

Package Information

3.1

Package Introduction

The PXA255 processor is offered in a 256-pin mBGA (refer to Figure 2, “PXA255 processor” on

page 19).

3.1.1

Functional Signal Definitions

3.1.1.1

PXA255 Processor Signal Pin Descriptions

Table 3, “Pin and Signal Descriptions for the PXA255 Processor” on page 9 describes the signal

definitions for the PXA255 processor. Figure 2, “PXA255 processor” on page 19 illustrates the

physical characteristics of the PXA255 processor. Table 5, “PXA255 processor 256-Lead

17x17mm mBGA Pinout — Ballpad No. Order” on page 20 describes the pinout for the PXA255

processor.

8

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Some of the processor pins can be connected to multiple signals. The GAFRn_m registers

determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be

routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed

twice—once in each unit that can use the pin. Not all peripherals can be used simutaneously in one

design because different peripherals share the same pins.

Table 2. Processor Pin Types

Type

Function

IC

CMOS input

OC

OCZ

CMOS output

CMOS output, Hi-Z

CMOS bidirectional, Hi-Z

Analog Input

ICOCZ

IA

OA

Analog output

IAOA

SUP

Analog bidirectional

Supply pin (either VCC or VSS)

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

Memory Controller Pins

Memory address bus. (output) Signals the address

requested for memory accesses.

MA[25:0]

MD[15:0]

MD[31:16]

nOE

OCZ

Driven Low

Memory data bus. (input/output) Lower 16 bits of the

data bus.

ICOCZ

OCZ

Hi-Z

Driven Low

Note [4]

Memory data bus. (input/output) Used for 32-bit

memories.

Hi-Z

Memory output enable. (output) Connect to the output

enables of memory devices to control data bus drivers.

Driven High

Memory write enable. (output) Connect to the write

enables of memory devices.

nWE

OCZ

Note [4]

SDRAM CS for banks 3 through 0. (output) Connect to

the chip select (CS) pins for SDRAM. For the PXA255

processor processor nSDCS0 can be Hi-Z, nSDCS1-3

cannot.

nSDCS[3:0]

DQM[3:0]

OCZ

Driven High

Driven Low

Note [5]

SDRAM DQM for data bytes 3 through 0. (output)

Connect to the data output mask enables (DQM) for

SDRAM.

Driven Low

SDRAM RAS. (output) Connect to the row address

strobe (RAS) pins for all banks of SDRAM.

nSDRAS

nSDCAS

OCZ

Driven High

SDRAM CAS. (output) Connect to the column address

strobe (CAS) pins for all banks of SDRAM.

Synchronous Static Memory clock enable. (output)

Connect to the CKE pins of SMROM. The memory

controller provides control register bits for de-assertion.

SDCKE[0]

OC

Driven Low

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

9

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

SDRAM and/or Synchronous Static Memory clock

enable. (output) Connect to the clock enable pins of

SDRAM. It is deasserted during sleep. SDCKE[1] is

always de-asserted upon reset. The memory controller

provides control register bits for de-assertion.

SDCKE[1]

OC

Driven low

Synchronous Static Memory clock. (output) Connect to

the clock (CLK) pins of SMROM. It is driven by either the

internal memory controller clock, or the internal memory

controller clock divided by 2. At reset, all clock pins are

free running at the divide-by-2 clock speed and may be

turned off via free-running control register bits in the

memory controller. The memory controller also provides

control register bits for clock division and deassertion of

each SDCLK pin. SDCLK[0] control register assertion bit

defaults to on if the boot-time static memory bank 0 is

configured for SMROM.

SDCLK[0]

OC

SDCLK[1]

SDCLK[2]

OCZ

OC

SDRAM Clocks (output) Connect SDCLK[1] and

SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1

and 2/3, respectively. They are driven by either the

internal memory controller clock, or the internal memory

controller clock divided by 2. At reset, all clock pins are

free running at the divide-by-2 clock speed and may be

turned off via free-running control register bits in the

memory controller. The memory controller also provides

control register bits for clock division and de-assertion of

each SDCLK pin. SDCLK[2:1] control register assertion

bits are always de-asserted upon reset.

Driven Low

nCS[5]/

ICOCZ

GPIO[33]

nCS[4]/

GPIO[80]

Static chip selects. (output) Chip selects to static

memory devices such as ROM and Flash. Individually

programmable in the memory configuration registers.

nCS[5:0] can be used with variable latency I/O devices.

nCS[3]/

Pulled High -

Note[1]

Note [4]

GPIO[79]

nCS[2]/

GPIO[78]

nCS[1]/

GPIO[15]

Static chip select 0. (output) Chip select for the boot

memory. nCS[0] is a dedicated pin.

nCS[0]

ICOCZ

OCZ

Driven High

Driven Low

Note [4]

Read/Write for static interface. (output) Signals that the

current transaction is a read or write.

RD/nWR

Holds last state

Variable latency I/O ready pin. (input) Notifies the

ICOCZ memory controller when an external bus device is ready

to transfer data.

RDY/

Pulled High -

Note[1]

Note [3]

GPIO[18]

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[8]/

GPIO[66]

Pulled High -

Note[1]

ICOCZ

Memory controller alternate bus master request.

(input) Allows an external device to request the system

bus from the memory controller.

10

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

LCD display data. (output) Transfers pixel information

L_DD[15]/

from the LCD controller to the external LCD panel.

Pulled High -

Note[1]

ICOCZ

Note [3]

GPIO[73]

Memory controller grant. (output) Notifies an external

device that it has been granted the system bus.

MBGNT/

GP[13]

Memory controller grant. (output) Notifies an external

device that it has been granted the system bus.

Pulled High -

Note[1]

ICOCZ

Note [3]

Memory controller alternate bus master request.

ICOCZ (input) Allows an external device to request the system

MBREQ/

GP[14]

Pulled High -

Note[1]

bus from the memory controller.

PCMCIA/CF Control Pins

nPOE/

PCMCIA output enable. (output) Reads from PCMCIA

memory and to PCMCIA attribute space.

Pulled High -

Note[1]

ICOCZ

GPIO[48]

Note [5]

PCMCIA write enable. (output) Performs writes to

ICOCZ PCMCIA memory and to PCMCIA attribute space. Also

nPWE/

Pulled High -

Note[1]

GPIO[49]

used as the write enable signal for variable latency I/O.

nPIOW/

PCMCIA I/O write. (output) Performs write transactions

to PCMCIA I/O space.

Pulled High -

Note[1]

ICOCZ

Note [5]

GPIO[51]

nPIOR/

PCMCIA I/O read. (output) Performs read transactions

from PCMCIA I/O space.

Pulled High -

Note[1]

ICOCZ

GPIO[50]

PCMCIA card enable 2. (output) Selects a PCMCIA

nPCE[2]/

GPIO[53]

card. nPCE[2] enables the high byte lane and nPCE[1]

enables the low byte lane.

Pulled High -

Note[1]

ICOCZ

Note [5]

MMC clock. (output) Clock signal for the MMC controller.

PCMCIA card enable 1. (outputs) Selects a PCMCIA

ICOCZ card. nPCE[2] enables the high byte lane and nPCE[1]

enables the low byte lane.

nPCE[1]/

GPIO[52]

Pulled High -

Note[1]

Note [5]

IO Select 16. (input) Acknowledge from the PCMCIA

ICOCZ card that the current address is a valid 16 bit wide I/O

address.

nIOIS16/

GPIO[57]

Pulled High -

Note[1]

PCMCIA wait. (input) Driven low by the PCMCIA card to

ICOCZ extend the length of the transfers to/from the PXA255

processor processor.

nPWAIT/

GPIO[56]

Pulled High -

Note[1]

PCMCIA socket select. (output) Used by external

steering logic to route control, address, and data signals

to one of the two PCMCIA sockets. When PSKTSEL is

low, socket zero is selected. When PSKTSEL is high,

socket one is selected. Has the same timing as the

PSKTSEL/

GPIO[54]

Pulled High -

Note[1]

ICOCZ

Note [5]

address bus.

PCMCIA register select. (output) Indicates that the

ICOCZ target address on a memory transaction is attribute

space. Has the same timing as the address bus.

nPREG/

Pulled High -

Note[1]

GPIO[55]

LCD Controller Pins

L_DD(7:0)/

LCD display data. (outputs) Transfers pixel information

from the LCD Controller to the external LCD panel.

Pulled High -

Note[1]

ICOCZ

Note [3]

GPIO[65:58]

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[8]/

GPIO[66]

Pulled High -

Note[1]

ICOCZ

Memory controller alternate bus master request.

(input) Allows an external device to request the system

bus from the Memory Controller.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

11

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

LCD display data. (output) Transfers pixel information

L_DD[9]/

from the LCD controller to the external LCD panel.

Pulled High -

Note[1]

ICOCZ

Note [3]

GPIO[67]

MMC chip select 0. (output) Chip select 0 for the MMC

controller.

LCD display data. (output) Transfers pixel information

L_DD[10]/

GPIO[68]

from the LCD controller to the external LCD panel.

Pulled High -

Note[1]

ICOCZ

Note [3]

MMC chip select 1. (output) Chip select 1 for the MMC

controller.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[11]/

GPIO[69]

Pulled High -

Note[1]

ICOCZ

Note [3]

MMC clock. (output) Clock for the MMC controller.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[12]/

GPIO[70]

Pulled High -

Note[1]

RTC clock. (output) Real-time clock 1 Hz tick.

LCD display data. (output) Transfers pixel information

L_DD[13]/

GPIO[71]

from the LCD controller to the external LCD panel.

Pulled High -

Note[1]

ICOCZ

Note [3]

3.6864 MHz clock. (output) Output from 3.6864 MHz

oscillator.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[14]/

GPIO[72]

Pulled High -

Note[1]

32 kHz clock. (output) Output from the 32 kHz oscillator.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[15]/

GPIO[73]

Pulled High -

Note[1]

Memory Controller grant. (output) Notifies an external

device it has been granted the system bus.

L_FCLK/

GPIO[74]

LCD frame clock. (output) Indicates the start of a new

frame. Also referred to as Vsync.

Pulled High -

Note[1]

ICOCZ

Note [3]

L_LCLK/

GPIO[75]

LCD line clock. (output) Indicates the start of a new line. Pulled High -

Also referred to as Hsync. Note[1]

L_PCLK/

GPIO[76]

LCD pixel clock. (output) Clocks valid pixel data into the Pulled High -

LCD line-shift buffer.

Note[1]

AC bias drive. (output) Notifies the panel to change the

ICOCZ polarity for some passive LCD panel. For TFT panels,

this signal indicates valid pixel data.

L_BIAS/

Pulled High -

Note[1]

Note [3]

GPIO[77]

Full Function UART Pins

Full function UART receive. (input)

FFRXD/

ICOCZ

Pulled High -

Note[1]

Note [3]

MMC chip select 0. (output) Chip select 0 for the MMC

Controller.

GPIO[34]

Full Function UART transmit. (output)

FFTXD/

ICOCZ

Pulled High -

Note[1]

MMC chip select 1. (output) Chip select 1 for the MMC

Controller.

GPIO[39]

FFCTS/

Pulled High -

Note[1]

ICOCZ Full function UART clear-to-send. (input)

ICOCZ Full function UART data-carrier-detect. (input)

ICOCZ Full function UART data-set-ready. (input)

Note [3]

GPIO[35]

FFDCD/

Pulled High -

Note[1]

GPIO[36]

FFDSR/

Pulled High -

Note[1]

GPIO[37]

12

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

Note [3]

FFRI/

Pulled High -

Note[1]

ICOCZ Full function UART ring indicator. (input)

ICOCZ Full function UART data-terminal-ready. (output)

ICOCZ Full function UART request-to-send. (output)

GPIO[38]

FFDTR/

Pulled High -

Note[1]

Note [3]

GPIO[40]

FFRTS/

Pulled High -

Note[1]

GPIO[41]

Bluetooth UART Pins

BTRXD/

Pulled High -

Note[1]

ICOCZ Bluetooth UART receive. (input)

Note [3]

GPIO[42]

BTTXD/

Pulled High -

Note[1]

ICOCZ Bluetooth UART transmit. (output)

ICOCZ Bluetooth UART clear-to-send. (input)

ICOCZ Bluetooth UART request-to-send. (output)

GPIO[43]

BTCTS/

Pulled High -

Note[1]

GPIO[44]

BTRTS/

Pulled High -

Note[1]

GPIO[45]

Standard UART and ICP Pins

IrDA receive signal. (input) Receive pin for the FIR

function.

IRRXD/

Pulled High -

Note[1]

ICOCZ

Note [3]

GPIO[46]

Standard UART receive. (input)

IrDA transmit signal. (output) Transmit pin for the

Standard UART, SIR and FIR functions.

IRTXD/

Pulled High -

Note[1]

GPIO[47]

Standard UART transmit. (output)

Hardware UART Pins

HWRXD/

Pulled High -

Note[1]

ICOCZ Hardware UART receive. (input)

Note [3]

GPIO[42/49]

HWTXD/

Pulled High -

Note[1]

ICOCZ Hardware UART transmit. (output)

ICOCZ Hardware UART clear-to-send. (input)

ICOCZ Hardware UART data-terminal-ready. (output)

GPIO[43/48]

HWCTS/

Pulled High -

Note[1]

GPIO[44/50]

HWRTS/

Pulled High -

Note[1]

GPIO[45/51]

MMC Controller Pins

MMCMD

MMDAT

ICOCZ Multimedia card command. (bidirectional)

Hi-Z

ICOCZ Multimedia card data. (bidirectional)

PCMCIA card enable 2. (outputs) Selects a PCMCIA

nPCE[2]/

GPIO[53]

card. Bit one enables the high byte lane and bit zero

enables the low byte lane.

Pulled High -

Note[1]

ICOCZ

Note [5]

Note [3]

MMC clock. (output) Clock signal for the MMC controller.

LCD display data. (output) Transfers pixel information

L_DD[9]/

GPIO[67]

from the LCD controller to the external LCD panel.

ICOCZ

Pulled High -

Note[1]

MMC chip select 0. (output) Chip select 0 for the MMC

controller.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

13

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

LCD display data. (output) Transfers pixel information

L_DD[10]/

from the LCD controller to the external LCD panel.

Pulled High -

Note[1]

ICOCZ

Note [3]

GPIO[68]

MMC chip select 1. (output) Chip select 1 for the MMC

controller.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[11]/

GPIO[69]

Pulled High -

Note[1]

ICOCZ

Note [3]

MMC clock. (output) Clock for the MMC controller.

Full function UART receive. (input)

FFRXD/

Pulled High -

Note[1]

MMC chip select 0. (output) Chip select 0 for the MMC

controller.

GPIO[34]

Full function UART transmit. (output)

FFTXD/

Pulled High -

Note[1]

MMC chip select 1. (output) Chip select 1 for the MMC

controller.

GPIO[39]

MMCCLK/

GP[6]

Pulled High -

Note[1]

ICOCZ MMC clock. (output) Clock signal for the MMC controller.

Note [3]

MMCCS0/

GP[8]

MMC chip select 0. (output) Chip select 0 for the MMC

controller.

Pulled High -

Note[1]

ICOCZ

MMCCS1/

GP[9]

MMC chip select 1. (output) Chip select 1 for the MMC

controller.

Pulled High -

Note[1]

ICOCZ

SSP Pins

SSPSCLK/

GPIO[23]

Pulled High -

Note[1]

ICOCZ Synchronous serial port clock. (output)

ICOCZ Synchronous serial port frame. (output)

ICOCZ Synchronous serial port transmit. (output)

ICOCZ Synchronous serial port receive. (input)

ICOCZ Synchronous serial port external clock. (input)

Note [3]

SSPSFRM/

GPIO[24]

Pulled High -

Note[1]

SSPTXD/

GPIO[25]

Pulled High -

Note[1]

SSPRXD/

GPIO[26]

Pulled High -

Note[1]

SSPEXTCLK/

GPIO[27]

Pulled High -

Note[1]

NSSP Pins

NSSPSCLK/

GPIO[81]

Pulled High -

Note[1]

ICOCZ Network synchronous serial port clock. (output/input)

ICOCZ Network synchronous serial port frame. (output/input)

Note [3]

NSSPSFRM/

GPIO[82]

Pulled High -

Note[1]

NSSPTXD/

GPIO[83]

Network synchronous serial port transmit/recieve.

(output/input)

Pulled High -

Note[1]

ICOCZ

NSSPRXD/

GPIO[84]

Network synchronous serial port transmit/receive.

(output/input)

Pulled High -

Note[1]

ICOCZ

USB Client Pins

USB_P

IAOAZ USB client positive. (bidirectional)

Hi-Z

USB_N

IAOAZ USB client negative pin. (bidirectional)

14

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

AC97 Controller and I²S Controller Pins

AC97 audio port bit clock. (input) AC97 clock is

generated by Codec 0 and fed into the PXA255

processor processor and Codec 1.

AC97 Aaudio port bit clock. (output) AC97 clock is

generated by the PXA255 processor.

I²S bit clock. (input) I²S clock is generated externally

BITCLK/

Pulled High -

Note[1]

ICOCZ

Note [3]

GPIO[28]

and fed into PXA255 processor.

I²S bit clock. (output) I²S clock is generated by the

PXA255 processor.

SDATA_IN0/

GPIO[29]

AC97 audio port data in. (input) Input line for Codec 0.

I²S data in. (input) Input line for the I²S controller.

Pulled High -

Note[1]

ICOCZ

Note [3]

AC97 audio port data in. (input) Input line for Codec 1.

I²S system clock. (output) System clock from I²S

controller.

SDATA_IN1/

GPIO[32]

Pulled High -

Note[1]

AC97 audio port data out. (output) Output from the

PXA255 processor to Codecs 0 and 1.

I²S data out. (output) Output line for the I²S controller.

SDATA_OUT/

GPIO[30]

Pulled High -

Note[1]

ICOCZ

Note [3]

AC97 audio port sync signal. (output) Frame sync

SYNC/

signal for the AC97 controller.

I²S sync. (output) Frame sync signal for the I²S

controller.

Pulled High -

Note[1]

ICOCZ

OC

Note [3]

GPIO[31]

nACRESET

AC97 audio port reset signal. (output)

Driven Low

I²C Controller Pins

SCL

ICOCZ I²C clock. (bidirectional)

Hi-Z

SDA

ICOCZ I²C data. (bidirectional).

PWM Pins

PWM[1:0]/

Pulled High -

Note[1]

ICOCZ Pulse width modulation channels 0 and 1. (outputs)

Note [3]

GPIO[17:16]

DMA Pins

DMA request. (input) Notifies the DMA Controller that an

ICOCZ external device requires a DMA transaction. DREQ[1] is

GPIO[19]. DREQ[0] is GPIO[20].

DREQ[1:0]/

GPIO[19:20]

Pulled High -

Note[1]

GPIO Pins

GPIO[1:0]

General purpose I/O. Wakeup sources on both rising

and falling edges on nRESET.

Pulled High -

Note[1]

ICOCZ

Note [3]

General purpose I/O. More wakeup sources for sleep

Pulled High -

Note[1]

GPIO[14:2]

ICOCZ

mode.

General purpose I/O. Additional General Purpose I/O

Pulled High -

Note[1]

GPIO[22:21]

ICOCZ

pins.

Crystal and Clock Pins

3.6864 MHz crystal input. No external caps are

required.

PXTAL

OA

Note [2]

3.6864 MHz crystal output. No external caps are

required.

PEXTAL

TXTAL

IA

Note [2]

OA

32 KHz crystal input. No external caps are required.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

15

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)

Pin Name

TEXTAL

Type

IA

Signal Descriptions

Reset State

Note [2]

Sleep State

Note [2]

32 kHz crystal output. No external caps are required.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[12]/

GPIO[70]

Pulled High -

Note[1]

ICOCZ

Note [3]

RTC clock. (output) Real time clock 1 Hz tick.

LCD display data. (output) Transfers the pixel

information from the LCD controller to the external LCD

panel.

L_DD[13]/

GPIO[71]

Pulled High -

Note[1]

Note [3]

3.6864 MHz clock. (output) Output from 3.6864 MHz

oscillator.

LCD display data. (output) Transfers pixel information

from the LCD controller to the external LCD panel.

L_DD[14]/

GPIO[72]

Pulled High -

Note[1]

Note [3]

32 kHz clock. (output) Output from the 32 kHz oscillator.

48 MHz clock. (output) Peripheral clock output derived

from the PLL.

NOTE: This clock is only generated when the USB unit

clock enable is set.

Pulled High -

Note[1]

48MHz/GP[7]

ICOCZ

RTCCLK/

GP[10]

Real time clock. (output) 1 Hz output derived from the

32 kHz or 3.6864 MHz output.

Pulled High -

Note[1]

Note [3]

3.6864 MHz clock. (output) Output from 3.6864 MHz

oscillator.

Pulled High -

Note[1]

3.6MHz/GP[11] ICOCZ

32kHz/GP[12]

Pulled High -

Note[1]

ICOCZ 32 kHz clock. (output) Output from the 32 kHz oscillator.

Miscellaneous Pins

BOOT_SEL

IC

Boot select pins. (input) Indicates type of boot device.

Input

[2:0]

Driven low while

entering sleep

mode. Driven high

when sleep exit

sequence begins.

Power Enable for the power supply. (output) When

negated, it signals the power supply to remove power to

the core because the system is entering sleep mode.

PWR_EN

OC

Driven High

Main Battery Fault. (input) Signals that main battery is

low or removed. Assertion causes PXA255 processor

processor to enter sleep mode or force an imprecise data

exception, which cannot be masked. PXA255 processor

will not recognize a wake-up event while this signal is

asserted. Minimum assertion time for nBATT_FAULT is 1

ms.

nBATT_FAULT IC

Input

VDD Fault. (input) Signals that the main power source is

going out of regulation. nVDD_FAULT causes the

PXA255 processor to enter sleep mode or force an

imprecise data exception, which cannot be masked.

nVDD_FAULT is ignored after a wake-up event until the

power supply timer completes (approximately 10 ms).

Minimum assertion time for nVDD_FAULT is 1 ms.

nVDD_FAULT

IC

Hard reset. (input) Level -sensitive input used to start the

processor from a known address. Assertion terminates

the current instruction abnormally and causes a reset.

When nRESET is driven high, the processor starts

execution from address 0. nRESET must remain low until

the power supply is stable and the internal 3.6864 MHz

oscillator has stabilized.

Input. Driving low

during sleep will

cause normal

reset sequence

and exit from sleep

mode.

nRESET

16

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

Reset out. (output) Asserted when nRESET is asserted

and deasserts after nRESET is de-asserted but before

the first instruction fetch. nRESET_OUT is also asserted

for “soft” reset events: sleep, watchdog reset, or GPIO

reset.

Driven low during

any reset sequence

- driven high prior to

first fetch.

nRESET_OUT OC

JTAG and Test Pins

Driven Low

JTAG test interface reset. Resets the JTAG/debug port.

If JTAG/debug is used, drive nTRST from low to high

either before or at the same time as nRESET. If JTAG is

not used, nTRST must be either tied to nRESET or tied

low.

nTRST

IC

Input

JTAG test data input. (input) Data from the JTAG

TDI

IC

controller is sent to the PXA255 processor using this pin. Input

This pin has an internal pull-up resistor.

Input

Hi-Z

JTAG test data output. (output) Data from the PXA255

TDO

OCZ

processor is returned to the JTAG controller using this

pin.

Hi-Z

JTAG test mode select. (input) Selects the test mode

required from the JTAG controller. This pin has an

internal pull-up resistor.

TMS

TCK

IC

Input

JTAG test clock. (input) Clock for all transfers on the

JTAG test interface.

TEST

IC

Test Mode. (input) Reserved. Must be grounded.

Test Clock. (input) Reserved. Must be grounded.

Input

TESTCLK

Power and Ground Pins

Positive supply for internal logic. Must be connected

to the low voltage supply on the PCB.

VCC

SUP

Powered

Grounded

Powered

Grounded

Note [6]

Ground supply for internal logic. Must be connected to

the common ground plane on the PCB.

VSS

Grounded

Note [6]

Positive supply for PLLs and oscillators. Must be

connected to the common low voltage supply.

PLL_VCC

PLL_VSS

Ground supply for the PLL. Must be connected to

common ground plane on the PCB.

Grounded

Positive supply for all CMOS I/O except memory bus

and PCMCIA pins. Must be connected to the common

3.3v supply on the PCB.

VCCQ

VSSQ

VCCN

VSSN

SUP

Powered

Note [7]

Ground supply for all CMOS I/O except memory bus

and PCMCIA pins. Must be connected to the common

ground plane on the PCB.

Grounded

Note [7]

Positive supply for memory bus and PCMCIA pins.

Must be connected to the common 3.3v or 2.5v supply on Powered

the PCB.

Ground supply for memory bus and PCMCIA pins.

Must be connected to the common ground plane on the

PCB.

Grounded

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

17

Package Information

Table 4. Pin Description Notes

Note

Description

GPIO reset operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are

disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input paths

must be enabled and the pullups turned off by clearing the read-disable-hold (RDH) bit described in

Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-27 in the Intel® PXA255 Processor

Developers Manual. Even though sleep mode sets the RDH bit, the pull-up resistors are not re-enabled by sleep

mode.

[1]

[2]

Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators. Refer to Section 3.3.1,

“32.768 kHz Oscillator” on page 3-4 in the Intel® PXA255 Processor Developers Manual and Section 3.3.2,

“3.6864 MHz Oscillator” on page 3-4 of the Intel® PXA255 Processor Developers Manual for details on sleep-

mode operation.

GPIO sleep operation: The state of these pins is determined by the corresponding PGSRn during the transition

into sleep mode. See Section 3.5.9, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)”

and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 in the Intel®

PXA255 Processor Developers Manual. If selected as an input, this pin does not drive during sleep. If selected

as an output, the value contained in the sleep-state register is driven out onto the pin and held there while the

PXA255 processor is in sleep mode.

[3]

GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.

Static memory control pins: During sleep mode, these pins can be programmed to either drive the value in the

sleep-state register or be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the power-

manager general-configuration register. If PCFR[FS] is not set, then during the transition to sleep these pins

function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by

the memory controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.

[4]

[5]

PCMCIA control pins: During sleep mode: can be programmed either to drive the value in the sleep-state

register or be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the

transition to sleep these pins function as described in [3], above.

[6]

[7]

During sleep, this supply may be driven low. This supply must never be high impedance.

Remains powered in sleep mode.

18

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Figure 2. PXA255 processor

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

19

Package Information

Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet 1

of 3)

Ball #

Signal

Ball #

Signal

Ball #

Signal

A1

A2

VCCN

C10

C11

C12

C13

C14

C15

C16

D1

VCCQ

VSSQ

USB_P

VCCQ

VSSQ

F3

F4

nSDCAS

VCCN

L_DD[13]/GPIO[71]

L_DD[12]/GPIO[70]

L_DD[11]/GPIO[69]

L_DD[9]/GPIO[67]

L_DD[7]/GPIO[65]

GPIO[11]

A3

F5

SDCLK[1]

VSSQ

A4

F6

A5

F7

GPIO[10]

FFRTS/GPIO[41]

SSPSCLK/GPIO[23]

FFDTR/GPIO[40]

VCC

A6

IRTXD/GPIO[47]

VSS

F8

A7

F9

A8

L_BIAS/GPIO[77]

SSPRXD/GPIO[26]

SDATA_OUT/GPIO[30]

SDA

SDCLK[2]

F10

F11

F12

F13

F14

F15

F16

G1

A9

D2

SDCLK[0]

A10

A11

A12

A13

A14

A15

A16

B1

D3

RDnWR

GPIO[9]

D4

VCCN

BOOT_SEL[2]

GPIO[8]

FFDCD/GPIO[36]

FFRXD/GPIO[34]

FFCTS/GPIO[35]

BTCTS/GPIO[44]

SDATA_IN1/GPIO[32]

DQM[1]

D5

L_DD[10]/GPIO[68]

L_DD[5]/GPIO[63]

L_DD[1]/GPIO[59]

L_LCLK/GPIO[75]

SSPTXD/GPIO[25]

nACRESET

D6

VSSQ

D7

NSSPSCLK/GPIO[81]

MA[0]

D8

D9

G2

VSSN

D10

D11

D12

D13

D14

D15

D16

E1

G3

nSDCS[2]

nWE

B2

DQM[2]

SCL

G4

B3

L_DD[15]/GPIO[73]

GPIO[14]

PWM[1]/GPIO[17]

BTTXD/GPIO[43]

MMCMD

G5

nOE

B4

G6

nSDCS[1]

VCC

B5

GPIO[13]

G7

B6

GPIO[12]

VCCQ

G8

VSSQ

B7

L_DD[3]/GPIO[61]

L_PCLK/GPIO[76]

SSPEXTCLK/GPIO[27]

FFRI/GPIO[38]

FFDSR/GPIO[37]

USB_N

NSSPRXD/GPIO[84]

nSDRAS

G9

VCC

B8

G10

G11

G12

G13

G14

G15

G16

H1

VSSQ

B9

E2

VSSN

TESTCLK

TEST

B10

B11

B12

B13

B14

B15

B16

C1

E3

SDCKE[1]

E4

SDCKE[0]

BOOT_SEL[1]

VCCQ

E5

L_DD[6]/GPIO[64]

L_DD[4]/GPIO[62]

L_DD[[0]/GPIO[58]

L_FCLK/GPIO[74]

SSPSFRM/GPIO[24]

SDATA_IN0/GPIO[29]

SYNC/GPIO[31]

PWM[0]/GPIO[16]

FFTXD/GPIO[39]

BTRXD/GPIO[42]

BTRTS/GPIO[45]

IRRXD/GPIO[46]

MMDAT

E6

GPIO[7]

E7

BOOT_SEL[0]

MA[2]

E8

E9

H2

MA[1]

RDY/GPIO[18]

VSSN

E10

E11

E12

E13

H3

MD[16]

C2

H4

VCCN

C3

L_DD[14]/GPIO[72]

VSSQ

H5

MD[17]

C4

H6

MA[3]

20

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Package Information

Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet 2

of 3)

Ball #

Signal

Ball #

Signal

Ball #

Signal

C5

C6

C7

C8

C9

H12

H13

H14

H15

H16

J1

L_DD[8]/GPIO[66]

VCCQ

E14

E15

E16

F1

VCCQ

H7

H8

VSSQ

VSS

NSSPTXD/GPIO[83]

NSSPSFRM/GPIO[82]

nSDCS[0]

nSDCS[3]

VCC

L_DD[2]/GPIO[60]

VSSQ

H9

VSS

H10

H11

P6

VCC

BITCLK/GPIO[28]

TCK

F2

nTRST

MD[24]

MD[26]

MD[27]

L9

TMS

L10

L11

L12

L13

L14

L15

L16

M1

GPIO[0]

PWR_EN

GPIO[1]

GPIO[2]

VSSQ

P7

GPIO[6]

TDI

P8

P9

nCS[2]/GPIO[78]

MD[29]

TDO

P10

P11

P12

P13

P14

P15

P16

R1

MA[7]

MD[12]

J2

VSSN

TEXTAL

TXTAL

MD[31]

J3

MA[6]

nPOE/GPIO[48]

nPCE[1]/GPIO[52]

VSSN

J4

MD[18]

MA[5]

MA[14]

J5

M2

MD[21]

J6

MA[4]

M3

MA[15]

nPSKTSEL/GPIO[54]

MA[18]

J7

VCC

M4

VCCN

J8

VSS

M5

MD[1]

R2

VSSN

J9

VSS

M6

MD[6]

R3

MA[20]

J10

J11

J12

J13

J14

J15

J16

K1

VSSQ

M7

MD[7]

R4

VSSN

GPIO[5]

GPIO[4]

nRESET

VSSQ

M8

M9

DQM[0]

MD[8]

R5

MA[22]

R6

VSSN

M10

M11

M12

M13

M14

M15

M16

N1

MD[15]

R7

MD[25]

VCCQ

R8

VSSN

PLL_VCC

PLL_VSS

MA[8]

GPIO[22]

nPREG/GPIO[55]

VCCN

R9

MD[10]

R10

R11

R12

R13

R14

R15

R16

T1

VSSN

MD[30]

K2

MA[9]

VSSN

K3

MD[19]

VCCN

nIOIS16/GPIO[57]

MD[22]

nCS[4]/GPIO[80]

VSSN

K4

K5

MA[10]

MA[11]

VSSQ

N2

VSSN

nPIOW/GPIO[51]

nPCE[2]/GPIO[53]

VSS

K6

N3

MA[16]

K7

N4

MD[0]

K8

VCC

N5

VCCN

T2

VCCN

K9

VSSQ

N6

MD[4]

T3

MD[23]

K10

K11

VCC

N7

VCCN

T4

MA[21]

nRESET_OUT

N8

nCS[0]

T5

MA[24]

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

21

Electrical Specifications

Table 5. PXA255 processor 256-Lead 17x17mm mBGA Pinout — Ballpad No. Order (Sheet 3

of 3)

Ball #

Signal

Ball #

Signal

Ball #

Signal

K12

K13

K14

K15

K16

L1

nBATT_FAULT

nVDD_FAULT

GPIO[3]

PXTAL

N9

N10

N11

N12

N13

N14

N15

N16

P1

VCCN

MD[13]

VCCN

T6

T7

MD[3]

MD[5]

T8

nCS[1]/GPIO[15]

nCS[3]/GPIO[79]

MD[9]

DREQ[0]/GPIO[20]

VCCN

T9

PEXTAL

MA[12]

T10

T11

T12

T13

T14

T15

T16

DREQ[1]/GPIO[19]

GPIO[21]

MD[11]

L2

VSSN

MD[14]

L3

MA[13]

nPWAIT/GPIO[56]

MA[17]

nCS[5]/GPIO[33]

nPWE/GPIO[49]

nPIOR/GPIO[50]

VCCN

L4

MD[20]

L5

MD[2]

P2

MA[19]

L6

VCC

P3

VCCN

L7

DQM[3]

MD[28]

P4

MA[25]

L8

P5

MA[23]

3.2

Package Power Ratings

Table 6.

θ_JAand Maximum Power Ratings

Processor

Max Power

θ_JA

PXA255

^{33 C}°/w

1.4W

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

This section provides the absolute maximum ratings for the processors. Do not exceed these

parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not

guaranteed.

22

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

Table 7. Absolute Maximum Ratings

Symbol

Description

Min

Max

Units

TS

Storage Temperature

-40

125

°C

Offset Voltage between any two VSS pins (VSS, VSSQ,

VSSN)

VSS_O

-0.3

0.3

V

Offset Voltage between any of the following pins:

VCCQ and VCCN

VCC_O

VCC_HV

VCC_LV

Voltage Applied to High Voltage Supplies (VCCQ, VCCN)

VSS-0.3

VSS+4.0

V

Voltage Applied to Low Voltage Supplies (VCC,

PLL_VCC)

VSS+1.65

max of

VCCQ+0.3,

VSS+4.0

VIP

Voltage Applied to non-Supply pins except XTAL pins

VSS-0.3

V

max of

VCC+0.3,

VSS+1.65

Voltage Applied to XTAL pins (PXTAL, PEXTAL, TXTAL,

TEXTAL)

VIP_X

Maximum ESD stress voltage, Human Body Model; Any

pin to any supply pin, either polarity, or Any pin to all non-

supply pins together, either polarity. Three stresses

maximum.

VESD

IEOS

2000

5

V

Maximum DC Input Current (Electrical Overstress) for any

non-supply pin

mA

4.2

Power Consumption Specifications

Power consumption depends on the operating voltage, peripherals enabled, external switching

activity, and external loading.

Specifying maximum power consumption requires all units to be run at their maximum

performance, and at maximum voltage and loading conditions. The maximum power consumption

of the PXA255 processor is calculated using these conditions:

• All peripheral units operating at maximum frequency and size configuration

• All I/O loads maximum (50 pF)

• Core operating at worst-case power scenario (hit rates adjusted for worst power)

• All voltages at maximum of range. Maximum range for the core voltage is set to maintain

compatibility with the PXA250.

• Maximum case temperature

Do not exceed the maximum package power rating or T_casetemperature.

Since few systems operate at maximum loading, performance, and voltage, a more optimal system

design requires more typical power-consumption figures. These figures are important when

considering battery size and optimizing regulator efficiency. Typical systems operate with fewer

modules active and at nominal voltage and load. The typical power consumption for the PXA255

processor is calculated using these conditions:

• SSP, STUART, USB, PWM, Timer, I2S peripherals operating

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

23

Electrical Specifications

• LCD enabled with 320x240x16-bit color

• MMC, AC97, BTUART, FFUART, ICP, I2C peripherals disabled

• I/O loads at nominal (35 pf for all pins)

• Core operating at 98% instruction hit rate, 95% data hit rate, run mode

• All voltages at nominal values

• Nominal case temperature

Table 8 contains power consumption numbers for the PXA255 processor.

Table 8. Power Consumption Specifications for PXA255 processor (Sheet 1 of 2)

Symbol

Description

Typical

Maximum

Units

400 MHz active mode, Maximum: V_cc=1.65V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.3V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

245

28

800

355

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

411

2598

300 MHz active mode, Maximum: V_cc=1.43V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.1V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

185

24

570

345

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

283

2057

200 MHz active mode, Maximum: V_cc=1.32V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.0V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

115

19

340

330

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

178

1637

400 MHz idle mode, Maximum: V_cc=1.65V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.3V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

95

9

460

50

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

121

939

300 MHz idle mode, Maximum: V_cc=1.43V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.1V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

43

9

335

50

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

77

659

200 MHz idle mode, Maximum: V_cc=1.32V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.0V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

33

9

205

50

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

63

451

33 MHz idle mode, Maximum: V_cc=1.32V, V_ccq/V_ccn=3.6V, Temp=100° C

Typical: V_cc=1.0V, V_ccq/V_ccn=3.3V, Temp=Room

24

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

Table 8. Power Consumption Specifications for PXA255 processor (Sheet 2 of 2)

Symbol

Description

V_ccCurrent

Typical

Maximum

Units

I_ccc

I_ccp

15

9

70

50

mA

mW

V_ccqand V_ccnCurrent

Total Power

P_TOTAL

45

272

Sleep mode, Maximum: V_cc=0V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccpV_ccqand V_ccnCurrent 45

75

µA

Fast sleep wakeup mode, Maximum: V_cc=1.0/1.1/1.3V, V_ccq/V_ccn=3.3V, Temp=Room

I_ccc

I_ccp

V_ccCurrent

-

−

V_ccqand V_ccnCurrent

-

4.3

Operating Conditions

This section shows voltage, frequency, and temperature specifications for the processor for four

different ranges (shown in Table 9, “Voltage, Temperature, and Frequency Electrical

Specifications”.) The temperature specification for each range is constant; the frequency range

depends on the operation voltage.

Note: The parameters in Table 9 are preliminary and subject to change.

Table 9. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2)

Symbol

Description

Min

Typical

Max

Units

T_case

Case Temperature - Extended Temp

Case Temperature - Nominal Temp

VSS, VSSN, VSSQ Voltage

VCCQ Voltage

-40

0

-

100

85

°C

V

-

0

VVSS

-0.3

3.0

0.3

3.6

VVCCQ

VVCCN

3.3

V

VCCN Voltage

2.375

2.5/3.3

V

Low Voltage Range

VVCC_L

VCC, PLL_VCC Voltage, Low Range

.95

1.00

1.1

1.155

118

V

fTURBO_L

Turbo Mode Frequency, Low Range

99.5

MHz

External Synchronous Memory

Frequency, Low Range

fSDRAM_L

50

99.5

MHz

Medium Voltage Range

VVCC_M

VCC, PLL_VCC Voltage, Mid Range

.95

1.32

V

fTURBO_M

Turbo Mode Frequency, Mid Range

99.5

199.1

MHz

External Synchronous Memory

Frequency, Mid Range

fSDRAM_M

50

99.5

MHz

High Voltage Range

VVCC_H

VCC, PLL_VCC Voltage, High Range

1.045

99.5

1.43

V

fTURBO_H

Turbo Mode Frequency, High Range

298.7

MHz

External Synchronous Memory

Frequency, High Range

fSDRAM_H

50

99.5

MHz

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

25

Electrical Specifications

Table 9. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2)

Symbol

Description

Min

Typical

Max

Units

Peak Voltage Range

VVCC_P

VCC, PLL_VCC Voltage, Peak Range

Turbo Mode Frequency, Peak Range

1.235

99.5

1.30

1.65

V

fTURBO_P

398.2

MHz

External Synchronous Memory

Frequency, Peak Range

fSDRAM_P

50

99.5

MHz

4.4

Targeted DC Specifications

The DC characteristics for each pin include input-sense levels and output-drive levels and currents.

These parameters can be used to determine maximum DC loading, and also to determine maximum

transition times for a given load. Table 10, “Standard Input, Output, and I/O Pin DC Operating

Conditions” shows the DC operating conditions for the high- and low-strength input, output, and

I/O pins. All DC specification values are valid for the entire temperature range of the device.

Table 10. Standard Input, Output, and I/O Pin DC Operating Conditions

Symbol

Description

Min

Typical

Max

Units

Input DC Operating Conditions

Input High Voltage, all standard input and

I/O pins

VIH

VIL

IIN

0.8*VCCQ

VSS

VCCQ

0.2*VCCQ

10

V

Input Low Voltage, all standard input and

I/O pins

Input Leakage, all standard input and IO

pins

µA

Output DC Operating Conditions

Output High Voltage, all standard output

and I/O pins

VOH

VOL

VCCQ-0.1

VCCQ

V

Output Low Voltage, all standard output

and I/O pins

VSS

-10

-3

VSS+0.4

V

Output High Current, all standard, high-

strength output and I/O pins (VO=VOH)

IOH_H

IOH_L

IOL_H

IOL_L

mA

Output High Current, all standard, low-

strength output and I/O pins (VO=VOH)

Output Low Current, all standard, high-

strength output and I/O pins (VO=VOH)

10

3

Output Low Current, all standard, low-

strength output and I/O pins (VO=VOH)

26

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

Table 11. Standard Input, Output, I/O Pin DC Operating Conditions for 2.5-V Memory

Symbol

Description

Min

Typ

Max

Units

Input DC Operating Conditions

Input High Voltage, all standard input and

I/O pins

Vih

Vil

Iin

0.9*VCCN

VCCN

0.1*VCCN

10

V

Input Low Voltage, all standard input and

I/O pins

VSS

-

Input Leakage, all standard input and I/O

pins

uA

Output DC Operating Conditions

Output High Voltage, all standard output

and I/O pins

Voh

Vol

VCCN-0.3

VSS

VCCN

V

Output Low Voltage, all standard output

and I/O pins

VSS+0.3

4.5

Targeted AC Specifications

All the non-analog input, output, and I/O pins on the processor can be divided into one of two

categories:

1. High Strength Input, Output, and I/O pins:

• nCS[5:1] (GP 33, 80, 79, 78, 15 respectively), nCS[0]

• MD[31:0], MA[25:0]

• DQM[3:0]

• nOE, nWE, nSDRAS, nSDCAS, nSDCS[3:0]

• SDCLK[2:0], SDCKE[1:0]

• RDnWR, RDY (GP[18])

• nPWE, nPOE pins (GP[49:48])

• MMCLK (GP[53]), MMCMD, MMDAT

• TDO

• nACRESET

2. Low Strength Input, Output, and I/O pins - all remaining non-supply pins

A pin’s AC characteristics include input and output capacitance, which determine loading for

external drivers or other load analysis. The AC characteristics also include a de-rating factor, which

indicates how much faster or slower the AC timings get with different loads. Table 12, “Standard

Input, Output, and I/O Pin AC Operating Conditions” shows the AC operating conditions for the

high- and low-strength input, output, and I/O pins. All AC specification values are valid for the

entire temperature range of the device.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

27

Electrical Specifications

Table 12. Standard Input, Output, and I/O Pin AC Operating Conditions

Symbol

Description

Min

Typical

Max

Units

Input capacitance, all standard input and

IO pins

CIN

10

pF

Output capacitance, all standard high-

strength output and IO pins

COUT_H

tdF_H

25¹

50¹

pF

Output de-rating, falling edge on all

standard, high-strength output and I/O

pins, from 50pF load.

ns/pF

Output de-rating, rising edge on all

standard, high-strength output and I/O

pins, from 50pF load.

tdR_H

ns/pF

NOTE: ¹AC specifications guaranteed for loads in this range. All testing is done at 50pF

4.6

Oscillator Electrical Specifications

The processor contains two oscillators, each for a specific crystal: a 32.768-kHz oscillator and a

3.6864-MHz oscillator. When choosing a crystal, match the crystal parameters as closely as

possible.

4.6.1

32.768-kHz Oscillator Specifications

The 32.768-kHz oscillator is connected between the TXTAL (amplifier input) and TEXTAL

(amplified output). Table 13, “32.768-kHz Oscillator Specifications” shows the 32.768-kHz

specifications.

Table 13. 32.768-kHz Oscillator Specifications

Symbol

Description

Min

Typical

Max

Units

Crystal Specifications - Typical is FOX NC38

F_XT

ESR

P

Crystal Frequency, TXTAL/TEXTAL

Equivalent series resistance, TXTAL/TEXTAL

Drive Level

—

6

32.768

—

65

1

kHz

kΩ

—

uW

Amplifier Specifications

VIH_X

VIL_X

IIN_XT

Input High Voltage, TXTAL

0.8*VCC

VSS

VCC

V

Input Low Voltage, TXTAL

Input Leakage, TXTAL

0.2*VCC

1

µA

pF

s

CIN_XT Input Capacitance, TXTAL/TEXTAL

tS_XT Stabilization Time

Board Specifications

18

-

25

10

2

RP_XT

CP_XT

Parasitic Resistance, TXTAL/TEXTAL to any node

Parasitic Capacitance, TXTAL/TEXTAL, total

20

MΩ

pF

5

COP_XT Parasitic Shunt Capacitance, TXTAL to TEXTAL

0.4

pF

28

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

To drive the 32.768-kHz crystal pins from an external source

• Drive the TEXTAL pin with a digital signal that has a low level near 0 volts and a high level

near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew

rate is 1 volt per 1 µs. The maximum current sourced by the external clock source when the

clock is at its maximum positive voltage should be approximately 1 mA.

• Float the TXTAL pin or drive it complementary to the TEXTAL pin, with the same voltage

level, slew rate, and input current restrictions.

4.6.2

3.6864 MHz Oscillator Specifications

The 3.6864-MHz oscillator is connected between the PXTAL (amplifier input) and PEXTAL

(amplified output). Table 14 shows the 3.6864-MHz specifications.

Table 14. 3.6864-MHz Oscillator Specifications

Symbol

Description

Min

Typical

Max

Units

Crystal Specifications - Typical is FOX HC49S

F_XP

ESR

P

Crystal Frequency, PXTAL/PEXTAL

Equivalent series resistance, PXTAL/PEXTAL

Drive Level

—

50

—

3.6864

—

MHz

Ω

-

300

100

—

uW

Amplifier Specifications

VIH_X

VIL_X

Input High Voltage, PXTAL

0.8*VCC

VSS

VCC

0.2*VCC

10

V

Input Low Voltage, PXTAL

Input Leakage, PXTAL

IIN_XP

CIN_XP

tS_XP

µA

pF

ms

Input Capacitance, PXTAL/PEXTAL

Stabilization Time

40

50

17.8

20

67.8

Board Specifications

RP_XP

CP_XP

Parasitic Resistance, PXTAL/PEXTAL to any node

Parasitic Capacitance, PXTAL/PEXTAL, total

MΩ

pF

5

COP_XP Parasitic Shunt Capacitance, PXTAL to PEXTAL

0.4

pF

To drive the 3.6864-MHz crystal pins from an external source

• Drive the PEXTAL pin with a digital signal with a low level near 0 volts and a high level near

VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is

1 volt / 100 ns. The maximum current sourced by the external clock source when the clock is

at its maximum positive voltage should be approximately 1 mA.

• Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage

level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility

will be introduced in the system; therefore, it is not recommended.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

29

Electrical Specifications

Note: The minimum duty cycle for an external signal driven into PEXTAL is 40/60.

4.7

Reset and Power AC Timing Specifications

The processor asserts the nRESET_OUT pin in one of several different modes:

• Power on

• Hardware reset

• Watchdog reset

• GPIO reset

• Sleep mode

The following sections provide the timing and specifications for the entry and exit of these modes.

4.7.1

Power-On Timing

The external voltage regulator and other power-on devices must provide the processor with a

specific sequence of power and resets to ensure proper operation. Figure 3, “Power-On Reset

Timing” on page 31, shows this sequence and is detailed in Table 15, “Power-On Timing

Specifications” on page 31.

On the processor, it is important that the power supplies be powered up in a certain order to avoid

high current situations. The required order is:

1. VCCQ

2. VCCN

3. VCC and PLL_VCC

On the processor, it is important that the VCCQ power supply be powered up before or at the same

time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up

anytime within the specification shown in Figure 3 and Table 15.

30

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

Note: If hardware reset is entered during sleep mode, follow the proper power-supply stabilization times

indicated in Figure 3 and nRESET timing requirements indicated in Table 15.

Figure 3. Power-On Reset Timing

t_{R_VCCQ}

t_{R_VCCN}

VCCQ, PWR_EN

t_{D_VCCN}

t_{R_VCC}

VCCN

t_{D_VCC}

VCC

t_{D_NTRST}

nTRST

t_{D_JTAG}

JTAG PINS

t_{D_NRESET}

nRESET

t_{D_OUT}

nRESET_OUT

NOTES:

1. nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the

processor enters sleep mode.

2. The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ. The

use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system’s

power management requirements. VCCN and VCC are not dependant on the PWR_EN signal being

asserted.

Table 15. Power-On Timing Specifications

Symbol

Description

Min

Typical

Max

Units

tR_VCCQ

tR_VCCN

tR_VCC

VCCQ rise / stabilization time

0.01

—

100

10

ms

VCCN rise / stabilization time

VCC, PLL_VCC rise / stabilization time

Delay between VCCQ applied and

VCCN applied

tD_VCCN

tD_VCC

0

—

ms

Delay from VCCN applied and VCC,

PLL_VCC applied

-10

10

Delay between VCC, PLL_VCC stable

and nTRST de-asserted

tD_NTRST

Delay between nTRST de-asserted and

JTAG pins active, with nRESET

asserted

tD_JTAG

0.03

—

ms

Delay between VCC, PLL_VCC stable

and nRESET de-asserted

tD_NRESET

tD_OUT

10

—

ms

ns

Delay between nRESET de-asserted

and nRESET_OUT de--asserted

18.1

400

18.2

420

Delay between nRESET_OUT

deasserted and nCS0 asserted

tD_NCS0

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

31

Electrical Specifications

4.7.2

Hardware Reset Timing

The timing sequences shown in hardware reset timing for hardware reset assumes stable power

supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings

indicated in Section 4.7.1, “Power-On Timing” on page 30.

Figure 4. Hardware Reset Timing

t

DHW_NRESET

nRESET

t

DHW_OUT

nRESET_OUT

t

DHW_OUT_A

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is

or the Cotulla will enter Sleep Mode

de-asserted or the PXA255 processor enters sleep mode.

Table 16. Hardware Reset Timing Specifications

Symbol

Description

Min

Typical

Max

Units

tDHW_NRESET Minimum assertion time of nRESET

0.001

ms

Delay between nRESET asserted and

tDHW_OUT_A

0

0.001

18.2

420

ms

ns

nRESET_OUT asserted

Delay between nRESET de-asserted and

tDHW_OUT

18.1

400

nRESET_OUT de-asserted

Delay between nReset_Out de-asserted

and nCS0 asserted

tDHW_NCS0

—

4.7.3

4.7.4

Watchdog Reset Timing

Watchdog reset is an internally generated reset and therefore has no external pin dependencies. The

nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for t_{DHW_OUT}

Refer to Figure 4, “Hardware Reset Timing” on page 32.

.

GPIO Reset Timing

GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as

the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies

based on the frequency of clock selected, and if the clocks and power manager is in the frequency

change sequence when GPIO reset is asserted (see Section 4.6.1, “32.768-kHz Oscillator

Specifications” on page 28.) Figure 5, “GPIO Reset Timing” on page 33 shows the possible timing

of GPIO reset.

32

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

Figure 5. GPIO Reset Timing

t

A_GP[1]

GP[1]

nRESET_OUT

t

DHW_OUT

t

DHW_OUT_A

Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is

deasserted or the application processor will enter Sleep Mode

Table 17. GPIO Reset Timing Specifications

Symbol

Description

Min

Typical

Max

Units

Minimum assert time of GP[1]¹in

3.6864MHz input clock cycles

tA_GP[1]

4

cycles

Delay between GP[1] asserted and

tDHW_OUT_A nRESET_OUT asserted in 3.6864 MHz

input clock cycles

3

8

cycles

Delay between nRESET_OUT asserted

tDHW_OUT

and nRESET_OUT de-asserted, run or

1.28

6.5

µs

turbo mode²

Delay between nRESET_OUT asserted

tDHW_OUT_F and nRESET_OUT de-asserted, during

1.28

360

390

µs

frequency change sequence³

Delay between nReset_Out de-asserted

tDHW_NCS0

150.69

—

ns

and nCS0 asserted

NOTES:

1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should

check the state of GP[1] before configuring as a reset to ensure no spurious reset is generated.

2. Time is 512*N processor clock cycles plus up to 4 cycles of the 3.6864-MHz input clock.

3. Time during the frequency change sequence depends on the state of the PLL lock detector at the

assertion of GPIO reset. The lock detector has a maximum time of 350µs plus synchronization.

4.7.5

Sleep Mode Timing

Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The

sequence indicated in Figure 6, “Sleep Mode Timing” on page 34 and detailed in Figure 18, “Sleep

Mode Timing Specifications” on page 34 is the required timing parameters for sleep mode.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

33

Electrical Specifications

Figure 6. Sleep Mode Timing

t

A_GP[x]

GP[x]

PWR_EN

t

D_PWR_R

D_PWR_F

t

DSM_VCC

VCC

t

D_F

A UL T

nVDD_FAULT

nRESET_OUT

t

DSM_OUT

Note: nBATT_FAULT must be high or Cotulla will not exit Sleep Mode

Note: nBATT_FAULT must be high or the PXA255 processor

will not exit sleep mode.

Table 18. Sleep Mode Timing Specifications

Symbol

Description

Min

Typical

Max

Units

Assert time of GPIO wake-up source

(x=[15:0])

tA_GP[x}

91.6

—

µs

Delay from nRESET_OUT asserted to

PWR_EN de-asserted

tD_PWR_F

tD_PWR_R

tDSM_VCC

tD_FAULT

61

—

91.6

122.1

10

µs

Delay between GP[x] asserted to

PWR_EN asserted

30.5

Delay between PWR_EN asserted and

VCC stable

ms

µs

Delay between PWR_EN asserted and

nVDD_FAULT de-asserted

10

Delay between PWR_EN asserted and

nRESET_OUT de-asserted, OPDE set

tDSM_OUT

tDSM_OUT_F

28.0

—

28.5

650

Delay between PWR_EN asserted and

nRESET_OUT de-asserted, FWAKE set

Delay between PWR_EN asserted and

tDSM_OUT_O nRESET_OUT de-asserted, OPDE

10.35

—

10.5

332

ms

ns

clear

Delay between nReset_Out de-asserted

and nCS0 asserted

t_{DSM_NCS0}

180.84

NOTE: For the parameter t_{DSM_VCC}, VCC refers to the VCC supply internal to the processor. The internal

VCC regulator must be stable within the stated maximum for the processor to function correctly.

Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of

the internal regulator and must be taken into account when designing the system.

34

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

4.8

Memory Bus and PCMCIA AC Specifications

This section provides the timing information for these types of memory:

• SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 19, “SRAM /

ROM / Flash / Synchronous Fast Flash AC Specifications” on page 35)

• Variable latency I/O (Table 20, “Variable Latency I/O Interface AC Specifications” on

page 35)

• Card interface (PCMCIA or Compact Flash) (Table 21, “Card Interface (PCMCIA or Compact

Flash) AC Specifications” on page 36)

• Synchronous memories (Table 22, “Synchronous Memory Interface AC Specifications 1” on

page 36)

Table 19. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications

Symbol

Description

MEMCLKs

tromAS

MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted

1

MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) de-

asserted

tromAH

1

tromASW MA(25:0) setup to nWE asserted

3

1

2

1

2

1

2

tromAHW MA(25:0) hold after nWE de-asserted

tromCES

tromCEH

tromDS

nCS setup to nWE asserted

nCS hold after nWE de-asserted

MD(31:0), DQM(3:0) write data setup to nWE asserted

tromDSWH MD(31:0), DQM(3:0) write data setup to nWE de-asserted

tromDH MD(31:0), DQM(3:0) write data hold after nWE de-asserted

tromNWE nWE high time between beats of write data

Table 20. Variable Latency I/O Interface AC Specifications

Symbol

Description

MEMCLKs

tvlioAS

MA(25:0) setubp to nCS asserted

1

2

1

tvlioASRW MA(25:0) setup to nOE or nPWE asserted

tvlioAH

tvlioCES

tvlioCEH

MA(25:0) hold after nOE or nPWE de-asserted

nCS setup to nOE or nPWE asserted

nCS hold after nOE or nPWE de-asserted

tvlioDSW MD(31:0), DQM(3:0) write data setup to nPWE asserted

MD(31:0), DQM(3:0) write data setup to nPWE de-

tvlioDSWH

asserted

2

tvlioDHW MD(31:0), DQM(3:0) hold after nPWE de-asserted

1

0

2

tvlioDHR

MD(31:0) read data hold after nOE de-asserted

tvlioRDYH RDY hold after nOE, nPWE de-asserted

tvlioNPWE nPWE, nOE high time between beats of write or read data

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

35

Electrical Specifications

Table 21. Card Interface (PCMCIA or Compact Flash) AC Specifications

Symbol

Description

MEMCLKs

MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or

nPIOR asserted

tcardAS

2

MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or

nPIOR de-asserted

tcardAH

2

tcardDS

tcardDH

MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted

MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted

nPWE, nPOE, nPIOW, or nPIOR command assertion

2

tcardCMD

NOTE: These numbers are minimums. They can be much longer based on the programmable card

interface timing registers.

Table 22. Synchronous Memory Interface AC Specifications ¹

Units,

Notes

Symbol

Description

MIN

MAX

SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous)

tsynCLK

tsynCMD

tsynRCD

tsynCAS

SDCLK period

10

1

20

ns, 2

sdclk

nSDCAS, nSDRAS, nWE, nSDCS assert time

nSDRAS to nSDCAS assert time

1

nSDCAS to nSDCAS assert time

2

MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,

tsynSDOS nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0)

rise

3.8

3.6

ns, 3

MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,

tsynSDOH nWE, nOE, SDCKE(1:0), RDnWR output hold time from

SDCLK(2:0) rise

tsynSDIS

tsynDIH

MD(31:0) read data input setup time from SDCLK(2:0) rise

MD(31:0) read data input hold time from SDCLK(2:0) rise

0.5

1.5

ns

Fast Flash (Synchronous READS only)

tffCLK

tffAS

SDCLK period

15

0.5

1

20

ns, 4

sdclk

MA(25:0) setup to nSDCAS (as nADV) asserted

nCS setup to nSDCAS (as nADV) asserted

nSDCAS (as nADV) pulse width

tffCES

tffADV

tffOS

nSDCAS (as nADV) de-assertion to nOE assertion

nOE deassertion to nCS de-assertion

3

tffCEH

NOTES:

4

1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.

2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of

the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest.

3. This number represents 1/2 SDCLK period.

4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of

the 132.7 MHz MEMCLK at its fastest.

36

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

4.9

Peripheral Module AC Specifications

This section describes the AC specifications for the LCD and SSP peripheral units.

4.9.1

LCD Module AC Timing

Figure 7 describes the LCD timing parameters. The LCD pin timing specifications are referenced

to the pixel clock (L_PCLK). Values for the parameters are given in Table 23.

Figure 7. LCD AC Timing Definitions

L_PCLK

T

pclkdv

L_LDD[7:0]

(rise)

T

pclkdv

L_LDD[7:0]

(fall)

T

pclklv

L_LCLK

L_BIAS

L_FCLK

T

pclkbv

T

pclkfv

A4775-01

Table 23. LCD AC Timing Specifications

Symbol

Description

Min

Max

Units

Notes

Tpclkdv L_PCLK rise/fall to L_LDD<7:0>

driven valid

Tpclkdv

0

3.5

ns

1

Tpclklv

Tpclkfv

Tpclkbv

L_PCLK fall to L_LCLK driven valid

L_PCLK fall to L_FCLK driven valid

L_PCLK rise to L_BIAS driven valid

-0.5

2.0

12

ns

2

5.524

NOTES:

1. Program the LCD data pins to be driven on either the rising or falling edge of the pixel clock (L_PCLK).

2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time,

they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin.

4.9.2

SSP Module AC Timing

Figure 8, “SSP AC Timing Definitions” on page 38 describes the SSP timing parameters. The SSP

pin timing specifications are referenced to SCLK_C. Values for the parameters are given in

Table 24, “SSP AC Timing Specifications” on page 38.

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

37

Electrical Specifications

Figure 8. SSP AC Timing Definitions

SCLK_C

SFRM_C

TXD_C

T

sfmv

T

sfmv

T

rxdh

rxds

RXD_C

A4774-01

Table 24. SSP AC Timing Specifications

Symbol

Description

SCLK_C rise to SFRM_C driven valid

Min

Max

Units

Notes

Tsfmv

Trxds

21

ns

RXD_C valid to SCLK_C fall (input setup)

11

0

SCLK_C fall to RXD_C invalid (input

hold)

Trxdh

Tsfmv

ns

SCLK_C rise to TXD_C valid

22

4.9.3

Boundary Scan Test Signal Timings

Table 25, “Boundary Scan Test Signal Timing” shows the boundary scan test signal timing.

Table 25. Boundary Scan Test Signal Timing (Sheet 1 of 2)

Symbol

Parameter

TCK frequency

Min

Max

Units

Notes

TBSF

0.0

33.33

MHz

ns

TBSCH TCK high time

15.0

Measured at 1.5 V

TBSCL TCK low time

Measured at 1.5 V

0.8 V to 2.0 V

TBSCR TCK rise time

5.0

TBSCF TCK fall time

2.0 V to 0.8 V

TBSIS1 Input setup to TCK TDI, TMS

TBSIH1 Input hold from TCK TDI, TMS

TBSIS2 Input setup to TCK nTRST

TBSIH2 Input hold from TCK nTRST

TBSOV1 TDO valid delay

4.0

6.0

25.0

3.0

1.5

1.1

1.5

6.9

5.4

6.9

Relative to falling edge of TCK

TOF1

TDO float delay

TOV12 All outputs (non-test) valid delay

38

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

Electrical Specifications

Table 25. Boundary Scan Test Signal Timing (Sheet 2 of 2)

Symbol

Parameter

Min

Max

Units

Notes

TOF2

All outputs (non-test) float delay

1.1

5.4

ns

Relative to falling edge of TCK

Input setup to TCK all inputs

(non-test)

TIS10

TIH8

4.0

6.0

ns

Input hold from TCK all inputs

(non-test)

4.10

AC Test Conditions

The AC specifications in Section 4.5, “Targeted AC Specifications” on page 27 are tested with a

50 pF load indicated in Figure 9.

Figure 9. AC Test Load

Output Ball

C = 50pF

L

C

L

Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification

39

厂商	型号	描述	页数
ETC	PXA.M0.5GG.NB	[ CONN RCPT FMALE 5POS GOLD SOLDER ]	76 页
MARVELL	PXA1088	WCDMA / TD -SCDMA通信处理器[ WCDMA/TD-SCDMA Communication Processor ]	2 页
MARVELL	PXA168	高性能，高集成度处理器可扩展到1.2 GHz的对成本敏感的，智能消费类和嵌入式设备[ High Performance, Highly Integrated Processor Scalable to 1.2 GHz for Cost-Sensitive, Intelligent Consumer and Embedded Devices ]	2 页
INTEL	PXA210	英特尔-R PXA250和PXA210应用处理器[ Intel-R PXA250 and PXA210 Applications Processors ]	46 页
INTEL	PXA250	英特尔-R PXA250和PXA210应用处理器[ Intel-R PXA250 and PXA210 Applications Processors ]	46 页
INTEL	PXA270	电气，机械和热规格[ Electrical, Mechanical, and Thermal Specification ]	126 页
ACTEL	PXA270	为PXA270平台的存储解决方案[ Storage solution for PXA270 platform ]	2 页
ACTEL	PXA300	为Marvell公司的PXA300 / 310平台存储解决方案[ Storage Solution for Marvell’s PXA300/310 Platform ]	2 页
MARVELL	PXA300	可扩展性能高达624兆赫的高性价比和高能效的智能手机，嵌入式解决方案，以及手持设备[ Scalable Performance up to 624 MHz for Cost-Effective and Power-Efficient Smartphones, Embedded Solutions, and Handheld Devices ]	4 页
ACTEL	PXA310	为Marvell公司的PXA300 / 310平台存储解决方案[ Storage Solution for Marvell’s PXA300/310 Platform ]	2 页