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VV5402

型号:

VV5402

描述:

VV5402单片传感器[ VV5402 Monolithic Sensor ]

品牌:

ETC[ ETC ]

页数:

16 页

PDF大小:

161 K

VISION VV5402 Monolithic Sensor  
Multi-standard Monochrome CMOS Image Sensor.  
PRODUCT DATASHEET  
DISTINCTIVE CHARACTERISTICS  
Complete Video Camera on a single chip  
EIA/CCIR standard compatible  
Low light operation to 0.5 lux  
Automatic Exposure and Gain Control  
Automatic Black Level Calibration  
Linear or Gamma corrected output option  
Industry standard 48 pin LCC package  
Low power operation (250mW Typical)  
Integral 75driver  
Control options pin selectable for ease of use  
GENERAL DESCRIPTION  
The VV5402 is a highly-integrated VLSI  
camera device based on VISION’s unique  
CMOS sensor technology. It is suitable for  
applications requiring a composite video  
output with minimum external circuitry.  
level allow use of a single fixed-aperture lens  
over a wide range of operating conditions.  
Normal and Backlit modes further enhance  
difficult scene types.  
All major control functions are pin selectable  
giving maximum flexibility with ease of use. The  
VV5402 offers a complete camera system with  
only a few external components.  
The device incorporates a 388 x 295 pixel  
image sensor and all the necessary support  
circuits to generate fully formatted composite  
video into a 75load.  
Automatic control of exposure, gain and black  
BLOCK DIAGRAM  
AGC  
AEC  
RESETB  
LIN  
BKLIT  
CCIR  
Pixel Format  
384 x 287 (CCIR)  
320 x 243 (EIA)  
DIGITAL  
CONTROL  
LOGIC.  
VERTICAL  
SHIFT  
REGISTER  
PHOTO DIODE ARRAY  
Pixel Size  
Array Size  
Min. illumination  
S/N  
12µm x 12µm  
4.66mm x 3.54mm  
0.5 lux (Standard Clock)  
Typically 52dB  
VRT  
Vbloom  
VOFF  
VBG  
EBCK  
EVWT  
ANALOG  
VOLTAGE  
REFS.  
COLUMN SENSE AMPLIFIERS  
SAMPLE & HOLD  
5V  
2V7  
AVO  
Exposure control Automatic (to 146000:1)  
CKOUT  
CKIN  
VIDEO  
BUFFER  
CLOCK  
CIRCUIT  
Gain Control  
Power Supply  
Power  
Automatic (to +20dB)  
5v ±5%  
SIN  
< 300 mW  
VIDEO  
AMP  
o
o
HORIZONTAL SHIFT REGISTER  
Temperature  
0 C - 40 C  
cd27031c.fm  
1
VISION V V 5402 Sensor  
Contents  
page  
3
5
Main Features  
Specifications  
Pin List  
9
Video Standards  
Example Support Circuit  
12  
15  
2
cd27031c.fm  
Main Features  
Automatic Gain Control (AGC)  
Video Output  
The VV5402 automatically increases the  
system gain of its output stage if with the  
current gain setting and maximum exposure  
the image is too dark. Gain can be varied from  
x1 to x16 in times-two steps, giving five  
different gain settings.  
The VV5402 delivers a fully-formatted  
composite monochrome video signal. Stand-  
ards options include EIA (320 x 244) and  
CCIR (384 x 287). On chip signal conditioning  
allows user-selection of linear or gamma-  
corrected output.  
If the scene is too dark and the integration  
period has almost reached its maximum  
value, the gain value is incremented by one  
step (times two). In the same frame period the  
exposure value is divided by two, halving the  
integration period. The exposure controller  
then increases the exposure value as neces-  
sary. Similarly if the image is too bright and  
the integration period is short then gain will be  
reduced by one step (divide by two) and the  
exposure value will be doubled. The exposure  
controller can then adjust the exposure value  
as necessary to provide a correctly exposed  
image.  
The integrated 75driver eliminates the need  
for additional active components to drive  
standard loads, including double terminated  
lines.  
Automatic Exposure and Gain Control  
Automatic exposure and gain control are  
enabled with AEC=1 (pin 21) and AGC=1  
(pin22). However, If AEC is inhibited by pin  
21, AGC is also inhibited. Inhibiting AEC or  
AGC by taking pin 21 or 22 low freezes the  
current value(s) for these.  
Automatic Exposure Control (AEC)  
Backlit Mode  
The VV5402 controls exposure over a range  
of 99,000:1 in EIA mode and 146,000:1 in  
CCIR mode, and operates at illumination  
levels as low as 0.5 lux at standard clock  
frequencies. (Thesystem clock frequency can  
be reduced to provide increased sensitivity.)  
The VV5402 can be configured to operate in  
two auto-exposure modes, selected by the  
BKLIT pin (pin28) state. The default mode  
(BKLIT = 0) provides exposure control for  
normally illuminated scenes. For scenes  
where a bright background can cause the  
foreground subject to be severely under  
exposed, the ‘Backlit’ mode (BKLIT = 1) offers  
superior performance.  
Automatic exposure control is achieved by  
varying pixel current integration time  
according to the average light level on the  
sensor. This integration time can vary from  
one pixel clock period to one frame period.  
‘Backlit Mode’ (BKLIT=1) operates by using a  
higher threshold level for the exposure control  
comparator over the central area of an image,  
which is therefore exposed for longer and so  
enhanced. The area in which the higher  
comparator threshold is used when BKLIT=1  
is illustrated below:  
Pixels above a threshold white level are  
counted every frame, and the number at the  
end of the frame defines the image exposure.  
If the image is other than correctly exposed, a  
new value for integration time is calculated  
and applied for the next frame. Corrections  
are either ±1/8 or ±1/64, depending upon the  
degree of over or under exposure.  
09/04/97  
3
VISION V V 5402 Sensor  
Backlit Mode Threshold Area:  
Normal operation (BKLIT=0)  
Higher threshold area (BKLIT=1)  
10%  
30%  
80%  
25%  
80%  
90%  
25%  
75%  
Exposure  
control area  
Visible  
image  
Higher  
Threshold  
Note: The threshold level used for the central area is a preset mutiple of the normal mode reference  
level, and is not alterable.  
Spectral Response  
1.0  
0.8  
0.6  
0.4  
0.2  
0
Wavelength nm  
4
cd27031c.fm  
Specifications  
SPECIFICATIONS  
Package Details  
1.52 TYP  
0.51  
TYP  
13.7  
Glass Lid  
0.55  
0.86  
0.5  
Die  
Base  
0.53  
Viewed from side  
The optical array is centred within the  
package to a tolerance of ± 0.2 mm, and  
rotated no more than ± 0.5o  
2.16  
PIN 1  
Tolerances on package dimensions ±10%  
Glass lid placement is controlled so that no  
package overhang exists.  
1.016 PITCH TYP  
All dimensions in millimetres  
Viewed from below  
Absolute Maximum Ratings  
Parameter  
Value  
Supply Voltage  
-0.5 to +7.0 volts  
Voltage on other input pins  
Temperature under bias  
Storage Temperature  
-0.5 to V + 0.5 volts  
DD  
o
o
-15 C to 85 C  
o
o
-30 C to 125 C  
Maximum DC TTL output Current Magnitude 10mA (per o/p, one at a time, 1sec. duration)  
Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute  
maximum ratings for extended periods may reduce reliability. Functionality at or above these  
conditions is not implied.  
09/04/97  
5
VISION V V 5402 Sensor  
DC Operating Conditions  
Symbol  
Parameter  
Min.  
4.75  
Typ.  
5.0  
Max.  
5.25  
Units  
Volts  
Notes  
V
Operating supply voltage  
Input Voltage Logic “1”  
DD  
IH  
IL  
V
2.4  
-0.5  
0
V
+0.5 Volts  
Volts  
DD  
V
Input Voltage Logic “0”  
0.8  
70  
o
T
Ambient Operating Temperature  
C
Still air  
A
AC Operating Conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Units Notes  
EIA Crystal frequency  
CCIR Crystal frequency  
12.0000  
14.7456  
MHz  
MHz  
1
CKIN  
CKIN  
1
CKIN  
1. Pixel Clock =  
/
2
Electrical Characteristics  
Symbol  
Parameter  
Min.  
Typ.  
Max. Units  
Notes  
10  
25  
mA  
mA  
1
1
1
IDCC  
IADD  
IDD  
Digital supply current  
Analog supply current  
Overall supply current  
Internal voltage reference  
Internal bandgap reference  
Output Voltage Logic “1”  
Output Voltage Logic “0”  
Input Leakage current  
35  
mA  
V
V
V
V
2.700  
1.22  
Volts  
Volts  
Volts  
REF2V7  
BG  
2.4  
-1  
I
I
= 2mA  
OH  
OH  
OL  
0.6  
1
Volts  
= -2mA  
OL  
µA  
IILK  
VIH on  
input  
µA  
VIL on  
input  
Typical conditions, VDD = 5.0 V, TA = 27oC  
1. Digital and Analogue outputs unloaded - add output current.  
6
cd27031c.fm  
Specifications  
Operating Characteristics  
Parameter  
min.  
typ.  
50  
max.  
units  
Note  
Dark Current Signal  
mV/Sec  
Modal pixel voltage due to photodiode leak-  
age under zero illumination with Gain=1  
(V  
= (V - V )/(t1-t2), averaged over two  
dark  
t1 t2  
different frames)  
V /Lux·10ms, where Lux gives 50% satu-  
Ave  
Sensitivity  
6
V/Lux·Sec  
ration with Gain=1 and Exposure=10ms  
Min. Illumination  
Shading  
0.5  
Lux  
%
Standard CCIR clock  
TBA  
Variance of V  
over eight equal blocks at  
ave  
50% saturation level illumination  
Random Noise  
Smear  
-52  
dB  
%
RMS variance of all pixels, at 66% satura-  
tion, over four frames  
TBA  
Ratio of V  
of the area outside a rectangle  
ave  
25 lines high illuminated at 500xV  
level  
50%  
to V  
of the rectangle  
Ave  
Flicker  
Lag  
TBA  
TBA  
%
%
Variation of V of one line from field to field  
at 66% saturation level illumination  
ave  
Average residual signal with no illumination  
in the field following one field of 66% sat.  
illumination  
Blooming  
TBA  
Ratio of spot illumination level that produces  
0.1xV output from immediately around the  
sat  
spot to the V spot illumination level (pin-  
sat  
hole target)  
Note: Devices are normaly not 100% tested for the above characterisation parameters, other than  
Dark Current Signal (see Blemish Specification below).  
All voltage (VA, Vave, Vsat, Vxx%) measurements are referenced to the black level, V  
, and spot blem-  
black  
ishes are excluded (see Blemish Specification below). V  
refers to the output that is xx% of saturation,  
xx%  
that is peak white.  
Test Conditions  
o
Illumination Colour Temp.  
Clock Frequency  
Exposure  
3200 K  
Std. CCIR  
Maximum  
x1  
The sensor is tested using the example support  
circuit illustrated later in this document. Standard  
imaging conditions used for optical tests employ a  
tungsten halogen lamp to uniformly illuminate the  
sensor (to better than 0.5%), or to illuminate  
specific areas. A neutral density filter is used to  
control the level of llumination where required.  
Gain  
Auto. Gain Control (AGC)  
Correction mode  
Off  
Linear  
09/04/97  
7
VISION V V 5402 Sensor  
Blemish Specification  
A Blemish is an area of pixels that produces output significantly different from its surrounding  
pixels for the same illumination level. The definition of a Blemish Pixel varies according to testing  
conditions as follows:  
Test  
Exposure  
Illumination  
Blemish Pixel output definition  
1 - Black Frame  
Minimum  
Black  
Differing more than ± 100mV. from modal value.  
2 - Dark Current  
Maximum  
Black  
Output more than three times the modal value  
(see Dark Current Signal above).  
3 - Pixel Variation  
Mid range  
66% Sat.  
Differing more than ±35mV from modal value.  
Note: The mode of pixel values must be within  
±70 mV of 66% of V for all devices.  
sat  
Note: Gain is set to Minimum and Correction set to Linear for all tests; measurement of blemishes for  
Test 3 is conducted under standard illumination (see above), set to produce average output of  
66% saturation level.  
The pixel area of the sensor is divided into the following areas to qualify the blemish specification:  
Area A is the central area of the array as defined  
by the box with sides 50% of the linear height  
and 50% of the linear width of the array.  
Area A  
Area C is 10 vertical pixels by 10 horizontal pixels  
around the edge of the array.  
Area B  
Area B is the remaining area of the array.  
Area C  
The blemish specification is then defined as follows:  
Image Area Max. No. of Blemishes  
Notes  
Area A  
0
This is the most critical image area  
4
Unconnected single pixels  
Area B  
Area C  
1
Of up to four connected pixels (2x2 max.)  
Any number  
Blemishes in this area are not significant, but the device  
shall, however, have no row or column (>50% of row or  
column) faults in any area.  
8
cd27031c.fm  
Pin List  
Pinout Diagram  
30 29 28 27 26 25 24 23 22 21 20 19  
31  
VSS  
18  
17  
SCE  
SIN  
DNC 32  
33  
DNC  
VDD  
DNC  
16 SAB1  
34  
35  
15  
VGND  
AVO  
14  
13  
DNC 36  
VVDD  
48 Pin LCC  
Viewed from top of package  
37  
38  
39  
ODD  
SCI  
12  
11  
10  
DNC  
DNC  
DNC  
AVSS  
EVWT  
EBCK  
DNC  
VDD  
VSS  
40  
41  
9
8
42  
7
AVDD  
43 44 45 46 47 48  
1
2
3
4
5
6
Pins Marked “DNC” must be left ‘floating’.  
PIN LIST  
Pin  
Name  
Type  
Description  
POWER SUPPLIES  
1
AVCC  
AVDD  
AVSS  
VVDD  
VGND  
VSS  
PWR Core analogue power and reference supplies.  
PWR output stage power. AVDD3 output stage logic.  
GND Output stage ground. AVSS3 output stage logic.  
PWR 75ohm buffer supply.  
7
10  
13  
15  
GND 75ohm buffer ground.  
24,31  
27,34  
41  
GND Digital padring & logic ground.  
PWR Digital padring & logic power.  
PWR Core digital power.  
VDD  
DVDD  
DVSS  
AGND  
42  
GND Core digital ground.  
48  
GND Core analogue ground and reference supplies.  
09/04/97  
9
VISION V V 5402 Sensor  
Pin  
Name  
Type  
Description  
ANALOGUE VOLTAGE REFERENCES  
2
3
VBG  
OA  
IA  
Internal bandgap reference voltage (1.22V nominal). Requires external  
0.1uF capacitor.  
VOFF/  
VPED  
Pedestal DAC & Offset Comp. DAC bias. Connect to VBG or external ref-  
erence.  
4
DEC2V2  
DEC2V7  
EBCK  
OA  
OA  
IA  
Decouple 2.2V reference. Requires external 0.1uF capacitor.  
Decouple 2.7V reference. Requires external 0.1uF capacitor.  
External black level bias. Internally generated. Decouple to VGND  
External white pixel threshold for exposure control. Decouple to VGND  
Defines white level for clamp circuitry. Requires external 0.1uF capacitor.  
Anti-blooming voltage reference. Requires external 0.1uF capacitor.  
Pixel reset voltage. Connect to VREF2V7 or external reference.  
Offset DAC common mode input. Connect to VREF2V7.  
5
8
9
EVWT  
IA  
43  
44  
45  
46  
47  
VBLWT  
IA  
VBLOOM OA  
VRT  
IA  
IA  
VCM  
VREF2V7 OA  
Internally generated 2.7V reference. Requires external 4.7uF capacitor.  
ANALOGUE OUTPUTS  
14  
AVO  
OA  
Buffered Analogue video out. Can drive a doubly terminated 75ohm load.  
SYSTEM CLOCKS  
25  
26  
CKOUT  
CKIN  
OD  
ID  
Oscillator output. Connect Crystal for standard timing.  
Oscillator input. Connect Crystal for standard timing.  
IMAGE TIMING SIGNALS  
37 ODD OD  
Odd/even field signal. (ODD = 1 for odd fields, ODD = 0 for even)  
10  
cd27031c.fm  
Pin List  
Pin  
Name  
Type  
Description  
DIGITAL CONTROL SIGNALS  
16  
17  
SAB1  
SIN  
ID↓  
ID↓  
Chip Address, Bit 1  
Used to reset video timing control logic without resetting any other part of  
VV5402. Resets video logic on the falling edge of the SIN pulse.  
18  
19  
SCE  
LIN  
ID↓  
ID↓  
Scan Mode Enable - only relevant to test mode.  
Gamma corrected or Linear output. LIN = 0, gamma corrected output,  
LIN = 1, linear output. Default is gamma.  
20  
21  
SAB0  
AEC  
ID↓  
ID↑  
Chip Address, Bit 0  
Automatic exposure control. AEC = 1, auto exposure is enabled; AEC = 0  
auto exposure and auto gain control are disabled.  
22  
23  
28  
AGC  
ID↑  
ID↑  
ID↓  
Automatic gain control enable. AGC = 1, auto-gain is enabled (if AEC = 1);  
AGC = 0, auto-gain is disabled.  
CCIR  
BKLIT  
Select default video mode for power-on. CCIR = 1 for CCIR video. EIA  
video mode is selected when CCIR = 0. Default is CCIR if unconnected  
Normal or Backlit exposure control mode. BKLIT = 0, normal mode; BKLIT  
= 1, backlit mode. Default is normal. See Exposure Control for details.  
29  
38  
RESETB  
SCI  
ID↑  
ID↓  
Active low camera reset. All camera systems are reset to power-on state.  
Scan Chain Input - only relevant to test mode.  
OTHER PINS  
6, 11, 12, 30, 32,  
33, 35, 36, 39, 40  
DNC DO NOT CONNECT. These pins must be left ‘floating’ for correct opera-  
tion.  
Key:  
OA  
OD  
-
-
Analogue output  
Digital output  
IA  
-
Analogue input  
ID - Digital input  
OD- Digital output with internal pull-down  
ID- Digital input with internal pull-up  
DNC- Do Not Connect  
BI  
-
Bidirectional  
09/04/97  
11  
VISION V V 5402 Sensor  
VIDEO STANDARDS  
The VV5402 has 2 different video format modes, producing CCIR or EIA standard composite  
Monochrome video output. Line standards and frequencies are as follows:  
Video Mode Format Image (Pixels) Crystal Frequency CCIR pin  
CCIR  
EIA  
4:3  
4:3  
384 x 287  
320 x 243  
14.7456 MHz  
12.0000 MHz  
1
0
VV5402 Video Modes  
Video signal Characteristics  
The following table summarises the composite video output levels (AVO) for the two standards,  
which are graphically illustrated on the following pages:  
Symbol  
Parameter  
Min.  
Typ.  
0.3  
Max. Units  
Notes  
V
V
VSync  
Vblank  
CCIR, EIA Sync. level  
0.9  
CCIR, EIA Blanking  
level  
DC reference  
level  
0.9  
1.0  
2.3  
2.4  
V
V
V
V
Vblack  
CCIR Black level  
EIA Black level  
VSat  
CCIR Saturation level  
EIA Saturation level  
Peak White;  
AVO clipped at  
this level  
Note: All measurements are made with AVO driving one 75load.  
12  
cd27031c.fm  
Video Standards  
CCIR Timing Diagram  
line time reference point  
rise times  
(10% - 90%)  
line blank 0.3 ± 0.1µs  
line sync. 0.25 ± 0.05µs  
{
line period H = 64µs  
line sync. 4.7µs  
back porch 5.8µs  
front porch 1.5µs  
peak white level  
2.3v  
black &  
blanking level  
0.9v  
0.3v  
sync. level  
CCIR composite video signal - line level timing  
frame start  
field 1  
field 0  
2.5H  
2.5H  
2.5H  
26H  
field 1  
2.5H  
field 2  
2.5H  
2.5H  
25H  
CCIR composite video signal - field level timing  
09/04/97  
13  
VISION V V 5402 Sensor  
EIA Timing Diagrams  
rise times  
(10% - 90%)  
line blank 0.3 ± 0.1µs  
line sync. 0.25 ± 0.05µs  
line time reference point  
{
line period H = 63.5µs  
line sync. 4.83µs  
back porch 4.00µs  
front porch 1.33µs  
peak white level  
2.4v  
black level  
blanking level  
sync. level  
1.0v  
0.9v  
0.3v  
EIA composite video signal - line level timing  
frame start  
field 0  
field 1  
3H  
3H  
3H  
19H  
field 2  
3H  
field 1  
3H  
3H  
20H  
EIA composite video signal - field level timing  
14  
cd27031c.fm  
Example Support Circuit  
EXAMPLE SUPPORT CIRCUIT  
AVD  
VDD  
8
REG1  
1
R1  
+7 to +12v dc  
0v  
2,3,  
6, 7  
C2  
C5  
C6  
C1  
C3  
C4  
24  
C7  
34  
1
41  
7
13  
27  
VDD1 VDD2  
DVDD  
MONITOR  
AVCC  
AVDD VVDD  
1. Keep nodes Supply and Ground pins  
low impedance and independent  
R4  
14  
AVO  
VSS1  
2. Video output should be referred to VGND.  
31  
42  
10  
48  
15  
VSS2  
DVSS  
AVSS  
VGND  
IC1  
3. Keep circuit components close to chip  
pins (especially de-coupling capacitors)  
(48 pin LCC)  
AGND  
23  
CCIR  
16  
SAB1  
SAB0  
20  
VDD  
38  
18  
SCI  
28  
19  
BKLIT  
LIN  
VV5402  
SCE  
Component  
IC1  
Value  
22  
21  
AGC  
AEC  
VV5402  
LM78L05  
C19  
8
9
EBCK  
REG1  
C18  
EVWT  
44  
45  
VBLOOM  
VRT  
C1,C2  
C3  
0.22 µF  
68 µF  
(6V Tant.)  
0.1 µF  
VBLTW  
C8  
C9  
43  
C17  
C16  
DEC2V7  
DEC2V2  
5
4
R5  
C4-C9,C13,  
C16-C19  
C10  
C11, C12  
C14  
46  
47  
VCM  
C15  
4.7µF  
10 pF  
100pF  
VREF2V7  
C10  
VOFF/VPED  
3
2
R1  
R2  
R3  
R4  
R5  
5R6  
10R  
10M  
75R  
33R  
CKIN CKOUT  
26  
VBG  
SIN  
17  
C13  
C14  
25  
R2  
R3  
C11  
C12  
X1  
Crystal  
CCIR:14.7456 MHz  
EIA:12.0000 MHz  
X1  
Use Surface Mount components throughout.  
09/04/97  
15  
VISION V V 5402 Sensor  
VLSI VISION LIMITED  
UK Office  
Aviation House,  
31 PInkhill,  
USA West Office  
18805 Cox Avenue,  
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USA East Office  
2517 Highway 35  
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EH12 7BF  
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Email: info@vvl.co.uk  
Email: info@vvl.co.uk  
VLSI Vision Ltd. reserves the right to make changes to its products and spec-  
ifications at any time. Information furnished by VISION is believed to be accu-  
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tion, nor any infringements of patents or of any other third party rights which  
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© Copyright 1996, VLSI VISION  
VLSI Vision agent or distributor  
16  
cd27031c.fm  
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