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VV5300 Sensor

Integrated CMOS Image Sensor with

on-chip ADC.

DISTINCTIVE CHARACTERISTICS

•

Standard image format: 160 x 120

164 x 124 pixel array

•

Reduced flicker operation with 50Hz and 60Hz

mains frequencies

•

2 serial data output modes

Variable frame rate (2 fps - 60 fps)

On-chip 8-bit A/D convertor

Automatic exposure and gain controller

Automatic black level calibration

Options selectable via serial interface

8-bit and 4-bit conversion modes

8-wire and 4-wire parallel data output modes

GENERAL DESCRIPTION

VV5300 is a highly-integrated CMOS image sensing VV5300 features electronic exposure and gain con-

device. In addition to a 160 x 120 pixel image sensor trol over a wide range, enabling the use of a single

array, the device includes on-chip circuitry to drive fixed-aperture lens.

and sense the array.

A bi-directional 2-wire serial communications inter-

The output stage of the sensor contains a successive face allows the device to be configured and its oper-

approximation circuit which performs analogue-to- ating status monitored. The status information may

digital conversion of the photodiode array to produce also be multiplexed onto the digital output bus.

8-bit or 4-bit pixel data.

The primary image size is 160 x 120 but border pix-

els/lines can be enabled to give an effective image

size of 164 x 124.

BLOCK DIAGRAM

VERTICAL

SHIFT

REGISTER

Pixel Resolution

Pixel Size

160 x 120

12µm x 12µm

1.92mm x 1.44mm

5v +/-10%

DIGITAL

CONTROL

LOGIC

PHOTO DIODE ARRAY

SDA

SCL

Array Size

Power Supply

Min.illumination

Power

CLKI

D[7:0]

0.1 Lux

CLOCK

SAMPLE & HOLD

CIRCUIT

CLKO

175 mW (Typ.)

36 dB (Typ.)

IMAGE

FORMAT

SIN

FST

QCK

S/N

VBLTW

HORIZONTAL SHIFT REGISTER

Exposure control

Temperature

Automatic (25000:1)

-20^oC to +70^oC

VRT

VCM

VREF2V5

VPED/VBG

VCDS

ANALOG

VOLTAGE

REFS.

A/D CONVERTOR

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VV5300 Sensor

Main Features

On-chip 8-bit successive approximation analogue-to-digital convertor with 8-wire, 4-wire parallel and two

serial data output modes.

The default image format is 160x 120. Extra border pixel/lines can be enabled to give an image size of 164

x 124. Digital pixel data coding assigns 10_Has black and F0_Has white. Other codes specify line sync and

frame sync periods.

The VV5300 frame rates can be integer multiples of the mains supply frequencies used worldwide, i.e. 50Hz

and 60Hz. This ensures reduced flicker operation of the sensor

All VV5300 operating modes and system status information can be accessed via a two wire bidirectional

serial interface.

VV5300 features an automatic electronic exposure algorithm that enables the use of a single fixed-aperture

lens. Automatic gain control enhances operation under low light conditions.

Automatic black level control ensures consistent picture quality across the whole range of operating

conditions. Extensive use of automated operation and on chip references means that only a small number of

passive components are needed to realise a complete video camera.

On-chip voltage references simplifies the support circuitry and maintains device stability over a wide range

of operating conditions.

This device is also available with bayer pattern colour filters (VV6300), see seperate datasheet.

Exposure Control

With automatic exposure control selected VV5300 uses a complex algorithm to automatically set the

exposure value for the current scene. When combined with clock control and gain control the VV5300 can

operate over a very wide range of illumination levels.

Where direct control of the exposure is required the exposure value can be directly selected by writing to the

appropriate registers via the serial interface.

Clock Control

The system clock can be divided down internally to extend the operating range of VV5300 by allowing longer

exposure times. The clock divisor can be varied from 2 to 16 in times two steps i.e there are 4 different values.

Note: changing the system clock divisor modifies the pixel and frame rate.

Gain Control

If the image is to dark and the exposure is already close to its maximum, VV5300 will increase the system

gain.

Gain can be varied from x1 to x8 in times two steps i.e there are 4 different gain settings. If the scene is too

dark and integration period has almost reached its maximum value the gain value is incremented by one step

(i.e. doubled). If the gain setting changes the exposure value is automatically set to half the maximum

integration period. The exposure controller then increases the exposure value as necessary.

Similarly if the image is too bright and the integration period is short then gain will be reduced by one step

(i.e. divide by two). As before, the exposure value is set to half the maximum integration period. The exposure

controller can then adjust the exposure value as necessary to provide a correctly exposed image.

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VV5300 Sensor

Device Pinout

30 29 28 27 26 25 24 23 22 21 20 19

CLKI

CLKO

SDA

31

18 NC

32

33

34

35

17 QCK

16 FST

15 SIN

SCL

VSS

14 VDD

13 DVDD

DVSS

36

37

38

VV5300

AUTOLOADB

CE

12

NC

11

10

9

NC

NC 39

VREG

40

41

42

AVDD

NC

8

7

NC

43 44 45 46 47 48

1

2

3

4

5

6

Viewed from above

Pad List

Name

Type

Description

POWER SUPPLIES

Analogue ground

Analogue power

Digital power

Power

6

AVSS

AVDD

DVDD

VDD

GND

PWR

GND

PWR

GND

9

13

14

19

20

29

30

35

36

VDD

Power

VSS

Ground

VSS

Ground

VDD

Power

VSS

Ground

DVSS

Ground

ANALOGUE OUTPUTS

Pixel reset voltage

1

VRT

IA

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VV5300 Sensor

Name

Type

Description

2

VCDS

TEST

IA

Voltage reference

Analogue test

3

40

44

45

46

VREG

ΙΑ

Reference voltage input

Internal reference voltage

Bitline test white reference

VBLOOM

VBLTW

VBG

ΟΑ

IA

OA

Internally generated bangap reference voltage

1.22V

47

VREF2V5

ΟΑ

Internally generated reference voltage 2.5V

DIGITAL OUTPUTS

16

17

FST

OD

Frame start. Synchronises external image

capture.

QCK

Pixel sample clock. Qualifies video output for

external image capture.

25-28

21-24

D[3:0]

D[7:4]

BI↓

Parallel 4-bit databus. D[0] serial data bus.

Parallel 4-bit databus.

OD↓

DIGITAL CONTROL SIGNALS

34

33

37

SCL

SDA

BI↑

ID↓

Serial bus clock (bidirectional, open drain)

Serial bus data (bidirectional, open drain)

Enable autoload from EEPROM

AUTOLO

ADB

38

4

CE

HPIX

SIN

ID↑

ID↓

Chip enable

Hold pixel value.

15

Frame Timing reset(Soft reset)

SYSTEM CLOCKS

Oscillator input.

31

32

CLKI

ID

CLKO

OD

Oscillator output.

OA - Analogue output

OD - Digital output

BI - Bidirectional

A - Analogue input

D - Digital input

ID↑ − Digital input with internal pull-up

OD↓ − Digital output with internal pull-down

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VV5300 Sensor

SPECIFICATIONS

Package Details

1.56

0.51

13.7

Glass Lid

0.55

0.86

Die

Base

0.5

0.53

Viewed from side

The optical array is centred within the

package to a tolerance of ± 0.2 mm, and

o

rotated no more than ± 0.5

Tolerances on package dimensions ±10%

Glass lid placement is controlled so that no

package overhang exists.

2.16

PIN 1

All dimensions in millimetres +/-

1.016 PITCH

Viewed from below

Spectral Response

1.0

0.8

0.6

0.4

0.2

0

Wavelength nm

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VV5300 Sensor

Absolute Maximum Ratings

Parameter

Value

Supply Voltage

-0.5 to +7.0 volts

Voltage on other input pins

Temperature under bias

Storage Temperature

-0.5 to V_DD+ 0.5 volts

-15^oC to 85^oC

-30^oC to 125^oC

Maximum DC TTL output Current Magnitude 10mA (per o/p, one at a time, 1sec. duration)

Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute

maximum ratings for extended periods may reduce reliability. Functionality at or above these

conditions is not implied.

DC Operating Conditions

Symbol

Parameter

Min.

4.75

Typ.

5.0

Max.

5.25

Units

Volts

Notes

V_DD

V_IH

V_IL

T_A

Operating supply voltage

Input Voltage Logic “1”

2.4

-0.5

0

V_DD+0.5 Volts

Input Voltage Logic “0”

0.8

70

Volts

^oC

Ambient Operating Temperature

Still air

AC Operating Conditions

Symbol

Parameter

Min.

Typ.

Max.

Units Notes

Crystal frequency

Serial Data Clock

14.318

MHz

KHz

1

2

CKIN

SCL

100

1. Pixel Clock = ^CKIN

/

2

2. Serial Interface clock must be generated by host processor.

Electrical Characteristics

Symbol

Parameter

Min.

Typ.

10

Max. Units

mA

Notes

1

I

Digital supply current

Analog supply current

DCC

25

mA

I

ADD

o

Typical conditions, V = 5.0 V, T = 27 C

DD

A

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VV5300 Sensor

Symbol

Parameter

Min.

Typ.

Max. Units

Notes

35

mA

1

I

Overall supply current

DD

V_REF2V7Internal voltage reference

2.700

1.22

Volts

V_BG

V_OH

V_OL

Internal bandgap reference

Output Voltage Logic “1”

Output Voltage Logic “0”

Input Leakage current

2.4

-1

Volts I_OH= 2mA

Volts I_OL= -2mA

0.6

µA

I

V

on

IH

ILK

input

1

µA

V on

IL

input

o

Typical conditions, V = 5.0 V, T = 27 C

DD

A

1. Digital and Analogue outputs unloaded - add output current.

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VV5300 Sensor

Operating Characteristics

Parameter

min.

typ.

50

max.

units

Note

Dark Current Signal

mV/Sec

Modal pixel voltage due to photodiode leak-

age under zero illumination with Gain=1

(V_dark= (V_t1- V_t2)/(t1-t2), calculated over

two different frames

Sensitivity

6

V/Lux·Sec V_Ave/Lux·10ms, where Lux gives 50% satu-

ration with Gain=1 and Exposure=10ms

Min. Illumination

Shading

0.1

Lux

%

Standard CCIR clock

TBA

Variance of V_aveover eight equal blocks at

66% saturation level illumination

Random Noise

Smear

-36

dB

%

RMS variance of all pixels, at 66% satura-

tion, over four frames

TBA

Ratio of V_aveof the area outside a rectangle

25 lines high illuminated at 500xV_50%level

to V_Aveof the rectangle

Flicker

Lag

TBA

%

Variation of V_aveof one line from field to field

at 66% saturation level illumination

Average residual signal with no illumination

in the field following one field of 66% sat.

illumination

Blooming

TBA

Ratio of spot illumination level that produces

0.1xV_satoutput from immediately around the

spot to the V_satspot illumination level (pin-

hole target)

Note: Devices are normally not 100% tested for the above characterisation parameters, other than

Dark Current Signal (see Blemish Specification below).

All voltage (V , V , V , V

blemishes are excluded (see Blemish Specification below). V

saturation, that is peak white

) measurements are referenced to the black level, V

, and spot

black

A

ave sat

xx%

refers to the output that is xx% of

xx%

Test Conditions

Illumination Colour Temp.

Clock Frequency

Exposure

3200^oK

14.318MHz

Maximum

x1

The sensor is tested using the example support

circuit illustrated later in this document. Standard

imaging conditions used for optical tests employ a

tungsten halogen lamp to uniformly illuminate the

sensor (to better than 0.5%), or to illuminate

specific areas. A neutral density filter is used to

control the level of illumination where required.

Gain

Auto. Gain Control (AGC)

Off

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VV5300 Sensor

Blemish Specification

A Blemish is an area of pixels that produces output significantly different from its surrounding pixels

for the same illumination level. The definition of a Blemish Pixel varies according to testing condi-

tions as follows:

Test

Exposure

Minimum

Illumination

Black

Blemish Pixel output definition

1 - Black Frame

Differing more than ± 100 mV. from modal

value.

2 - Dark Current

3 - Pixel Variation

Maximum

Mid range

Black

Output more than three times the modal value

(see Dark Current Signal above).

66% Sat.

Differing more than ±35mV from modal value.

Note: The mode of pixel values must be within

±70 mV of 66% of V_satfor all devices.

Note: Gain is set to Minimum and Correction set to Linear for all tests; measurement of blemishes for

Test 3 is conducted under standard illumination (see above), set to produce average output of

66% saturation level.

The blemish specification is then defined as follows:

Max. No. of Blemishes

Notes

4

1

Unconnected single pixels

Of up to four connected pixels (2x2 max.)

NB, pixel blemishes may occur anywhere on the array.

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VV5300 Sensor

System Clock Generation

VV5300 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI

and CLKO pins. The device can also be driven directly from an external clock source driving CLKI.

CLK

CLOCK

DIVISION

CLOCK

DIVISION

VV5300

CKOUT

32

CKIN

31

CKOUT

32

CKIN

31

C1=C2=47pF

R1=1MΩ

R1

R2=510Ω

R2

Clock

Source

X1= 14.318MHz (up to 60fps)

17.73MHz (up to 50fps)

C1

C2

CMOS Driver

X1

Camera Clock Source

For greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency.

Two bits in the clock division register in the serial interface select the input clock frequency divisor. The table

below gives the different frame rates that can be selected, when CLKI = 14.318MHz, for each divisor. The

default clock divisor setting is a divide by 2. To achieve maximum frame rates data is converted at 4 bit

resolution.

1

CLKI

(MHz)

Pixel Freq.

(kHz)

Frame rate

(fps)

Divisor

Comments

default

14.318

0

1

0

1

0

1

2

4

1790

895

448

224

59.98

29.99

15.01

7.5

8

16

Clock Division (60Hz Video Mode)

1.

Approximate frame rate. Assumes 160 x 120 image format, parallel data output and 4 bit data

conversion

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VV5300 Sensor

Image Format

VV5300 has a single output image size, 160 x 120 pixel. The image size can be modified by asserting the

“enable borders” serial interface register bit, (Setup1, [001_0001₂]). The extended image size is 164 x 124

pixels. The default image format is 160 pixels by 120 lines.

Enable borders

Image size (column x row)

Comment

0

1

160 x 120

164 x 124

default

Image Format Selection

The diagram below shows the relationship between the default 160 x 120 pixel image and the extended 164

x 124 pixel format. A border, 2 pixels wide is enabled around the basic array.

164

160

Output Image Dimensions

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VV5300 Sensor

Frame Timing

The VV5300 frame rate depends upon:

(i)

the frequency of the clock input (CLKI)

(ii) the ADC conversion accuracy

(ii) the internal clock divisor chosen.

Users can set their own values for CLKI, the ADC conversion rate and also the clock divisor setting, subject

to achieving a frame rate up to 60 frames/sec.

The frame rate is determined in the following way:

An example is given with a clock input of 14.318MHz, 160 x120 image format, 8 bit ADC conversion rate and

a clock divisor of 4.

1.

2.

Determine clock input (CLKI) frequency - 14.318MHz

Pixel period = (Divisor x 8) / CLKI

Example:

Pixel period

= (4 x 8) / 14.318MHz

= 2.235µs

3.

Line period = (no. of active pixels + line overhead) * pixel period

The number of active pixels per line is either 160 or 164. The interline pixel period overhead (including the 4

border pixels that can be enabled to qualify extra video information) is mode dependent, 43 pixel periods for

60fps or 135 pixel periods for 50fps. Refer to figure * for more information.

Example:

Line period

= (160 + 43) x 2.235µs = 453.705µs

4.

Frame period = (no. of active lines + frame overhead) * line period

For the purposes of calculating the effective frame rate the number of active lines is assumed to be fixed at

120. The frame overhead (which includes the 4 border lines that can be enabled to qualify extra video

information) has a constant value of 27 line periods. Refer to table * for more information.

Example:

Frame period

Frame rate

= (120 + 27) x 453.705µs

= 66.694ms

= 1 / frame period

= 15 frames per second

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VV5300 Sensor

Digital Data Output Modes

VV5300 provides several different output modes. The different data formats are selected via the appropriate

register in the serial interface, Setup0, [001_0000₂], bits 5 and 6. 8-bit or 4-bit pixel data conversion is also

selected via the serial interface, Setup1, [001_0001₂]. If 4-bit pixel data conversion is selected as well as 8-

Wire parallel output format then 2 consecutive pixel nibbles may be packed into a single output byte therefore

increasing the effective frame rate.

Setup

Bit 6

Setup

Bit 5

Description

Comment

default

0

1

0

1

0

1

8-Wire Parallel

4-Wire Parallel

Serial

Serial UART

Data Output Modes

Frame Level Formatting

The frame level format for each mode is common and is given below. FST can be used for frame

synchronisation. The FST pulse is exactly one line period in length and the rising edge occurs just before the

status line start sequence (see line level formatting) is output.

Frame Start

FST

Black Lines (BK)

Visible Lines (VL)

Line

BL BL BL BL

Blank Lines (BL)

BL ST BK BK BL

BL BL BL

BL BL VL VL VL VL VL VL VL

VL

Start / Status Line (ST)

120 Visible Lines

FST

Line

BL

VL BL

BL BL

BL FE BL ST

BL BL

BL BL BL BL BL

Frame End (FE)

BL BL BL BL

Frame Period = 147 Lines

Frame Format (160 x 120 mode)

Frame Start

Black Lines (BK)

FST

Line

Visible Lines (VL)

BL BL BL BL

BL ST BK BK BL

Start / Status Line (ST)

BL BL BL

VL VL VL VL VL VL VL VL VL

VL

124 Visible Lines

Blank Lines (BL)

FST

Line

VL

VL VL

BL BL

BL FE BL ST

BL BL

BL BL BL BL BL

Frame End (FE)

BL BL BL BL

Frame Period = 147 Lines

Frame Format (164 x 124 mode)

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VV5300 Sensor

Line Level Formatting

Each line type (black, blank, visible) has a specific format associated with it independent of the data output

format selected. Each line begins with a start sequence of FF_HFF_H00_Hfollowed by XY_Hwhere XY_Hindicates

the line type. The next two bytes provide supplementary data (specifically the line number within the current

frame). Following this data are two guaranteed blank bytes (07_H07_Hfor 8 bit modes, 01_H01_Hfor 4 bit modes).

If the border lines/pixels have been enabled the next 2 bytes will be visible pixels otherwise they shall appear

as blank bytes. The next part of the line is reserved for the 160 visible pixels. The 4 bytes following the visible

pixels are formatted in the same way as the 4 bytes preceeding the 160 visible pixels. At the end of each line,

an end of line sequence is produced, (FF_HFF_H00_H80_H). If the line is within the visible part of the frame,

(lines 11 to 134 if the border lines are enabled otherwise lines 13 to 132), the end of line sequence is

immediately followed by 2 bytes containing the mean values for the central 128 pixels. The first byte contains

the mean value for the first 64 pixels of the middle 128 pixels and the second byte contains the mean value

for the latter 64 pixels of the middle 128 pixels. The 128 pixels comprise the standard 120 visible pixels, the

4 border pixels and an extra 4 border pixels that are never enabled as visible pixels but are used for exposure

control and hence contribute to the mean pixel value for the line. If the line type is not visible then the two

bytes following the end of line sequence will contain 07_H07_H. For the remainder of the interline period the

data output is always FF_H.

Sensor status and configuration information is output during the frame start line, (line 0), each data byte is

separated by a blank value (07_H) to avoid possible false line start conditions being generated. The

information output during the status line reflects, if the sensor is operating in 8bit ADC mode, the first 64

locations in the serial interface register map. If the sensor is operating in 4 bit mode less data can be output

during the status line. All the serial interface registers are 8bit values therefore 2, 4bit pixel periods are

required to output a single serial interface location. Note that the serial interface data is only output during

the visible monochrome pixels of the status line. This allows for one quarter of the serial interface address

space to be output during any status line. It is possible to select the remaining registers in the serial interface

for output, (see serial interface register setup 2, bits 7:6).

The “end of frame” line, it is actually 2 lines prior to the status line will output the 4 exposure control bin

averages during the first 4, (or 8 if operating in 4bit modes), monochrome pixels. Again the data is separated

by mode dependent padding data.

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VV5300 Sensor

Escape/Sync Sequence

XY

D D

1 0

8-wire output mode

4-wire output mode

FF

00

H

3

2

H

F F F F 0 0 X Y D D D D

0

H

3

2

1

Command

(Line Code)

C₂C₁C₀P₃P₂P₁P₀

1

Nibble X_H

Nibble Y_H

Supplementary Data

(i) Line Number (L₁₁MSB)

or (ii) If Line Code = End of Line then

L₁₁L₁₀L₉L₈L₇L₆

P

0

M₇M₆M₅M₄M₃M₂M₁M₀

Nibble D₃

L₅L₄L₃L₂L₁L₀

Nibble D₂

Mean Pixel Value for first half of the line

N₇N₆N₅N₄N₃N₂N₁N₀

0

Nibble D₁

Nibble D₀

Mean Pixel Value for second half of the line

Odd word parity

Line Code

Nibble X [1 C C C ] Nibble Y [P P P P ]

H 2 1 0 H 3 2 1 0

End of Line

1000₂(8_H)

1001₂(9_H)

1010₂(A_H)

1011₂(B_H)

1100₂(C_H)

1101₂(D_H)

1110₂(E_H)

1111₂(F_H)

0000₂(0_H)

1101₂(D_H)

1011₂(B_H)

0110₂(6_H)

0111₂(7_H)

1010₂(A_H)

1100₂(C_H)

0001₂(1_H)

Blank Line (BL)

Black line (BK)

Visible Line (VL)

Start of Frame (SOF)

End of Frame (EOF)

Reserved

Line Level Formatting

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VV5300 Sensor

Line Start Sequence

FF_HFF_H00_HC7_HLN

Sensor Status Data

07_HSD 07_HSD 07_HSD

07_H07_HSD

07_HSD

07_H

LN

07_H07_H

FRAME

START

Line Start

Line Number

Line Type

Inter-Line Period

Line End Sequence

Next Line Start

FF_HFF_HFF_HFF_H00_H

SD

07_HSD

07_H

07_H07_HFF_HFF_H00_H80_H07_H07_HFF_HFF_HFF_H

Line End

Line Start Sequence

FF_HFF_H00_HAB_HLN

Black Level Pixel Values (Nominally - 10_H)

PV

BLACK

07_H07_H

LN

07_H07_H

Line Start

Line Number

Line Type

Inter-Line Period

Line End Sequence

Next Line Start

FF_H

FF_H00_H

PV

07_H07_H07_H07_H

80_H

07_HFF_H

FF_H

FF_HFF_H00_H

07_H

FF_HFF_H

FF_H

Line End

Line Start Sequence

Blank Level (07_H)

07_H07_H07_H07_H07_H07_H07_H07_H07_H07_H07_H07_H07_H07_H

BLANK

FF_HFF_H00_H9D_HLN

LN

07_H07_H

Line Start

Line Number

Line Type

Inter-Line Period

Line End Sequence

Next Line Start

07_H07_H07_H07_H07_H07_H

07_H07_HFF_HFF_H00_H80_H07_H07_HFF_HFF_HFF_H

FF_HFF_HFF_HFF_H00_H

Line End

160 Visible Pixels

Black = 10_H- White = F0_H

Line Start Sequence

VISIBLE

07_H07_HPV

PV

FF_HFF_H00_HB6_HLN

LN

07_H07_H

Line Start

Line Number

Line Type

Inter-Line Period

07_H07_HFF_HFF_H00_H80_HMN MN FF_HFF_HFF_H

Line End Sequence

Next Line Start

FF_HFF_HFF_HFF_H00_H

PV

07_H

Line End

Line Mean Values

Frame Mean Values

07_HMN 07_HMN

Line Start Sequence

MN

07_H07_H

MN

07_H07_H07_H07_H

FF_HFF_H00_HDA_HLN

LN

07_H07_H

07_H

FRAME

END

Line Start

Line Number

Line Type

Inter-Line Period

Line End Sequence

Next Line Start

07_H07_H07_H07_H07_H07_H

07_H07_HFF_HFF_H00_H80_H07_H07_HFF_HFF_HFF_H

FF_HFF_HFF_HFF_H00_H

Line End

Line Coding

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VV5300 Sensor

8-Wire Parallel Mode

8-Wire parallel mode is selected when the appropriate bits are set via the serial interface.

When 8-bit conversion mode is selected the 8-bit pixel data is output on pins DATA[7:0]. The start of a frame

is indicated by a pulse on FST. The data is valid on the falling edge of the pixel sample clock fast QCK (QCK_F)

or on each edge of the slow QCK (QCK_S).

Line Start Line Type Line No.

P1

P2

P6

P7

P8

P9

P10

07_H07_HP0

P3

P4

P5

DATA[7:0]

FF_HFF_HFF_H00_HB6_HLN

LN

07_H07_H

QCK

F

S

Line Mean

Line End

P117 P118 P119 P120

DATA[7:0]

07_H07_H07_H07_HFF_HFF_H00_H80_HMN MN FF_HFF_HFF_H

FF_HFF_HFF_HFF_H00_H

QCK

F

S

8-Wire Parallel Mode (8-bit Pixel Data)

When 4-bit conversion mode is selected the 4-bit pixel data is output two bytes at a time on the DATA[7:0]

pins. The first pixel is mapped onto DATA[7:4] and the second pixel is output on DATA[3:0]. This effectively

doubles the pixel rate (and halves the frame period).

Line Start Line Type Line No.

F_H

0_H

B_H

6_H

LN

1_H

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10 P12 P14 P16 P18 P20 P22 P24

P11 P13 P15 P17 P19 P21 P23 P25

1_H

DATA[7:4]

DATA[3:0]

QCK

F

QCK

S

Line End

Line Mean

P102 P104 P106 P108 P110 P112 P114 P116 P118 1_H

1_H

F_H

0_H

8_H

0_H

MN MN F_H

F_H

0_H

DATA[7:4]

DATA[3:0]

P103 P105 P107 P109 P111 P113 P115 P117 P119

QCK

F

S

QCK

8-Wire Parallel Mode (4-bit Pixel Data)

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VV5300 Sensor

4-Wire Parallel Mode

4-Wire parallel mode is selected when the appropriate bits are set via the serial interface. When 8-bit data

conversion mode is selected (CONV8 = 1) the 8-bit pixel data is output on pins DATA[7:4] in two 4-bit nibbles.

The start of a frame is indicated by a pulse on FST. A QCK sample edge is generated for each nibble.

Line Start

F_HF_H

Line Type

B_H6_H

Line No.

LN LN

0_H

7_H

0_H

6_H

LN

0_H

F_H

7_H

F_H

0_H

F_H

0_H

7_H

F_H

0_H

DATA[7:4]

P0

QCK

F

S

Line End

0_H

7_H

0_H7_H

P115 P116 P117 P118 P119

0_H

7_H

0_H

7_H

F_H

0_H

8_H

0_H

MN MN

DATA[7:4]

QCK

F

S

MN MN F_H

LN

F_H

0_H

B_H

DATA[7:4]

QCK

F

S

4-Wire Parallel Mode (8-bit Pixel Data)

When 4-bit data conversion mode is selected (CONV8 = 0) the 4-bit pixel data is output on pins DATA[7:4].

Line Start

F_HF_H

Line Type

B_H6_H

Line No.

LN LN

LN

1_H

P0

P1

P2

P3

P4

F_H

0_H

1_H

DATA[7:4]

QCK

F

S

Line End

F_H

0_H

P113 P114 P115 P116 P117 P118 P119 1_H

1_H

F_H

MN MN

1_H

F_H

0_H

8_H

0_H

F_H

DATA[7:4]

QCK

F

S

DATA[7:4]

F_H

LN

F_H

0_H

B_H

6_H

QCK

F

S

4-Wire Parallel Mode (4-bit Pixel Data)

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VV5300 Sensor

Serial Mode

Serial mode is selected when the appropriate bits are set via the serial interface. When 8-bit data conversion

mode is selected the 8-bit pixel data is output on pin DATA[0] least significant bit first.

Line Start Line Type

Line No.

DATA[0]

QCK

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

FF_HFF_HFF_H00_HB6_HLN LN

07_H07_H

Line End

P116 P117 P118 P119

07_H

DATA[0]

QCK

07_H

07_H07_HFF_HFF_H00_H80_HMN MN FF_HFF_HFF_H

FF_HFF_HFF_HFF_H00_H

Pixel_0

Pixel_1

4

Pixel_2

DATA[0]

0

1

2

3

5

6

7

0

1

2

3

5

6

7

0

1

2

3

4

QCK

F

S

Serial Mode (8-bit Pixel Data)

When 4-bit data conversion mode is selected (CONV8 = 0) the 4-bit pixel data is output on pin DATA[0] least

significant bit first.

Line Start

F_HF_H

Line Type

B_H6_H

Line No.

LN LN

DATA[0]

QCK

LN

1_H

P2

P3

P4

P5

P6

F_H

0_H

1_H

Line End

DATA[0]

QCK

P113 P114 P115 P116 P117 P118 P119

P111 P112

1_H

F_H

0_H

8_H

0_H

MN MN

1_H

F_H

LN

F_H

0_H

B_H

6_H

DATA[0]

QCK

Pixel_0

Pixel_1

Pixel_2

Pixel_3

1

Pixel_4

2

DATA[0]

0

1

3

1

2

3

2

3

0

1

2

3

0

1

2

3

0

QCK

F

QCK

S

Serial Mode (4-bit Pixel Data)

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VV5300 Sensor

Serial UART Mode

Serial UART mode is selected when the appropriate bits are set via the serial interface. When 8-bit data

conversion mode is selected the 8-bit pixel data is output on pin DATA[0] least significant bit first. Each pixel

is preceded by a start bit and followed by an additional data bit and two stop bits.

Line Start Line Type Line No.

DATA[0]

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

FF_HFF_HFF_H00_HB6_HLN

LN

07_H07_H07_H07_H

Line End

07_H07_HFF_HFF_H00_H80_HMN MN FF_HFF_HFF_H

P116 P117 P118 P119

FF_HFF_HFF_HFF_H00_H

07_H

Pixel_0

3

07_H

Pixel_1

DATA[0]

6

0

1

2

5

7

3

0

2

4

5

6

7

4

1

Least Significant Bit First

Start Bit

Unused Data Bit

Two Stop Bits

Serial UART Mode (8-bit Pixel Data)

When 4-bit data conversion mode is selected the 4-bit pixel data is output two pixels at a time on pin DATA[0]

least significant bit first. Each pixel is preceded by a start bit and followed by an additional data bit and two

stop bits.

Line Start

F_HF_H

Line Type

0_H8_H

Line No.

LN LN

DATA[0]

1_H

LN

1_H

P0

P1

P2

P3

P4

F_H

0_H

Line End

1_H

P111 P112 P113 P114 P115 P116 P117 P118 P119

1_H

F_H

0_H

E_H

MN MN

MN MN F_H

LN

F_H

0_H

8_H

DATA[0]

Pixel_0

2

Pixel_1

Pixel_3

Pixel_2

2

0

1

3

1

3

0

1

2

3

0

1

Least Significant Bit First

Start Bit

Unused Data Bit

Two Stop Bits

Serial UART Mode (4-bit Pixel Data)

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VV5300 Sensor

Qualifying the Output Data

Data is output from VV5300 in a continuous stream. By utilising signals, like FST, and key events, like the

start of a line or the end of line, the user can sample and display the image data. QCK is used to sample the

data, as described in the previous section. By default the falling edge of QCK will sample the data, however

it is possible to use both the rising and falling edges of a slow QCK QCK_Sto sample the data.

Different sections of the frame can be enabled by QCK. The options, which are selected via setup register4

in the serial interface, are as follows, firstly the QCK can be disabled, therefore no data will be qualified. This

is the default option.

The second option is to have the QCK free running where all the data is qualified.

The third option is to only qualify the image data, which also includes the 2 black calibration monitor lines,

lines 1 and 2 in the frame. This option is further complicated in that extra black lines and the extra border

pixels/lines can be enabled giving the following 4 options:

1. Black lines (1-2) plus image (160 pixels by 120 lines)

2. Black lines (1-8) plus image (160 pixels by 120 lines)

3. Black lines (1-2) plus image (164 pixels by 124 lines)

4. Black lines (1-8) plus image (164 pixels by 124 lines)

The final option is to qualify the embedded frame control sequences as well as the image data. These control

sequences are the 6 bytes at the start and at the end of each image line, where an image line is defined

above. The frame start or status line, image and control sequence pixels, will also be qualified during this

mode.

QCK Exceptions

The output data from VV5300 can be formatted in many ways, as detailed in an earlier section of this

document. Under certain operating conditions the relationship between QCK and the output data is

compromised.

It is vital that the phase relationship between the output data stream and the QCK must be maintained from

line to line, for example ensuring that, if enabled, the line code byte is always qualified by the same edge of

the QCK, clearly only applicable when considering slow QCK qualification. It is known that there are an odd

number of pixel periods in each line of the frame. If the slow QCK is selected then clearly two pixels are

qualified during each QCK cycle resulting in the following modes of operation requiring special care: 4 bit

ADC 8 wire output, 8 bit ADC 8 wire output and 4 bit ADC 4 wire output. During the interline period, when the

data bus is outputting data fixed at FF (8bit ADC) or F (4bit ADC), the phase of the QCK is toggled, this will

occur during every interline period. For the 8bit 8wire or 4bit 4 wire options this change is a simple inversion.

The 4bit 8wire option is not quite as straightforward. During the interline period the QCK signal is changed

from its former state to 1 of 3 other states. In addition 2 out of the 4 possible states are video timing mode

dependent.

Please note that the number of nibbles/bytes qualified by the clocks described above, during the free running

QCK mode, will differ from the expected value, as follows:

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VV5300 Sensor

QCK Exception Details

Number of pixels qualified

50 frames per second

Number of pixels qualified

60 frames per second

Operating Mode

QCK_F

QCK_S

QCK_F

QCK_S

4bit 4wire

4bit 8wire

8bit 8wire

203

202

203

202

198

202

301

300

301

300

298

300

Pixel qualification exceptions

Serial Interface - Exposure Control Handshake

The process of writing timed exposure, clock division or gain settings to VV5300 using the serial interface

requires special attention. These timed parameters can be written to the serial interface at any point within

the frame timing but will only be transferred from shadow registers to their active registers at a specific point

within the frame timing, see diagram below. Please note that writing immediate clock division or gain

parameters are treated as a “normal” serial interface write messages.

odd frame

flag

new_exp

old_exp

old_clock_div

new_clock_div

new_gain

old_gain

1 frame period

Since the new external exposure, clock division or gain settings are written to shadow registers the user

continues to have full read/write access to the serial interface. A handshake system has been implemented

between the exposure controller and the serial interface to avoid the user writing, for example, a second

external timed gain value while the exposure controller has yet to transfer the first external timed gain value

from the shadow register to the active register. If an external timed gain message has been written a special

flag will be raised to indicate that it has yet to be transferred to the active register. This flag is available to the

user via reading the status 0 register in the serial interface. Until the flag is lowered the user knows that it is

not safe to write a further external gain value. Identical handshake protocols are used to implement timed

external exposure and clock division writes.

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VV5300 Sensor

Auto Black Calibration

Black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal.

VV5300 is equipped with an automatic function that continually monitors the output black level and calibrates

if it has moved out of range. Black calibration can be split into two stages, monitor (1 cycle) and update (3

cycles). During the monitor phase the current black level is compared against two threshold values. If the

current value falls outside the threshold window then an update cycle is triggered. The update cycle can also

be triggered by a change in the gain applied to sensor core or via the serial interface.

Serial Interface

In order to be controlled and configured by its host, VV5300 can receive and transmit data via a two-wire

serial interface.

Serial Communication Protocol

The host must perform the role of a communications master and the camera acts as either a slave receiver

or transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial

clock frequency of up to 100kHz. Since the serial clock is generated by the host it determines the data

transfer rate. The bus address for VV5300 is 20_H. Data transfer protocol on the bus is shown below.

Start condition

Read/Write bit

Acknowledge from receiver

SDA

SCL

MSB

2

1

7

8

9

1

3 - 8

9

P

S

ACK

Stop condition

Data Transfer Protocol

Data format

A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated

start followed by another message.

The first byte contains the device address byte which includes the data direction read/write bit. The device

address is 32₁₀Write, 33₁₀Read. The 5 msbs of the address byte are fixed as 0010_0₂. The lsb of the

address byte indicates the direction of the message. An even address causes the addressed slave to receive

information from the master (write), an odd address indicates message read by the master.

Sensor acknowledges valid address

Acknowledge from slave

DATA[7:0]

A

address[7:1]

0 0 1 0 0 0 0

[0]

S

A

INC

INDEX[6:0]

A

R

/

bit

W

DATA[7:0]

A

P

Data Format

After the read/write bit is sampled, the data direction cannot be changed, until the read/write bit next message

is received. The next byte contains the location of the first data byte (also referred to as the index).There may

be up to 128 such locations. If the msb of the second byte is set the automatic increment feature of the

address index is selected.

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VV5300 Sensor

Message interpretation

All serial interface communications with the sensor must begin with a start condition. If the start condition is

followed by a valid address byte then further communications can take place. The sensor will acknowledge

the receipt of a valid address by driving SDA low. The state of the read/write bit (lsb of the address byte) is

stored and the next byte of data can be interpreted.

During a write sequence the second byte received is an address index and is used to point to one of the

internal registers. The msbit of the following byte is the index auto increment flag. If this flag is set then the

serial interface will automatically increment the index address by one location after each slave acknowledge.

The master can therefore send data bytes continuously to the slave until the slave fails to provide an

acknowledge or the master terminates the write communication with a stop condition or sends a repeated

start, (Sr). If the auto increment feature is used the master does not have to send indexes to accompany the

data bytes.

As data is received by the slave it is written bit by bit to a serial/parallel register. After each data byte has

been received by the slave, an acknowledge is generated, the data is then stored in the internal register

addressed by the current index.

During a read message, the current index is read out in the byte following the device address byte. The next

byte read from the slave device are the contents of the register addressed by the current index. The contents

of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl.

At the end of each byte, in both read and write message sequences, an acknowledge is issued by the

receiving device. Although VV5300 is always considered to be a slave device, it acts as a transmitter when

the bus master requests a read from the sensor.

At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one

greater the last location read from or written to. A subsequent read will use this index to begin retrieving data

from the internal registers.

A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start

condition or by a negative acknowledge after reading a complete byte during a read operation.

The programmers model

There are 128, 8-bit registers within the camera, accessible by the user via the serial interface. They are

grouped according to function with each group occupying a 16-byte page of the location address space.

There are eight such groups, The primary categories are given below:

• Setup registers with bit significant functions including status (read only) bits

• Exposure parameters that influence output image brightness.

• System functions and test bit significant registers.

Any internal register that can be written to can also be read from.

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VV5300 Sensor

Index

Name

R/W

Default

Comments

000_0000

000_0001

RO

-

1100 0000₂(C0_H)

0001 0010₂(12_H)

0000 1000₂(08_H)

Reserved

000_0010 status0

System status information

000_0011 unused

000_0100 line_count

000_0101 leftav

RO

Current line counter value

Average value of pixels in the first

half of the current line.

000_0110 rghtav

RO

Average value of pixels in the second

half of the current line.

000_0111 frame_av

000_1000 bin1

000_1001 bin2

000_1010 bin3

000_1011 bin4

000_11xx unused

001_0000 setup0

001_0001 setup1

001_0010 setup2

001_0011 setup3

001_0100 setup4

001_0101 unused

001_011x unused

001_1xxx unused

010_0000 unused

010_0001 fine

RO

-

Average value of pixels in a frame.

Partial frame average - bin1

Partial frame average - bin2

Partial frame average - bin3

Partial frame average - bin4

R/W

-

0010_0111₂(27_H)

0111_0000₂(70_H)

0001_1111₂(1F_H)

0000_1111₂(0F_H)

Configure the digital logic

Pixel counter reset value

Exposure control modes

0000_0000₂(00_H) FST/QCK options

-

R/W

-

0000_0000₂(00_H)

0111_0000₂(70_H)

Fine exposure initially zero

Coarse exposure

010_0010 unused

010_0011 coarse

010_0100 gain

010_0101 clk_div

010_0110 gn_lim

010_0111 tl

R/W

-

0000_0000₂(00_H) Gain value

0000_0000₂(00_H) Clock division

0000_0111₂(07_H)

Maximum allowable gain

0101_0101₂(55_H) Lower exposure control threshold.

1001_0110₂(64_H) Centre exposure control threshold.

010_1000 tc

010_1001 th

0110_0110₂(73_H)

Upper exposure control threshold.

010_101x unused

010_1xxx unused

111_0011 xfav

-

R/W

1000_0000₂(80_H)

External frame average

111_0101 dcth

1000_0000₂(80_H) Digital comparator threshold

111_1001 unused

111_1010 unused

111_1011 unused

111_11xx unused

The programmers model

A detailed description of each register follows. The address indexes are shown as binary in brackets.

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VV5300 Sensor

Status 0 [000_0010 ]

2

The loading of certain system parameters is timed to avoid disturbing the video signal part way through a

frame. Bits 0-2 can be polled to check that a value written to either the exposure, gain or clock division

registers has been consumed or not. Bit 3 is essentially an internal flag differentiating between consecutive

frames.

Bit

Function

Default

Comment

0

Exposure value update pending

0

New exposure setting sent but not yet con-

sumed by the exposure controller

1

2

Clock division value update

pending

0

New clock division setting sent but not yet

consumed by the exposure controller

Gain value update pending

New gain value sent but not yet consumed by

the exposure controller

3

4

Odd/even frame

0

The flag will toggle state on alternate frames

Black Calibration fail flag

If the black calibration algorithm returns very

poor black levels - outwith both the calibration

and monitor windows then this flag will be set

and it will stay set until the next successful cal-

ibration is complete

7:5 Unused

0

Status 0 [000_0010 ]

2

Line_count [000_0100 ]

2

Bits

Function

Default

Comment

7:0

Line count

0000_0000₂Displays current line count

Line_count [000_0100 ]

2

The video timing logic is controlled by the pixel counter and the line counter. To reduce the level of digital

switching noise these counters implement a gray count sequence, where only a single counter register can

change state in a clock period. However the gray count sequence is user unfriendly,e.q. 248,232,233,

235,234. A binary version of the line count is generated internally, realising a 0,1,2,3,4..... sequence, and it

is this count sequence that is read by the serial interface and hence made available to the sensor user.

Line_avg 0 [000_0101 ] & Line_avg 1 [000_0110 ]

2

The exposure controller accumulates the pixel output values. On a line by line basis the accumulation is

performed in two stages. The qualified pixels in the left half of the video line are accumulated and then stored

in a latch. The process is then repeated during the right half of the video line. During the interline line period

(up until the latch that stores the value for the left half of the line is updated during the next line) the latches

will present valid average 8-bit pixel values for both halves of the line.

Bits

Function

Default

Comment

7:0

Line average

0

Average pixel value for first half of current line.

Line_avg 0 [000_0101 ]

2

Bits

Function

Default

Comment

7:0

Line average

0

Average pixel value for second half of current line.

Line_avg 1 [000_0110 ]

2

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VV5300 Sensor

Frame_avg [000_0111 ]

2

The average pixel values stored in latches halfway through and at the end of each active video line

are ultimately stored in bins that will maintain a frame sum of the pixel values. At the end of the

frame the values stored in these bins are used to determine the overall pixel average for the whole

frame.

Bits

Function

Default

Comment

7:0

Frame average

0

Pixel average for previous frame

Frame_avg [000_0111 ]

2

Bin1_avg [000_1000 ]

2

Bits

Function

Default

Comment

7:0

Bin1 average

0

Pixel average for current line

Bin1_avg [000_1000 ]

2

Bin2_avg [000_1001 ]

2

Bits

Function

Default

Comment

7:0

Bin2 average

0

Pixel average for current line

Bin2_avg [000_1001 ]

2

Bin3_avg [000_1010 ]

2

Bits

Function

Default

Comment

7:0

Bin3 average

0

Pixel average for current line

Bin3_avg [000_1010 ]

2

Bin4_avg [000_1011 ]

2

Bits

Function

Default

Comment

7:0

Bin4 average

0

Pixel average for current line

Bin4_avg [000_1011 ]

2

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VV5300 Sensor

Setup 0 [001_0000 ]

2

Setup registers 0,1,2,3 and 4 are used to alter the operating parameters of the sensor. All of these registers

can be written to and read from.

Setup 0 register controls some fundamental exposure and output format parameters. Defaults are shown in

Bold.

Bit

Function

Default

Comment

0

Automatic exposure control.

Off/On

1

Enables or disables automatic exposure control.

Current exposure value is frozen when disabled.

1

Clamp fine exposure

Off/On

1

If this bit is set and aec is enabled and the coarse

exposure has exceeded the clamp threshold, 16,

then the fine exposure will be clamped to 0.

2

3

Automatic gain control.

Off/On

1

0

Enables or disables automatic gain control. Cur-

rent gain value is frozen when disabled.

Enable immediate gain

update.

Allow manual change to gain to be applied imme-

diately.

Off/On

4

Enable immediate clock divi-

sion update.

0

Allow manual change to clock division to be

applied immediately.

Off/On

6:5 Data format select.

01

00 - 8 wire parallel output

01 - 4 wire parallel output

10 - 2 wire serial output

11 - 1 wire serial output

7

3/4 crystal clock

Off/On

0

Achieves clock division by 3 rather than 4.

Setup0 [001_0000 ]

2

Setup 1 [001_0001 ]

2

Setup 1 register controls registers that are less likely to be modified on a regular basis. The user should note

that the border pixels/lines can be disabled/enabled independently from the enabling/disabling of the custom

analogue horizontal shift register.

Bit

Function

Default

Comment

0

Enable additional black lines (3-8)

Off/On

0

If enabled extra black lines are visible at

device output

1

2

Enable border pixels

Off/On

0

Extends qualified image size to 164 x 124.

Default image size is 160 x 120

Enable horizontal shuffle mode.

Off/On

The contents of the horizontal shift register

are shuffled so that all the even columns then

all the odd columns are read out.

Setup1 [001_0001 ]

2

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VV5300 Sensor

Bit

Function

Default

Comment

3

Enable sample mode

Off/On

0

If enabled the data bus will continuously out-

put a “96_H” pattern. WIth the sensor in this

mode a user can determine the best point at

which to sample the data.

4

Status line data output enable.

Off/On

1

Enables the output of serial interface status

information on the data bus. By default the

bottom 64 locations from the serial interface

will be output.

5

6

8-bit or 4-bit ADC select

50fps timing/60fps timing

1

The analogue output ADC can be configured

to convert to 4-bit or 8-bit resolution.

The sensor will implement 60Hz like line

timing by default giving reduced flicker

operation with 60Hz source frequencies. If the

supply frequency is 50Hz then 50Hz like

timing should be selected.

7

External frame average

Off/On

0

Normally the accumulator arithmetic logic

calculates the frame average of the pixel

samples. However if this bit is enabled then

the user may specify a frame average.

Setup1 [001_0001 ]

2

Setup 2 [001_0010 ]

2

In many systems VV5300 will be continuously synchronised. During this synchronisation the video timing is

reset to a fixed point within the frame timing. The counter reset value is definable.

Bit

Function

Default

Comment

5:0 Pixel counter reset value.

011111₂

During synchronisation the pixel counter is

reset to the defined value.

6

7

Status information output option.

Off/On

0

Selects which system parameters are output

on status line. See table below.

Status information output option.

Off/On

Selects which system parameters are output

on status line. See table below.

Setup 2 [001_0010 ]

2

Register Address Range Register Address Range

Bit 7

Bit 6

8-bit modes

4-bit modes

0

1

0

1

0

00_H- 3F_H

40_H- 7F_H

-

00_H- 1F_H

20_H- 3F_H

40_H- 5F_H

Status line information options

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VV5300 Sensor

Register Address Range Register Address Range

Bit 7

Bit 6

1

8-bit modes

4-bit modes

1

-

60_H- 7F_H

Status line information options

Setup 3 [001_0011 ]

2

Bit

Function

Default

Comment

3:0 Exposure control mode

select.

1111₂

The average value for the frame that the

exposure controller uses can be calculated in

a number of different ways. See table below.

4

Autoload control

0

This bit controls the autoload feature._Note1

6:5 Exposure step size

01

Selects exposure step size. 1/8 for fast but

jerky convergence to 1/64 for slow but smooth

convergence. Default 1/16.

7

Unused

0

Setup 3 [001_0011 ]

2

Note1: The state of this pin can affect the autoload function in a number of ways.

1. If the autoload bit is high continuously and the autoload pin is also high then an autoload will not take place.

2. If the autoload bit is initially high and is then forced low then an autoload will take place regardless of the state of the

autoload pin.

3. If the autoload pin is initially high and is then forced low an autoload will take place regardless of the state of the

autoload bit.

4. A low to high transition on either the autoload bit or the autoload pin while VV5300 is running will have no effect on the

autoload function.

Bit 3 Bit 2 Bit 1 Bit 0

Function

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

bin1

bin2

bin3

bin4

(bin1 + bin2) / 2

(bin3 + bin4) / 2

(bin1 + bin3) / 2

(bin2 + bin4) / 2

(bin1 + bin4) / 2

(bin2 + bin3) / 2

Frame Average Options

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VV5300 Sensor

Bit 3 Bit 2 Bit 1 Bit 0

Function

1

0

1

0

1

(bin1 + bin2 + bin3 + bin4) / 4

Frame Average Options

Bit 6

Bit 5

Step size

Comment

Default

0

1

0

1

0

1

1/8

1/16

1/32

1/64

Exposure step size options

Setup 4 [001_0100 ]

2

The data output on the serial wire or the 4 wire/8 wire busses can be qualified, if required, by an internally

generated clock signal, QCK. This clock can be configured variously. Both a fast and a slow QCK can be

generated. If the former is selected then the falling edge of the clock will qualify the current data nibble/byte,

i.e. if the sensor is operating in 4 bit-4 wire mode then any true 8 bit data (e.g. line type code) will be qualified

on a nibble basis. If the slow QCK option is preferred then both edges of this clock are used to qualify the

current data nibble/byte.

The QCK function has a dedicated pin assigned, however by selecting the appropriate bits the FST pin can

also output QCK data. By default QCK is disabled. However by writing the appropriate message, QCK can

be forced to free run, qualify the embedded coding sequences and the visible data or the visible data only.

FST can also be enabled or disabled or alternatively the FST pin can output a timing signal to synchronise

several VV5300 sensors or finally the FST pin can output the state of the custom analogue block successive

approximation ADC output comparator.

Bit

Function

Default

Mode

1:0

FST/QCK pin mode.

00₂

FST pin

QCK pin

00₂

01₂

10₂

11₂

Normal FST

QCK_F

QCK_S

QCK_F

QCK_S

QCK_F

Inverted QCK_F

3:2

QCK mode select

00₂

01₂

10₂

11₂

disable

free running

validate control and image data

validate image data only

5:4

7:6

unused

00₂

FST mode select

00₂

01₂

10₂

11₂

disable FST

enable FST

synchronisation pulse output (SNO)

output ADC comparator output, CPO

Setup 4 [001_0100 ]

2

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VV5300 Sensor

Exposure Control Registers [010_0001 ] - [010_1001 ]

2

There is a set of parameters that control the time that the sensor pixels are exposed. The parameters are as

follows: fine and coarse exposure time, clock division control and finally gain control. The latter parameter

does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core.

An internal automatic algorithm will, if enabled, continually monitor the pixel output and then, if required, use

this data to correct the current exposure.

Manually changing the divisor applied to the incoming crystal clock can alter the effective integration of the

sensor. By slowing the internal clock down the integration period can be increased, i.e. halving the pixel clock

frequency will double the integration period.

If the user wishes to use the automatic exposure algorithm, the automatic exposure control (controlling fine

and coarse exposure) must be enabled. Additional gain control is optional. It is also possible to change the

gain manually via the serial interface even if the exposure is adjusted automatically.

If a user wishes to write an external value to one of the automatic exposure algorithm registers then it is

advised that the automatic control for that register be disabled prior to using the serial interface to write the

external value.

Note: The external exposure (coarse, fine or gain) values do not take effect immediately. Data from the serial

interface is read by the exposure algorithm at the start of a video frame. If the user reads an exposure value

via the serial interface then the value reported will be the data as yet unconsumed by the exposure algorithm,

because the serial interface logic locally stores all the data written to the sensor.

Between writing the exposure data and the point at which the data is consumed by the exposure algorithm,

bit 0 of the status register is set. The gain value is updated a frame later than the coarse and fine exposure

parameters. The gain is applied directly at the video output stage and does not require the long set up time

of the coarse and fine exposure settings.

The automatic exposure algorithm uses a set of exposure threshold settings. These thresholds may also be

modified by the user to alter the algorithm’s performance. The exposure algorithm uses these thresholds in

a histogram. The three thresholds divide the histogram into 4 regions, very overexposed, overexposed,

underexposed and very underexposed. The pixel data received from the sensor core is compared against

the thresholds to determine the accuracy of the current exposure setting. A series of flags are set to describe

the outcome of the histogram comparison and the new exposure setting can then be derived.

Each exposure parameter is subject to a maximum setting. The fine exposure setting can be clamped to a

fixed value regardless of the decision made by the automatic algorithm. The clamping will occur if the coarse

exposure setting exceeds a predetermined value and the clamping has been enabled via the serial interface.

Bit

Function

Default

Comment

7:0 Fine exposure value

0000_0000₂(00_H) maximum fine (50Hz mode) = FF_H

maximum fine (60Hz mode) = A8_H

Fine Exposure Value [010_0001 ]

2

Bit

Function

Default

Comment

7:0 Coarse exposure value

0111_0000₂(70_H) maximum coarse (50Hz and 60Hz modes)

91_H

Coarse Exposure Value [010_0011 ]

2

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VV5300 Sensor

Bit

Function

Default

Comment

2:0 Gain value

0

8 possible gain states can be written via the

serial interface

Gain Value [010_0100 ]

2

All 8 binary codes can be written to the core via the serial interface. Only the 4 thermometer codes

000,001,011 and 111 are selected by the automatic exposure algorithm. The 4 other codes are however still

valid and will be evaluated as detailed in the table below. It is clear, from the non-linear relationship between

the binary code and the actual gain applied at the analogue output stage, that care should be taken when

using non thermometer code gain settings. If the user writes a gain code of 110 (real gain = 1.600) and then

enables automatic gain control and the controller then decided to reduce the gain, the new gain value would

be 011 (real gain = 4.000) i.e. the effective applied gain at the analogue output stage has actually been

increased.

Gain binary code

Actual signal gain

000

001

010

011

100

101

110

111

1.000

2.000

1.333

4.000

1.143

2.667

1.600

8.000

System Gain

Bit

Function

Default

Comment

1:0 Clock divisor value

0

Pixel clock = Crystal clock ÷2ⁿ⁺¹

Clock Divisor Value [010_0101 ]

2

The undivided input crystal clock is used by the clock generator circuitry, elements of the serial interface and

a small number of other registers in the design. The remaining digital logic and the analogue circuitry, use

internally generated clocks, namely the pixel clock and the faster ADC clocks. These clocks are all slower

versions of the crystal clock. The ADC clocks may be up to half the crystal frequency, but can be further

divided by factors of 2, 4 or 8. The pixel clock is in turn slower than the ADC clock. If the ADC is operating in

4 bit mode then the pixel clock is 1/4 the frequency of the ADC clock, otherwise the pixel clock will be 1/8 the

frequency of the ADC clock.

Bit

Function

Default

Comment

2:0 Gain limit

7

Gain Limit[010_0110 ]

2

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VV5300 Sensor

Bit

Function

Default

Comment

7:0 Exposure lower threshold

85

Exposure Lower Threshold [010_0111 ]

2

Bit

Function

Default

Comment

7:0 Exposure centre threshold

100

Exposure Centre Threshold [010_1000 ]

2

Bit

Function

Default

Comment

7:0 Exposure higher threshold

115

Exposure Higher Threshold [010_1001 ]

2

Frame Average [111_0011 ]

2

The exposure controller normally compiles a frame average from the data received from the core. A complete

frame period is required to produce a frame average. This is clearly unacceptable for simulation and test

purposes. It is possible to manually force a frame average via the serial interface. This feature together with

the ability to curtail the frame duration will allow the behaviour of the exposure controller to be examined in

a realistic simulation period.

This register is read/write compatible

Bit

Function

Default

0

Comment

7:0

Frame average

Allow a synthetic frame average to be

written to and used by the exposure

controller

Frame Average [111_0011 ]

2

Digital Comparator Threshold [111_0101 ]

2

The ADC output from the CAB can be digitally compared against a digital threshold. This threshold is fully

programmable via the serial interface register. If the current ADC output is greater than or equal to the

programmed threshold then the modified ADC output will be forced to the full scale output. The full scale

value is mode dependent:- 224 for 8 bit ADC conversion or 14 for 4 bit conversion. If the current ADC output

is less than the threshold then the modified ADC output will be forced to minimum video. The minimum video

setting (the black level) is again mode dependent:- 16 for 8 bit ADC conversion or 1 for 4 bit conversion.

If this feature is not enabled, (tms[7] = 0), then the ADC output will pass unaltered.

As indicated above the ADC can convert to either 4 bit or 8 bit accuracy. When operating in a 4-bit mode the

threshold value should be packed to the 4 most significant bits of the register i.e. if the required threshold

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VV5300 Sensor

value is 10 then 160 should be written to the threshold register.

Bit

Function

Default

128

Comment

[7:0]

Threshold for digital comparator

The default has been set at the mid-

range video setting for 8 bit ADC

conversion. The user must repro-

gram the register if the test is run

when the ADC is converting to 4 bit

accuracy.

Digital Comparator Threshold [111_0101 ]

2

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VV5300 Sensor

Types of messages

This section gives guidelines on the basic operations to read data from and write data to the serial interface.

The serial interface supports variable length messages. A message may contain no data bytes, one data byte

or many data bytes. This data can be written to or read from common or different locations within the sensor.

The range of instructions available are detailed below.

• No data byte, only sets the index for a subsequent read message.

• Single location multiple data write or read for monitoring for real time control

• Multiple location, multiple data read or write for fast information transfers.

Examples of these operations are given below. A full description of the internal registers is given in the

previous section

For all examples the slave address used is 0010000₂=32₁₀for writing and 0010001₂=33₁₀for reading. This

corresponds to applying logical zero to both the sab0 and sab1 inputs.

Single location, single data write.

When a random value is written to the sensor, the message will look like this:

A

0101_0101

010_0000

0 0 1 0 0 0 0 0

0

S

P

In this example, the coarse (index = 0100000₂=32₁₀) exposure value has been written as 01010101₂. The r/

w bit is set to zero for writing and the inc bit is set to zero to disable automatic increment of the index after

writing the value. The location is preserved and may be used by a subsequent read.

Single location, single data read.

A read message always contains the index used to get the first byte.

010_0000

0101_0101

A

0

A

0 0 1 0 0 0 0 1

A

S

P

This example shows a coarse (index = 32₁₀) value of 0101_0101₂been read. Note that the read message is

terminated with a negative acknowledge (A) from the master: it is not guaranteed that the master will be able

to issue a stop condition at any other time during a read message. This is because if the data sent by the

slave is all zeros, the sda line cannot rise, which is part of the stop condition.

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VV5300 Sensor

No data write followed by same location read.

When a location is to be read, but the value of the stored index is not known, a write message with no data

byte must be written first, specifying the index. The read message then completes the message sequence.

To avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the

write and read messages. In this example, the gain value (index = 36₁₀) is read as 15₁₀:

No data write

A

Read index and data

36

A

32

33

10

15

A P

S

36

Sr

A 0

0

10

As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from

the master.

Same location multiple data write.

It may be desirable to write a succession of data to a common location. This is useful when the status of a

bit,(e.g. requesting a new black calibration), must be toggled.

The message sequence indexes setup1 register and initially turns ABC off. The next two data bytes then turn

ABC on and then finally off again, leaving it in the default state.

Toggle “Force Black Cal.”.

Write setup1

128

A

20

A

A P

S

0

A

0

10

2

0

10

16

10

Turn off ABC

Same location multiple data read

When an exposure related value (coarse, fine, acc or gain) is written, it takes effect on the output at the

beginning of the next video frame, (remember that the application of the gain value is a frame later than the

other exposure parameters). To signal the consumption of the written value, a flag is set when any of the

exposure or gain registers are written and is reset at the start of the next frame. This flag appears in status0

register and may be monitored by the bus master. To speed up reading from this location, the sensor will

repeatedly transmit the current value of the register, as long as the master acknowledges each byte read.

In the next example, a fine exposure value of 0 is written, the status register is addressed (no data byte) and

then constantly read until the master terminates the read message.

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VV5300 Sensor

Write fine with zero

Address the status0 reg.

20

A

20

A

22

0

A

0

A

S

0

A

16

Sr

16

10

Read continuously...

A

1

21

A

0

1

A

Sr

A

1

A

16

10

...until flag reset

A

0

P

A

1

Multiple location write

If the automatic increment bit is set, msb of the first data byte following the byte that contains the slave device

address, then it is possible to write data bytes to many adjacent internal registers. A write to the black

calibration parameters with their default values is shown in the following example.

.

Incremental write

32

A

20

A

96

A

P

S

1

8

A

16

10

16

Multiple location read

In the same manner, multiple locations can be read with a single read message. In this example the index is

written first, to ensure the exposure related registers are addressed and then all seven are read

No data write

A 1 32

Incremental read

33

32

A 1

Incremental read

gn_lim

coarse

A

32

Sr

A

S

10

fine

gain

A

Tc

T2

A

T1

A

P

Note that a stop condition is not required after the negative acknowledge from the master.

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VV5300 Sensor

Serial Interface Autoload

VVL_300 can be configured automatically at power-up with any user defined set of system parameters using

the serial interface auto-load feature. An external E²PROM is used to store the configuration data.

Both shortly after power up and in response to an off-sensor ‘soft’ reset on SIN, the auto-loader will

interrogate the E²PROM to determine whether or not valid data is present.

If no E²device is detected the auto-loader will shut-down and the serial interface register values will not be

changed from their existing values.

If, however, an E²device is detected, the auto-loader will begin to load data into the parameter registers from

starting from location zero in the E².

The first byte is a register header code which determines the destination of the following data byte. This

simple index & data format allows any sub-set of the VVL_300 registers map to be configured at power-up

and it allows them to be stored in the E²in any order.

If the auto-loader detects the ‘end-of-PROM-contents’ code 00h, it will then issue a STOP condition on the

serial interface, raise a flag to indicate that the parameters have been loaded and close down.

Header

ROM contents

ROM empty or end of data

00h

xxh

Parameter header into which the following byte is to be written.

2

E PROM header bytes

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VV5300 Sensor

Serial Interface Timing

stop

start

stop

SDA

SCL

...

tbuf

tlow tr

tf

thd;sta

thd;dat

thigh

tsu;dat

tsu;sta

tsu;sto

all values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V

Serial Interface Timing Characteristics

Parameter

Symbol

Min.

Max.

Unit

SCL clock frequency

fscl

0

***

-

kHz

us

Bus free time between a

tbuf

***

stop and a start

Hold time for a repeated

thd;sta

***

-

us

start

LOW period of SCL

HIGH period of SCL

tlow

thigh

***

-

us

Set-up time for a repeated

tsu;sta

start

Data hold time

thd;dat

tsu;dat

tr

***

-

us

ns

us

pF

Data Set-up time

-

Rise time of SCL, SDA

Fall time of SCL, SDA

Set-up time for a stop

***

-

tf

-

tsu;sto

Cb

***

-

Capacitive load of each

bus line (SCL, SDA)

***

Serial Interface Timing Characteristics

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VV5300 Sensor

EXAMPLE SUPPORT CIRCUIT

Vin

IC2

+8 to +12v dc

C1

C2

C3

R2

C5

R3

C6

R1

GND

0v

C17

C4

19 30 14

9

13

VDD

C18

37

40

AUTOLOADB

20

IC1

VSS1

VREG

29

35

VSS2

VSS3

(48 pin LCC)

28

27

26

25

24

D[0]

D[1]

D[2]

D[3]

D[4]

D[0]

D[1]

D[2]

D[3]

36

6

DVSS

AGND

R4

D[4]

D[5]

1

VRT

23

22

21

VV5300

D[5]

D[6]

D[7]

47

2

VCM/VREF2V5

VCDS

D[7]

C11

C12

C13

17

C7

QCK

FST

SIN

QCK

FST

SIN

16

15

45

VBLTW

VBG

C8

46

44

38

C9

CE

VBLOOM

3

4

TEST

C10

HPIX

Optional E²for configuration

autoload

31

32

34

33

R7

R8

C16

IC3

E²PROM

C17

8

7

6

5

C16

1

2

3

4

VCC

A0

A1

TEST

R5

R6

SCL

SDA

A2

SCL

SDA

GND

C15

C14

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VV5300 Sensor

Component

Part No. / Provisional Value

Rating / Notes

IC1

IC2

VV5300

7805

24C01

10.0 µF

0.1 µF

4.7 µF

100pF

22pF

1nF

VVL camera chip (48 pin LCC)

5V regulator

IC3

E2PROM SOIC (8 pin)

C3

C1,C2, C4-C11

C12, C13

C14, C15

C16, C17

C18

R1

0Ω

R2

0Ω

R3

0Ω

R4

33Ω

R5, R6

R7

2k2Ω

1MΩ

10Ω

R8

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VV5300 Sensor

VLSI VISION LIMITED

USA Eastern Office

UK Headquarters

USA Western Office

571 West Lake Avenue,

Suite 12,

BAY HEAD

NJ 08742 USA

Tel: +1 732 701 1101

Fax: +1 732 701 1102

Aviation House,

31 Pinkhill,

EDINBURGH

EH12 7BF

Scotland

Tel:+44 (0) 131 539 7111

1190 Saratoga Ave.,

Suite 180,

SAN JOSE

CA 95129 USA

Tel: +1 408 556 1550

Fax: +1 408 556 1564

Fax:+44 (0)131 539 7141

eMail: info@vvl.co.uk

VLSI Vision Ltd. reserves the right to make changes to its products and spec-

ifications at any time. Information furnished by VISION is believed to be accu-

rate, but no responsibility is assumed by VISION for the use of said informa-

tion, nor any infringements of patents or of any other third party rights which

may result from said use. No license is granted by implication or otherwise

under any patent or patent rights of any VISION group company.

VLSI Vision agent or distributor

cd34011-b.fm

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43

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