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OXFW900

型号：

OXFW900

描述：

IEEE1394到ATA / ATAPI本地桥[ IEEE1394 to ATA/ATAPI Native Bridge ]

品牌：

ETC[ ETC ]

页数：

30 页

PDF大小：

187 K

下载PDF手册
OXFW900  
IEEE1394 to ATA/ATAPI Native Bridge  
Data Sheet  
FEATURES  
·
S400 compliant 1394-1995 Link and Transaction  
layers  
·
ORB co-processor to accelerate translation of ORBs  
to ATAPI commands  
·
·
Compatible with 1394-1995 and 1394A Phys.  
Buffer Manager with max. RAM bandwidth of  
800Mbps  
Microsoft Win98-Second Edition, Win2000 and Apple  
MacOS 8.5 generic driver support  
SBP-2 Target Revision 4 compliant interface  
Fully ATA-4 compliant (see T13-1153D)  
Sustained IDE transfer rate of 25 Mbytes per second,  
Peak transfer rate of 50Mbytes per second.  
Supports PIO modes 0 to 4, DMA modes 0 to 2 and  
Ultra DMA modes 0 to 2  
·
·
Supports ORB chaining for increased performance  
High performance ATA command translation in  
firmware using Reduced Block Command (RBC) set  
Optional External Serial ROM interface for  
configuration data, user serial number, etc.  
Blank Flash memory programming feature via 1394  
bus  
3.3 Volts operation  
Low Power CMOS  
Firmware and Flash Programming Utilities supplied by  
Oxford Semiconductor  
ultra-thin 128-TQFP package (14mm x 14mm x 1mm )  
·
·
·
·
·
·
·
·
·
·
·
Integrated 32-bit RISC processor (ARM7TDMI) with  
on-chip scratch RAM  
·
DESCRIPTION  
The OXFW900 is  
a high-performance 1394 to  
ATA/ATAPI (IDE) native bridge with an integrated target  
Serial Bus Protocol (SBP-2 ) controller. By supporting  
the SBP-2 protocol, the device can use generic SBP-2  
drivers available in the Microsoft Windows 98SE, Microsoft  
Windows 2000, Microsoft Millennium and Apple MacOS  
operating systems.  
The Buffer Manager has a RAM bandwidth of 800Mbps. It  
provides storage for 1394 and ATA/ATAPI packets,  
automatically storing them and passing them to the  
appropriate destinations, without any intervention from the  
processor. It also provides storage and manages the  
sequencing of ORB fetching to reduce latency and improve  
data throughput.  
The device is ideally suited for smart-cable or tailgate  
interface applications for removable-media drives, compact  
flash card readers, CD-ROM, CD-R, CD-RW, DVD-ROM,  
DVD-RAM and hard disk drives, allowing IDE drives to be  
connected to a 1394 serial bus in a plug-and-play fashion.  
Both ATA and ATAPI devices are supported using the  
same firmware.  
The configuration data including the IEEE OUI  
(Organisational Unique Identifier) and device serial number  
is stored in the Flash ROM which may be uploaded from  
the 1394 bus, even when blank. The device also facilitates  
firmware uploads from the 1394 bus.  
The ORB co-processor translates ORBs as defined in the  
SBP-2 protocol into ATA/ATAPI commands, and  
automatically stores error/status messages at an address  
specified by the host.  
This highly integrated device offers a three-chip solution to  
native bridge applications using an external 1394 PHY and  
Flash ROM. A slow 32Kx8 Flash ROM (up to 120ns) is  
sufficient for most optical media applications. For  
applications that need a sustained data rate in excess of  
10Mbytes per second, for example high performance disk  
drives, an 8-bit 50ns FLASH or faster is recommended.  
The device is compatible with both 1394-1995 and 1394A  
PHYs.  
Concurrent operation of the ATA/ATAPI and 1394  
interfaces are facilitated using the high throughput Buffer  
Manager where LINK, ATAPI manager and ARM7TDMI  
can perform interleaved accesses to the on-chip RAM  
buffer. The high performance processor ensures that no  
significant latency is incurred. The ATA command  
translation is performed in firmware to meet RBC (Reduced  
Block Commands) standard, T10-1228D. The ATA/ATAPI  
Manager supports PIO modes 0 to 4, DMA modes 0 to 2  
and Ultra DMA mode 0 to 2 and provides the interface to  
the IDE bus. It is compliant with T13-1153D, ATA-4  
specification.  
The LINK controller complies with S400 1394-1995  
specification. The 1394 transaction layer and SBP-2  
protocol is implemented using a combination of the  
ARM7TDMI (low-power 32-bit RISC processor), an ORB  
(Operational Request Block) hardware co-processor and a  
high performance buffer manager.  
Oxford Semiconductor Ltd.  
69 Milton Park, Abingdon, Oxon, OX14 4RX, UK  
Tel: +44 (0)1235 824900  
Ó Oxford Semiconductor 1999  
OXFW900 Data Sheet Revision 1.0 – Nov 1999  
Part No. OXFW900-TQ-A  
Fax: +44(0)1235 821141  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
CONTENTS  
FEATURES..........................................................................................................................................................1  
DESCRIPTION.....................................................................................................................................................1  
CONTENTS..........................................................................................................................................................2  
1
2
3
4
BLOCK DIAGRAM ......................................................................................................................................3  
PIN INFORMATION.....................................................................................................................................4  
PIN DESCRIPTIONS ...................................................................................................................................5  
OPERATING CONDITIONS........................................................................................................................7  
5
5.1  
DC ELECTRICAL CHARACTERISTICS....................................................................................................7  
I/O BUFFERS..........................................................................................................................................................7  
6
AC ELECTRICAL CHARACTERISTICS....................................................................................................8  
IDE INTERFACE .....................................................................................................................................................8  
1394 LINK-PHY INTERFACE ................................................................................................................................ 11  
EXTERNAL PROCESSOR INTERFACE................................................................................................................ 12  
6.1  
6.2  
6.3  
7
8
9
TIMING WAVEFORMS..............................................................................................................................13  
PACKAGE INFORMATION.......................................................................................................................27  
ORDERING INFORMATION .....................................................................................................................28  
NOTES ...............................................................................................................................................................29  
CONTACT DETAILS.........................................................................................................................................30  
DISCLAIMER.....................................................................................................................................................30  
Data Sheet Revision 1.0  
Page 2  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
1 BLOCK DIAGRAM  
Buffer RAM  
PD[7:0]  
IDE_OE#  
RTS[3:0]#  
ID[15:0]  
CTL[1:0]  
RAM  
Manager  
PHY_CLK  
LINK_ON  
LPS  
Link-Phy  
interface  
DMARQ  
DIOW#  
DIOR#  
IORDY  
ATA/  
ATAPI  
manager  
LREQ  
DMACK#  
INTRQ#  
IA[2:0]  
D[15:0]  
A[16:0]  
IDE_CS#[2:0]  
ORB Co-  
processor  
CS#[3:0]  
External  
ROM  
interface  
OE#  
WE#  
BWE#[1:0]  
WIDTH16  
INT#  
ARM7TDMI  
XTALO  
XTALI  
Clock  
generator  
CKIN  
CKOUT  
EE_DO  
EE_DI  
SCRATCH  
RAM  
EEPROM  
interface  
EE_CK  
EE_CS  
Figure 1: OXFW900 Block Diagram  
Data Sheet Revision 1.0  
Page 3  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
2 PIN INFORMATION  
IA1  
IA0  
IA2  
97  
98  
99  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
IRESET  
IDE_OE#  
WIDTH16  
INT#  
A0  
VDD  
XTLO  
XTLI  
CKIN  
GND  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
VDD  
GND  
A8  
ICS0#  
ICS1#  
LINKON  
LPS  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
PD7  
PD6  
GND  
GND  
PD5  
PD4  
PD3  
PD2  
5VBIAS  
CKOUT  
VDD  
PD1  
PD0  
CTL1  
CTL0  
GND  
A9  
A10  
A11  
A12  
OXFW900-TQ-A  
PHYCLK  
VDD  
A13  
LREQ  
FORCE#  
TEST0  
TEST1  
GPO1  
GPO2  
GPO3  
GND  
5VBIAS  
A14  
A15  
A16  
WE#  
BWR0#  
Figure 2: Pinout (package = 128 TQFP)  
Data Sheet Revision 1.0  
Page 4  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
3 PIN DESCRIPTIONS  
1394 PHY-LINK interface  
104, 105, 108, 109, 110, 111, 115,  
Dir1  
I/O  
Name  
PD[7:0]  
Description  
Phy-Link Data Bus  
116  
117,118  
120  
122  
102  
I/O  
I
O
IU  
O
CTL[1:0]  
PHYCLK  
LREQ  
LINKON  
LPS  
Phy-Link Control Bus  
49.152 MHz clock sourced by PHY  
Link Request  
Requests link to power up when in a low power mode  
Indicates to phy that link is powered and ready  
103  
ARM external interface  
2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14,  
15, 18, 19, 20, 21  
35, 36, 37, 40, 41, 42, 43, 44, 45,  
48, 49, 50, 51, 52, 53, 54, 60  
25, 26, 29, 30  
T_I/O D[15:0]  
T_O A[16:0]  
T_O CS#[3:0]  
T_O OE#  
ARM external data bus  
ARM external address bus  
ARM external chip selects. CS0# is always used for program  
ROM.  
ARM external output enable. Active when reading data from  
external devices including program ROM  
Byte Write enables. For future expansion  
Write Enable. Active when writing to external devices  
31  
32, 33  
34  
T_O BWR#[1:0]  
T_O WE#  
62  
ID  
WIDTH16  
‘1’ = 16 bit external ROM  
(pulldown)  
‘0’ = 8 bit external ROM  
61  
IDE interface  
65, 66, 69, 70, 71, 72, 73, 74, 77,  
78, 79, 80, 81, 82, 85, 86  
97, 98, 99  
T_IU INT#  
External ARM interrupt  
T_I/O ID[15:0]  
IDE data bus  
T_O IA[2:0]  
IDE address bus  
100, 101  
T_O ICS#[1:0]  
T_O IDE_OE#[  
IDE chip select. Selects IDE drive 0 or 1  
IDE output enable. Only used when external buffering is  
required to drive IDE data bus  
63  
64  
T_O IRESET  
IDE interface reset  
89  
T_I  
DMARQ  
90  
91  
92  
95  
T_O DIOW#  
T_O DIOR#  
T_O IORDY  
T_O DMACK#  
IDE interface write strobe  
IDE interface read strobe  
96  
T_I  
INTRQ  
EEPROM interface  
128  
126  
1
O
O
IU  
O
GPO3  
GPO1  
GPI  
General Purpose Output 3  
General Purpose Output 1  
General Purpose Input  
127  
Miscellaneous Pins  
57  
GPO2  
General Purpose Output 2  
I
XTLI  
Crystal Oscillator input. 24.576 MHz crystal required. If a  
clock module is used rather than a crystal then this input  
must be tied high for the OXFW900 to operate, and the clock  
module output connected to the CKIN pin. IMPORTANT -  
See Application Notes regarding clocking  
58  
O
XTLO  
Crystal Oscillator output. IMPORTANT – See Application  
Notes regarding clocking.  
Data Sheet Revision 1.0  
Page 5  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
56  
I
CKIN  
Direct clock input. Used in conjunction with an external  
crystal oscillator of 24.576MHz. If a crystal is connected to  
XTLI and XTLO this input must be tied low for the OXFW900  
to operate. Mark space ratio of crystal oscillator must be  
45:55 or better. IMPORTANT – Please refer to Application  
Notes regarding clocking  
23  
IU  
RESET#  
Global reset for the OXFW900. Active Low.  
113  
T_O CKOUT  
Clock output. 24.576 MHz clock output. IMPORTANT –  
Please refer to Application Notes regarding clocking  
This input is used to allow the OXFW900 to reprogram a  
flash which has been loaded with a bad program. A bad  
program is defined as one that does not have the correct  
interlocking mechanism for reprogramming flash. This pin  
forces the ARM watchdog timer to trigger thus allowing the  
flash to be reprogrammed over the 1394 bus as if the flash  
were blank.  
123  
IU  
FORCE#  
124, 125  
IU  
TEST[1:0]  
‘11’ = NORMAL OPERATION. These pins have internal  
pullup resistors and must be left unconnected. Other settings  
are for foundry test purposes only.  
Power and ground2  
28, 47, 94, 114  
3V3  
3V3  
3.3V AC VDD  
3.3V DC VDD  
Supplies power to output buffers in switching (AC) state  
Power supply. Supplies power to core logic, input buffers  
and output buffers in steady state  
17, 24, 59, 84, 88, 121  
9, 38, 76, 112  
5V  
5V BIAS VDD  
Supplies 5V reference bias to all 5V tolerant I/O. All four  
MUST be connected to 5V rail.  
8, 27, 46, 67, 75, 93, 106  
16, 22, 39, 55, 68, 83, 87, 107, 119  
G
G
AC GND  
DC GND  
Supplies GND to output buffers in switching (AC) state  
Ground (0 volts). Supplies GND to core logic, input buffers  
and output buffers in steady state  
Table 1: Pin Descriptions  
Note 1: Direction key:  
I
Input  
T_O  
5V tolerant output  
IU  
ID  
O
Input with internal pull-up  
Input with external pull-down  
Output  
T_I/O  
5V tolerant bi-directional  
I/O  
Bi-directional  
G
Ground  
3V3  
5V  
3.3V power  
5V bias power  
T_I  
5V tolerant input  
Note 2: Power & Ground  
There are two GND and three VDD rails internally. One set of rails supply power and ground to output buffers while in switching  
state (called AC power) and another rail supply the core logic, input buffers and output buffers in steady-state (called DC rail). A  
third rail provides 5V bias voltage to 5V tolerant IO.  
The rails are not connected internally. This precaution reduces the effects of simultaneous switching outputs and undesirable RF  
radiation from the chip.  
Data Sheet Revision 1.0  
Page 6  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
Configuration & Operation  
4 OPERATING CONDITIONS  
Symbol  
VDD  
VIN  
IIN  
TSTG  
Parameter  
Min  
-0.3  
-0.3  
Max  
4.6  
VDD + 0.3  
+/- 10  
125  
Units  
V
V
mA  
°C  
DC supply voltage  
DC input voltage  
DC input current  
Storage temperature  
-40  
Table 2: Absolute maximum ratings  
Symbol  
VDD  
VBB  
Parameter  
Min  
3.0  
4.75  
0
Max  
3.6  
5.25  
70  
Units  
V
V
DC supply voltage  
5V PMOS bulk bias  
Temperature  
TC  
°C  
Table 3: Recommended operating conditions  
5 DC ELECTRICAL CHARACTERISTICS  
5.1 I/O Buffers  
Symbol Parameter  
Condition  
Commercial  
CMOS Interface  
CMOS Schmitt trig  
CMOS Interface 1  
CMOS Schmitt trig  
Min  
3.0  
0.7 x Vdd  
2.1  
Max  
3.6  
Units  
V
V
VDD  
VIH  
Supply voltage  
Input high voltage  
VIL  
Input low voltage  
0.3 x Vdd  
V
0.8  
5.0  
10.0  
10  
CIL  
COL  
IIH  
Cap of input buffers  
pF  
pF  
mA  
mA  
V
V
V
V
mA  
Cap of output buffers  
Input high leakage current  
Input low leakage current  
Output high voltage  
Output high voltage  
Output low voltage  
Vin = VDD  
Vin = VSS  
-10  
-10  
IIL  
10  
VDD – 0.05  
VOH  
VOH  
VOL  
VOL  
IOZ  
IOH = -1 mA  
IOH = -1mA to –24mA  
IOL = 1 mA  
IOL = 1mA to 24mA  
2.4  
0.05  
0.4  
10  
Output low voltage  
3-state output leakage current  
-10  
Symbol Parameter  
Operating supply current in  
Condition  
Typical  
Max  
Units  
normal mode  
ICC  
mA  
Operating supply current in  
Power-down mode  
Table 4: Characteristics of OXFW900 I/O buffers  
Data Sheet Revision 1.0  
Page 7  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
6 AC ELECTRICAL CHARACTERISTICS  
6.1 IDE interface  
Symbol Parameter  
Mode 0  
600  
80  
Mode 1  
400  
80  
Mode 2  
360  
40  
Mode 3  
200  
40  
Mode 4  
120  
40  
Units  
ns  
ns  
t0  
t1  
Cycle Time  
Address Valid to DIOR# / DIOW#  
setup  
t2  
t2i  
t3  
t4  
t5  
t6  
t6z  
t9  
DIOR# / DIOW# pulse width  
DIOR# / DIOW# recovery time  
DIOW# data setup (min )  
320  
-
60  
40  
50  
5
320  
-
45  
40  
35  
5
320  
-
30  
40  
20  
5
80  
80  
30  
40  
20  
5
80  
40  
20  
40  
20  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DIOW# data hold  
DIOR# data setup ( min )  
DIOR# data hold ( min )  
DIOR# data tristate (max )  
DIOR# / DIOW# to address valid  
hold  
30  
40  
30  
40  
30  
40  
30  
40  
30  
40  
tRD  
Read Data Valid to IORDY active if  
IORDY initially low after tA  
0
0
0
0
0
ns  
tA  
tB  
tA  
IORDY Setup time  
IORDY Pulse Width ( max )  
IORDY assertion to release  
35  
1250  
5
35  
1250  
5
35  
1250  
5
35  
1250  
5
35  
1250  
5
ns  
ns  
ns  
Table 5: OXFW900 IDE PIO / Register Transfers  
Data Sheet Revision 1.0  
Page 8  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
Symbol Parameter  
Mode 0  
480  
240  
150  
5
100  
20  
0
20  
80  
240  
120  
40  
Mode 1  
160  
80  
60  
5
30  
15  
0
Mode 2  
Units  
t0  
tD  
tE  
Cycle time  
DIOR# / DIOW#  
DIOR# data access ( max )  
DIOR# data hold ( min )  
120  
80  
50  
5
20  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tF  
tG  
tH  
tI  
DIOR# / DIOW# data setup  
DIOW# data hold  
DMACK to DIOR# / DIOW# setup ( min )  
DIOR# / DIOW# to DMACK hold ( min )  
DIOR# negated pulse width  
DIOW# negated pulse width  
DIOR# to DMARQ delay ( max )  
DIOW# to DMARQ delay ( max )  
IDCS[1:0] valid to DIOR# / DIOW#  
IDCS[1:0] hold  
tJ  
5
5
tKr  
tKw  
tLr  
tLw  
tM  
tN  
tZ  
80  
80  
40  
40  
40  
40  
25  
40  
40  
35  
35  
40  
40  
25  
80  
40  
20  
DMACK to tristate ( max )  
Table 6: OXFW900 Multiword DMA timings  
Data Sheet Revision 1.0  
Page 9  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
Symbol Parameter  
Mode 0 Mode 0 Mode 1 Mode1 Mode 2 Mode 2 Units  
min  
max  
min  
max  
min  
max  
t2cyc  
tcyc  
Typical sustained average two  
cycle time  
240  
160  
120  
ns  
ns  
ns  
Cycle time allowing for clock  
variations ( refer to ATA spec)  
Two cycle time allowing for clock  
variations ( refer to ATA spec )  
Data setup time at recipient  
Data hold time at recipient  
Data valid setup time at sender  
(from data bus being valid until  
STROBE edge )  
114  
235  
75  
55  
t2cyc  
156  
117  
tds  
tdh  
tdvs  
15  
5
70  
10  
5
48  
7
5
34  
ns  
ns  
ns  
tdvh  
tfs  
Data valid hold time at sender (from  
STROBE edge until data may  
become invalid  
First STROBE time (for device to  
first negate DSTROBE from STOP  
during a data-in burst)  
Limited interlock time  
Interlock time with minimum  
Unlimited interlock time  
6
0
6
0
6
0
ns  
ns  
230  
150  
10  
200  
150  
10  
170  
150  
10  
tli  
tmli  
tui  
0
20  
0
0
20  
0
0
20  
0
ns  
ns  
ns  
ns  
taz  
Maximum time allowed for output  
drivers to release (from being  
asserted or negated)  
tzah  
tzad  
Minimum delay time required for  
output drivers to assert or negate  
(from released state)  
Envelope time ( from DMACK# to  
STOP and HDMARDY# during  
data-out burst initiation  
STROBE to DMARDY time ( refer  
to ATA spec  
Ready-to-final-STROBE time ( no  
STROBE edges shall be sent this  
long after the negation of  
DDMARDY#  
20  
0
20  
0
20  
0
ns  
ns  
tenv  
20  
20  
70  
75  
20  
25  
70  
60  
20  
25  
70  
50  
tsr  
ns  
ns  
trfs  
trp  
Ready-to-pause time ( time that  
recipient shall wait to initiate pause  
after negating DMARDY# )  
Pull-up time before allowing IORDY  
to be released  
160  
125  
100  
ns  
tiordyz  
tziordy  
tack  
20  
20  
20  
ns  
ns  
ns  
ns  
Minimum time a device shall wait  
before driving IORDY  
0
0
0
Setup and hold times for DMACK#  
(before assertion or negation )  
Time from STROBE edge to  
negation of DMARQ or assertion of  
STOP (when sender terminates a  
burst )  
20  
50  
20  
50  
20  
50  
tss  
Table 7: OXFW900 Ultra DMA timings  
Data Sheet Revision 1.0  
Page 10  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
6.2 1394 Link-Phy interface  
The timings for 1394 Link – Phy are shown below :  
Symbol Parameter  
Min  
6
0
Max  
Units  
ns  
ns  
tlsu  
tlh  
Tld1  
Setup Time, PD[7:0] and CTL[1:0] before PhyClk  
Hold Time, PD[7:0] and CTL[1:0] after PhyClk  
Delay Time, PhyClk input high to initial instance of PD[7:0], CTL[1:0]  
and Lreq outputs valid  
TBD  
TBD  
TBD  
TBD  
ns  
Tld2  
Tld3  
Delay Time, PhyClk input high to subsequent instance(s) of PD[7:0],  
CTL[1:0] and Lreq outputs valid  
Delay Time, PhyClk input high to PD[7:0], CTL[1:0] and Lreq outputs  
invalid (high impedance)  
TBD  
TBD  
ns  
ns  
Table 8: OXFW900 Link-Phy interface timings  
Data Sheet Revision 1.0  
Page 11  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
6.3 External Processor Interface  
Name  
Description  
min (ns)  
typ (ns)  
max (ns)  
Common Timings  
-
-
-
tas  
tcss  
tws  
taddr1  
taddr2  
Address valid to CSx# and OE# falling  
CSx# and OE# falling to WE# or IOR# falling  
Wait State Additional Delay  
Not Last Address Valid  
Last Address Valid  
Common Read Timings  
IOR# valid  
Address hold after CSx# or OE# rising  
Single Access Read Timings  
0.3  
16  
0
2.5  
18.5  
600  
0
-
-
-
-
tiorl  
tah  
-
-
tdsa  
tdha  
tdsb  
tdhb  
Data valid and stable to CSx# and OE# rising  
Data hold after CSx# and OE# rising  
Data valid and stable to IOR# rising  
Data hold after IOR# rising  
0
0
-
Multiple Access Read Timings  
Data valid and stable to CSx# and OE# rising (not last access)  
Data hold after CSx# and OE# rising (not last access)  
Data valid and stable to IOR# rising (not last access)  
Data hold after IOR# rising (not last access)  
Data valid and stable to CSx# and OE# rising (last access)  
Data hold after CSx# and OE# rising (last access)  
Data valid and stable to IOR# rising (last access)  
Data hold after IOR# rising (last access)  
IOR# rising to next address valid  
Address valid to IOR# falling  
-
-
dsa1  
dha1  
dsb1  
dhb1  
dsa2  
dha2  
dsb2  
dhb2  
tahr  
0
0
0
0
tasr  
tiorh  
IOR# inactive between reads  
Common Write Timings  
-
-
-
tds  
Data valid to WE# rising  
39+tws  
tdh  
Data hold after WE# rising  
CS# hold after WE# rising  
CS# hold after Address invalid  
WE# valid  
13  
20  
1
17  
2.5  
tcsh  
tcsa  
twel  
Single Access Write Timings  
Address hold after WE# rising  
-
19  
-
-
-
-
60  
-
tah  
Multiple Access Write Timings  
Address valid to CSx# and OE# falling  
Address hold after WE# rising (not last access)  
WE# falling after next address valid  
Address hold after WE# rising (last access)  
WE# inactive between writes  
tas1  
tah1  
tas2  
tah2  
tweh  
Table 9: External Processor Interface timings  
All timings are preliminary and are subject to change  
Data Sheet Revision 1.0  
Page 12  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
7 TIMING WAVEFORMS  
t0  
ADDR valid  
t2  
t9  
t1  
t2i  
DIOR# /  
DIOW#  
t3  
t4  
ID[7:0]  
(WRITE)  
t6z  
t5  
t6  
ID[7:0]  
(READ)  
IORDY  
(Note1)  
tA  
tC  
IORDY  
(Note2)  
tRD  
IORDY  
(Note3)  
tC  
tB  
Figure 3: PIO / Register Transfer to / from IDE device  
Notes : Negation of IORDY by the drive is used to extend the PIO cycle. The determination of whether the cycle is to be  
extended is made by the host after tA from the Assertion of DIOR# or DIOW#. The assertion and negation of IORDY are  
described in the following three cases : -  
1) Device never negates IORDY and no wait is generated.  
2) Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and  
may be asserted for no more than 5ns before release : no wait generated.  
3) Device negated IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5ns before  
release : wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR#  
is asserted, the device shall place read data on DD[7:0] for tRD before asserting IORDY  
Data Sheet Revision 1.0  
Page 13  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
TIMING WAVEFORMS  
CS0# / CS1#  
tM  
tN  
t0  
DMARQ  
tL  
DMACK#  
tI  
tD  
tK  
tJ  
DIOR# / DIOW#  
tE  
tZ  
READ ID[15:0]  
WRITE ID[15:0]  
tG  
tF  
tG  
tH  
Figure 4: MultiWord DMA transfer to / from IDE device  
Data Sheet Revision 1.0  
Page 14  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ  
(device)  
tui  
tenv  
tfs  
tack  
DMACK(host)  
tzad  
STOP(host)  
(DIOW#)  
HDMARDY(host)  
(DIOR#)  
tziordy  
DSTROBE(device)  
(IORDY)  
tdvs  
tdvh  
taz  
ID[15:0]  
tack  
IA[2:0], ICS#[1:0]  
Figure 5: Initiating an Ultra DMA data-in burst  
Data Sheet Revision 1.0  
Page 15  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
t2cyc  
tdvh  
tcyc  
tcyc  
DSTROBE(device)  
(IORDY)  
tdvh  
tdvh  
tdvs  
tdvs  
ID[15:0]  
(device)  
DSTROBE(host)  
IORDY  
tds  
tdh  
tdh  
tds  
tdh  
ID[15:0] (host)  
Figure 6: Sustained Ultra DMA data-in burst  
Data Sheet Revision 1.0  
Page 16  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ(device)  
DMACK(host)  
trp  
STOP(host)  
DIOW#  
tsr  
DSTROBE(device)  
IORDY  
trfs  
DSTROBE(device)  
IORDY  
ID[15:0] (host)  
Figure 7: Host pausing an Ultra DMA data-in burst  
Data Sheet Revision 1.0  
Page 17  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ(device)  
DMACK(host)  
tli  
tli  
tmli  
STOP(host)  
DIOW#  
tack  
HDMARDY(host)  
DIOR#  
tss  
tiordyz  
DSTROBE(device)  
IORDY  
tzah  
taz  
CRC  
ID[15:0] (host)  
tack  
IA[2:0],  
ICS[1:0]  
Figure 8: Device terminating an Ultra DMA data-in burst  
Data Sheet Revision 1.0  
Page 18  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ(device)  
DMACK(host)  
tzah  
trp  
taz  
STOP(host)  
DIOW#  
tack  
HDMARDY(host)  
DIOR#  
trfs  
tli  
tmli  
tiordyz  
DSTROBE(device)  
IORDY  
tdvs  
tdvh  
CRC  
ID[15:0] (host)  
tack  
IA[2:0],  
ICS[1:0]  
Figure 9: Host terminating an Ultra DMA data-in burst  
Data Sheet Revision 1.0  
Page 19  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ  
(device)  
tui  
tenv  
tack  
DMACK(host)  
tli  
tui  
STOP(host)  
(DIOW#)  
HSTROBE(host)  
(DIOR#)  
tziordy  
DDMARDY(device)  
(IORDY)  
tdvs  
tdvh  
ID[15:0]  
tack  
IA[2:0], ICS#[1:0]  
Figure 10: Initiating an Ultra DMA data-out burst  
Data Sheet Revision 1.0  
Page 20  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
t2cyc  
tdvh  
tcyc  
tcyc  
HSTROBE(host)  
tdvh  
tdvh  
tdvs  
tdvs  
ID[15:0] (host)  
HSTROBE(device)  
tds  
tdh  
tdh  
tds  
tdh  
ID[15:0]  
(device)  
Figure 11: Sustained Ultra DMA data-out burst  
Data Sheet Revision 1.0  
Page 21  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ(device)  
DMACK(host)  
trp  
STOP(host)  
DIOW#  
tsr  
DDMARDY(device)  
IORDY#  
trfs  
HSTROBE(host)  
DIOR#  
ID[15:0] (host)  
Figure 12: Device pausing an Ultra DMA data-in burst  
Data Sheet Revision 1.0  
Page 22  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
DMARQ(device)  
DMACK(host)  
tli  
tli  
tmli  
STOP(host)  
DIOW#  
tack  
DDMARDY(device)  
IORDY#  
tiordyz  
tss  
HSTROBE(host)  
DIOR#  
tdvs tdvh  
ID[15:0] (host)  
CRC  
tack  
IA[2:0],  
ICS[1:0]  
Figure 13: Host Terminating an Ultra DMA data-out burst  
Data Sheet Revision 1.0  
Page 23  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
tli  
DMARQ(device)  
DMACK(host)  
trp  
STOP(host)  
DIOW#  
tack  
DDMARDY(device)  
IORDY#  
trfs  
tli  
tmli  
tiordyz  
HSTROBE(device)  
DIOR#  
tdvs  
tdvh  
CRC  
ID[15:0] (host)  
tack  
IA[2:0],  
ICS[1:0]  
Figure 14: Device Terminating an Ultra DMA data-out burst  
Data Sheet Revision 1.0  
Page 24  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
CLK  
1
2
3
4
PD[7:0]  
CTL[1:0]  
LReq  
tlsu  
tlh  
Figure 15: Phy to Link timings  
CLK  
1
2
3
4
PD[7:0]  
CTL[1:0]  
LReq  
tld1  
tld2  
tld3  
Figure 16: Link to Phy timings  
Data Sheet Revision 1.0  
Page 25  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
tws  
Address  
Data  
tdsb  
tdhb  
tas  
tcss  
tdsa  
tdha  
CS#  
OE#  
tah  
WE#  
IOR#  
tiorl  
taddr1  
dsb1  
taddr2  
Address  
Data  
dhb1  
dsb2  
dhb2  
tastcss  
dsa1  
dha1  
dsa2  
dha2  
CS#  
tah  
OE#  
WE#  
tahr  
tasr  
tiorl  
tws  
tiorl  
IOR#  
tiorh  
tws  
Figure 17: External Processor Bus timings  
Data Sheet Revision 1.0  
Page 26  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
8 PACKAGE INFORMATION  
Figure 18: 128 TQFP package information  
Data Sheet Revision 1.0  
Page 27  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
9 ORDERING INFORMATION  
OXFW900-TQ - A  
Revision  
Package Type – 128 TQFP  
Data Sheet Revision 1.0  
Page 28  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
NOTES  
This page has been intentionally left blank  
Data Sheet Revision 1.0  
Page 29  
OXFW900  
OXFORD SEMICONDUCTOR LTD.  
CONTACT DETAILS  
Oxford Semiconductor Ltd.  
69 Milton Park  
Abingdon  
Oxfordshire  
OX14 4RX  
United Kingdom  
Telephone:  
Fax:  
Sales e-mail:  
+44 (0)1235 824900  
+44 (0)1235 821141  
sales@oxsemi.com  
1394 Tech support e-mail: 1394_support@oxsemi.com  
Web site:  
http://www.oxsemi.com  
DISCLAIMER  
Oxford Semiconductor believes the information contained in this document to be accurate and reliable. However, it is subject to  
change without notice. No responsibility is assumed by Oxford Semiconductor for its use, nor for infringement of patents or other  
rights of third parties. No part of this publication may be reproduced, or transmitted in any form or by any means without the prior  
consent of Oxford Semiconductor Ltd. Oxford Semiconductor’s terms and conditions of sale apply at all times.  
Data Sheet Revision 1.0  
Page 30  
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