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2SK3210STL

型号：

2SK3210STL

描述：

硅N沟道MOS FET高速电源开关[ Silicon N Channel MOS FET High Speed Power Switching ]

品牌：

RENESAS[ RENESAS TECHNOLOGY CORP ]

页数：

9 页

PDF大小：

156 K

下载PDF手册
2SK3210(L), 2SK3210(S)  
Silicon N Channel MOS FET  
High Speed Power Switching  
REJ03G0414-0300  
(Previous ADE-208-760A (Z))  
Rev.3.00  
Sep. 30, 2004  
Features  
•
Low on-resistance  
RDS = 40 mΩ typ.  
•
•
High speed switching  
4 V gate drive device can be driven from 5 V source  
Outline  
LDPAK  
D
4
4
1. Gate  
2. Drain  
3. Source  
4. Drain  
G
1
2
3
1
2
3
S
Absolute Maximum Ratings  
(Ta = 25°C)  
Item  
Drain to source voltage  
Gate to source voltage  
Drain current  
Drain peak current  
Body-drain diode reverse drain current  
Avalanche current  
Avalanche energy  
Channel dissipation  
Channel temperature  
Storage temperature  
Symbol  
VDSS  
VGSS  
ID  
Ratings  
Unit  
150  
±20  
30  
120  
30  
30  
67  
100  
150  
V
V
A
A
A
ID (pulse)Note1  
IDR  
Note3  
IAP  
A
Note3  
EAR  
mJ  
W
°C  
°C  
PchNote2  
Tch  
Tstg  
–55 to +150  
Notes: 1. PW ≤ 10ms, duty cycle ≤ 1 %  
2. Value at Tc = 25°C  
3. Value at Tch = 25°C, Rg ≥ 50 Ω  
Rev.3.00 Sep. 30, 2004 page 1 of 8  
2SK3210(L), 2SK3210(S)  
Electrical Characteristics  
(Ta = 25°C)  
Item  
Symbol  
V(BR)DSS  
V(BR)GSS  
IGSS  
Min  
150  
±20  
—
—
1.0  
—
—
18  
—
—
—
—
—
—
—
—
—
Typ  
—
—
—
—
—
40  
45  
30  
2600  
820  
350  
25  
180  
600  
280  
0.91  
110  
Max  
—
—
±10  
10  
2.5  
45  
63  
—
—
—
—
—
Unit  
V
V
µA  
µA  
V
mΩ  
mΩ  
S
pF  
pF  
pF  
ns  
ns  
ns  
ns  
V
Test Conditions  
Drain to source breakdown voltage  
Gate to source breakdown voltage  
Gate to source leak current  
Zero gate voltage drain current  
Gate to source cutoff voltage  
ID = 10 mA, VGS = 0  
IG = ±100 µA, VDS = 0  
VGS = ±16 V, VDS = 0  
VDS = 150 V, VGS = 0  
VDS = 10 V, ID = 1 mA  
ID = 15 A, VGS = 10 V Note4  
ID = 15 A, VGS = 4 VNote4  
ID = 15 A, VDS = 10 VNote4  
IDSS  
VGS(off)  
RDS(on)  
RDS(on)  
|yfs|  
Ciss  
Coss  
Crss  
td(on)  
tr  
td(off)  
tf  
VDF  
Static drain to source on state  
resistance  
Forward transfer admittance  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
Turn-off delay time  
Fall time  
Body–drain diode forward voltage  
VDS = 10 V, VGS = 0  
f = 1MHz  
VGS = 10 V, ID= 15 A  
RL = 2 Ω  
—
—
—
—
IF = 30 A, VGS = 0  
IF = 30 A, VGS = 0  
diF/dt = 50 A/µs  
Body–drain diode reverse recovery  
time  
trr  
—
ns  
Notes: 4. Pulse test  
Rev.3.00 Sep. 30, 2004 page 2 of 8  
2SK3210(L), 2SK3210(S)  
Main Characteristics  
Power vs. Temperature Derating  
Maximum Safe Operation Area  
100  
500  
300  
160  
120  
80  
µ
s
100  
30  
10  
3
1
Operation in  
this area is  
limited by RDS(on)  
40  
0.3  
0.1  
Ta = 25°C  
0.05  
1000  
100 300  
0
10 30  
0.1  
1
3
50  
100  
150  
200  
0.3  
Drain to Source Voltage VDS (V)  
Case Temperature Tc (°C)  
Typical Output Characteristics  
Typical Transfer Characteristics  
50  
40  
30  
20  
10  
50  
40  
30  
20  
10  
VDS = 10 V  
Pulse Test  
10 V  
Pulse Test  
5 V  
4 V  
75°C  
25°C  
3 V  
Tc = –25°C  
VGS = 2.5 V  
0
0
1
2
3
4
5
2
4
6
8
10  
Drain to Source Voltage VDS (V)  
Gate to Source Voltage VGS (V)  
Drain to Source Saturation Voltage vs.  
Gate to Source Voltage  
Static Drain to Source on State Resistance  
vs. Drain Current  
1000  
2.0  
1.6  
1.2  
0.8  
0.4  
Pulse Test  
Pulse Test  
500  
200  
100  
50  
ID = 20 A  
VGS = 4 V  
10 V  
10 A  
5 A  
20  
10  
100  
10  
20  
50  
12  
5
0
2
4
8
16  
20  
1
Gate to Source Voltage VGS (V)  
Drain Current ID (A)  
Rev.3.00 Sep. 30, 2004 page 3 of 8  
2SK3210(L), 2SK3210(S)  
Static Drain to Source on State Resistance  
vs. Temperature  
Forward Transfer Admittance vs.  
Drain Current  
100  
250  
200  
150  
100  
50  
Pulse Test  
Tc = –25°C  
30  
10  
75°C  
25°C  
3
1
5, 10 A  
ID = 20 A  
VGS = 4 V  
5, 10 A  
120  
0.3  
0.1  
VDS = 10 V  
Pulse Test  
20 A  
10 V  
0
10  
50 100  
5
20  
2
0.1  
0.5  
1
0.2  
–40  
0
40  
80  
160  
Drain Current ID (A)  
Case Temperature Tc (°C)  
Body-Drain Diode Reverse  
Recovery Time  
Typical Capacitance vs.  
Drain to Source Voltage  
1000  
500  
10000  
di / dt = 50 A / µs  
Ciss  
V
GS = 0, Ta = 25°C  
3000  
1000  
200  
100  
50  
Coss  
300  
100  
Crss  
30  
10  
20  
10  
VGS = 0  
f = 1 MHz  
0.1 0.3  
1
3
10  
30  
100  
0
10  
20  
30  
40  
50  
Reverse Drain Current IDR (A)  
Drain to Source Voltage VDS (V)  
Dynamic Input Characteristics  
Switching Characteristics  
5000  
500  
400  
300  
200  
100  
20  
ID = 30A  
VGS = 10 V, VDD = 30 V  
VGS  
PW = 5 µs, duty < 1 %  
2000  
1000  
500  
16  
12  
8
t
d(off)  
VDD = 100 V  
50 V  
25 V  
t
f
200  
100  
t
r
VDS  
50  
4
0
t
d(on)  
VDD = 100 V  
50 V  
25 V  
20  
10  
0
40  
80  
120  
160  
200  
0.1 0.2 0.5  
1
2
5 10 20 50  
Drain Current ID (A)  
Gate Charge Qg (nc)  
Rev.3.00 Sep. 30, 2004 page 4 of 8  
2SK3210(L), 2SK3210(S)  
Reverse Drain Current vs.  
Source to Drain Voltage  
Maximum Avalanche Energy vs.  
Channel Temperature Derating  
50  
40  
30  
20  
10  
100  
80  
Pulse Test  
IAP = 30 A  
VDD = 50 V  
duty < 0.1 %  
Ω
Rg > 50  
60  
VGS = 10 V  
40  
20  
0
0, –5 V  
1.2  
5 V  
0
0.4  
0.8  
1.6  
2.0  
25  
50  
75  
100  
125  
150  
Source to Drain Voltage VSD (V)  
Channel Temperature Tch (°C)  
Normalized Transient Thermal Impedance vs. Pulse Width  
3
1
Tc = 25°C  
D = 1  
0.5  
0.3  
0.1  
θch – c(t) = γs (t) × θch – c  
θch – c = 1.25°C/W, Tc = 25°C  
PW  
T
P
DM  
D =  
0.03  
0.01  
PW  
T
10 µ  
100 µ  
1 m  
10 m  
Pulse Width PW (s)  
100 m  
1
10  
Avalanche Test Circuit  
Avalanche Waveform  
V
DSS  
– V  
1
2
EAR  
=
× L × IAP ×  
V
DSS  
DD  
2
L
V
DS  
Monitor  
I
AP  
Monitor  
V
(BR)DSS  
I
AP  
Rg  
V
V
DD  
D. U. T  
DS  
I
D
Vin  
15 V  
50Ω  
V
DD  
0
Rev.3.00 Sep. 30, 2004 page 5 of 8  
2SK3210(L), 2SK3210(S)  
Switching Time Test Circuit  
Vin Monitor  
Switching Time Waveform  
Vout  
Monitor  
90%  
D.U.T.  
R
L
10%  
10%  
Vin  
V
DD  
= 30 V  
Vin  
10 V  
Vout  
10%  
50Ω  
90%  
tr  
90%  
td(off)  
td(on)  
t
f
Rev.3.00 Sep. 30, 2004 page 6 of 8  
2SK3210(L), 2SK3210(S)  
Package Dimensions  
• 2SK3210(L)  
As of January, 2003  
Unit: mm  
4.44 0.2  
1.ꢀ 0.15  
10.2 0.ꢀ  
1.ꢀ 0.2  
1.ꢀ7 0.2  
2.49 0.2  
+ 0.2  
– 0.1  
0.86  
0.76 0.1  
2.54 0.5  
0.4 0.1  
2.54 0.5  
Package Code  
JEDEC  
LDPAK (L)  
—
JEITA  
—
Mass (reference value)  
1.40 g  
• 2SK3210(S)  
As of January, 2003  
Unit: mm  
4.44 0.2  
7.8  
6.6  
10.2 0.ꢀ  
1.ꢀ 0.15  
2.49 0.2  
+ 0.2  
– 0.1  
0.1  
2.2  
1.ꢀ7 0.2  
0.4 0.1  
+ 0.2  
1.ꢀ 0.2  
2.54 0.5  
0.86  
– 0.1  
2.54 0.5  
Package Code  
JEDEC  
LDPAK (S)-(1)  
—
JEITA  
—
Mass (reference value)  
1.ꢀ0 g  
Rev.3.00 Sep. 30, 2004 page 7 of 8  
2SK3210(L), 2SK3210(S)  
Ordering Information  
Part Name  
Quantity  
Shipping Container  
2SK3210L  
2SK3210STL  
50 pcs.  
1000 pcs.  
Loose packing  
Taping  
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of  
production before ordering the product.  
Rev.3.00 Sep. 30, 2004 page 8 of 8  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Keep safety first in your circuit designs!  
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble  
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,  
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
Notes regarding these materials  
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's  
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.  
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,  
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.  
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of  
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is  
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product  
information before purchasing a product listed herein.  
The information described here may contain technical inaccuracies or typographical errors.  
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.  
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor  
home page (http://www.renesas.com).  
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to  
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes  
no responsibility for any damage, liability or other loss resulting from the information contained herein.  
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life  
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a  
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater  
use.  
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.  
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and  
cannot be imported into a country other than the approved destination.  
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.  
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.  
RENESAS SALES OFFICES  
http://www.renesas.com  
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.  
Renesas Technology America, Inc.  
450 Holger Way, San Jose, CA 95134-1368, U.S.A  
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501  
Renesas Technology Europe Limited  
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.  
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900  
Renesas Technology Hong Kong Ltd.  
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong  
Tel: <852> 2265-6688, Fax: <852> 2730-6071  
Renesas Technology Taiwan Co., Ltd.  
10th Floor, No.99, Fushing North Road, Taipei, Taiwan  
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999  
Renesas Technology (Shanghai) Co., Ltd.  
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China  
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952  
Renesas Technology Singapore Pte. Ltd.  
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632  
Tel: <65> 6213-0200, Fax: <65> 6278-8001  
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .2.0  
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