HYS72T512020HR-5-A,PDF,HYS72T512020HR-5-A PDF资料,Datasheet,下载HYS72T512020HR-5-A技术资料

September 2006

HYS72T512020HR–[3.7/5]–A

240-Pin Registered-DDR2-SDRAM Modules

DDR2 SDRAM

RoHS Compliant

Internet Data Sheet

Rev. 1.11

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

HYS72T512020HR–[3.7/5]–A

Revision History: 2006-09, Rev. 1.11

Page

Subjects (major changes since last revision)

All

Qimonda Update

Adapted internet edition

Previous Revision: 2005-05, Rev. 1.0

27,31

SPD Update

36

Package outline figure updated

Previous Revision: 2005-02, Rev. 0.5

26, 27

Corrected IDD Currents

Removed IDD6(l) from IDD specification tables

Previous Revision: 2005-02, Rev. 0.5

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev400 / 3.2 QAG / 2006-07-21

03062006-TZ8J-GNDA

2

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

1

Overview

1.1

Features

This chapter contains features and the description

•

240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory

modules for PC, Workstation and Server main memory

applications

Two ranks 512M x 72 module organization with 256M ×4

chip organization

Standard Double-Data-Rate-Two Synchronous DRAMs

(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power

supply

Built with 1-Gbit DDR2 SDRAMs in P-TFBGA-68 chipsize

packages.

•

Programmable CAS Latencies (3, 4 & 5), Burst Length (4

& 8) and Burst Type

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_1.8 compatible

Off-Chip Driver Impedance Adjustment (OCD) and On-Die

Termination (ODT)

•

Serial Presence Detect with E²PROM

RDIMM Dimensions (nominal): 50.00 mm high, 133.35

mm wide

Qimonda Proprietary Raw Card Layout

RoHS compliant products¹⁾

•

TABLE 1

Performance for DDR2-533 and DDR2-400

Product Type Speed Code

–3.7

–5

Units

Speed Grade

PC2–4200 4–4–4

PC2–3200 3–3–3

—

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

266

200

15

200

15

MHz

ns

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

15

ns

t_RAS

t_RC

45

40

ns

60

55

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

Rev. 1.11, 2006-09

3

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

1.2

Description

The Qimonda HYS72T512020HR–[3.7/5]–A module family

are Registered DIMM modules “RDIMMs” with 50,0 mm

height based on DDR2 technology.

driven on the DIMM using register devices and a PLL for the

clock distribution. This reduces capacitive loading to the

system bus, but adds one cycle to the SDRAM timing.

Decoupling capacitors are mounted on the PCB board. The

DIMMs feature serial presence detect based on a serial

E²PROM device using the 2-pin I2C protocol. The first

128 bytes are programmed with configuration data and the

second 128 bytes are available to the customer.

DIMMs are available as ECC modules in 512M x 72

(4 GByte) organization and density, intended for mounting

into 240-Pin connector sockets.The memory array is

designed with 1-Gbit Double-Data-Rate-Two (DDR2)

Synchronous DRAMs. All control and address signals are re-

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description

SDRAM Technology

PC2–4200

HYS72T512020HR–3.7–A

PC2-3200

4 GB 2R×4 PC2–4200R–444–11–ZZ

4 GB 2R×4 PC2–3200R–333–11–ZZ

2 Ranks, ECC

1 Gbit (×4)

HYS72T512020HR–5–A

1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T512020HR–5–A, indicating Rev. “A” dies

are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–ZZ”, where

4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency

= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced

on the Raw Card “ZZ”

TABLE 3

Address Format

DIMM

Density

Module

Organization

Memory

Ranks

ECC/

Non-ECC

# of

SDRAMs

# of row/bank/columns bits

Raw Card

4 GB

512M × 72

2

ECC

36

14/3/11

ZZ

TABLE 4

Components on Modules

Product Type¹⁾

DRAM Components¹⁾DRAM Density

HYB18T1G400AF 1 Gbit

DRAM Organization

256M × 4

Note ²⁾

HYS72T512020HR

1) Green Product

2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.

Rev. 1.11, 2006-09

4

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

2

Pin Configuration

2.1

Pin Configuration

The pin configuration of the Registered DDR2 SDRAM DIMM

is listed by function in Table 5 (240 pins). The abbreviations

used in columns Pin and Buffer Type are explained in Table 6

and Table 7 respectively. The pin numbering is depicted in

Figure 1.

TABLE 5

Pin Configuration of RDIMM

Ball No.

Name

Buffer

Function

Type Type

Clock Signals

185

186

52

CK0

CKE0

CKE1

NC

I

SSTL

—

Clock Signal CK0, Complementary Clock Signal CK0

I

Clock Enables 1:0

Note: 2-Ranks module

171

I

NC

Not Connected

Note: 1-Rank module

Control Signals

193

76

S0

S1

NC

I

SSTL

—

Chip Select Rank 1:0

Note: 2-Ranks module

I

NC

Not Connected

Note: 1-Rank module

192

RAS

I

SSTL

CMOS

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

74

CAS

73

WE

18

RESET

Register Reset

Address Signals

71

BA0

BA1

BA2

NC

I

SSTL

Bank Address Bus 1:0

190

54

Bank Address Bus 2

Not Connected

Rev. 1.11, 2006-09

6

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

188

183

63

A0

I

SSTL

—

Address Bus 12:0, Address Signal 10/AutoPrecharge

A1

I

A2

I

182

61

A3

I

A4

I

60

A5

I

180

58

A6

I

A7

I

179

177

70

A8

I

A9

I

A10

AP

A11

A12

A13

NC

A14

NC

A15

NC

I

57

I

176

196

I

Address Signal 13

Not Connected

NC

I

174

173

SSTL

—

Address Signal 14

Not Connected

NC

I

SSTL

—

Address Signal 14

Not Connected

NC

Rev. 1.11, 2006-09

7

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Data Signals

3

DQ0

I/O

SSTL

Data Bus 63:0

4

DQ1

9

DQ2

10

DQ3

122

123

128

129

12

DQ4

DQ5

DQ6

DQ7

DQ8

13

DQ9

21

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

81

86

87

199

200

205

Rev. 1.11, 2006-09

8

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

206

89

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

90

95

96

208

209

214

215

98

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bits

42

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O

SSTL

Check Bits 7:0

43

48

49

161

162

167

168

Rev. 1.11, 2006-09

9

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Data Strobe Bus

7

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DQS9

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

DQS17

I/O

SSTL

Data Strobes 17:0

6

16

15

28

27

37

36

84

83

93

92

105

104

114

113

46

45

125

126

134

135

146

147

155

156

202

203

211

212

223

224

232

233

164

165

Rev. 1.11, 2006-09

10

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Data Mask

125

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

SSTL

Data Masks 8:0

Note: ×8 based module

134

146

155

202

211

223

232

164

EEPROM

120

SCL

SDA

SA0

SA1

SA2

I

CMOS

OD

Serial Bus Clock

119

I/O

Serial Bus Data

239

I

CMOS

Serial Address Select Bus 2:0

240

101

Parity

55

ERR_OUT

PAR_IN

O

I

CMOS

Parity bits

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

EEPROM Power Supply

I/O Driver Power Supply

238

V_DDSPD

PWR

51, 56, 62, 72, 75, V_DDQ

78, 170, 175,, 181,

191, 194

53, 59, 64, 67, 69, V_DD

172, 178, 184,,

187, 189, 197

PWR

GND

—

Power Supply

Ground Plane

2, 5, 8, 11, 14, 17, V_SS

20, 23, 26, 29, 32,

35, 38, 41, 44, 47,

50, 65, 66, 79, 82,

85, 88, 91, 94, 97,

100, 103, 106, 109,

112, 115, 118, 121,

124, 127, 130, 133,

136, 139, 142, 145,

148, 151, 154, 157,

160, 163, 166, 169,

198, 201, 204, 207,

210, 213, 216, 219,

222, 225, 228, 231,

234, 237

Rev. 1.11, 2006-09

11

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Ball No.

Name

Buffer

Function

Type Type

Other Pins

19, 55, 68, 102,

137, 138, 173, 220,

221

NC

—

Not connected

195

77

ODT0

ODT1

NC

I

SSTL

—

On-Die Termination Control 1:0

Note: 2-Ranks module

I

NC

Note: 1-Rank modules

TABLE 6

Abbreviations for Buffer Type

Abbreviation

Description

SSTL

CMOS

OD

Serial Stub Terminated Logic (SSTL_18)

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and tristate,

and allows multiple devices to share as a wire-OR.

TABLE 7

Abbreviations for Pin Type

Abbreviation

Description

I

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

O

I/O

AI

PWR

GND

NU

NC

Ground

Not Usable

Not Connected

Rev. 1.11, 2006-09

12

03062006-TZ8J-GNDA

ꢃ

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

FIGURE 1

Pin Configuration for RDIMM (240 pins)

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Rev. 1.11, 2006-09

13

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3

Electrical Characteristics

This chapter lists the electrical characteristics.

3.1

Absolute Maximum Ratings

This chapter contains the absolute maximum ratings table.

TABLE 8

Absolute Maximum Ratings

Parameter

Symbol

Values

Min.

Unit

Note

Max.

1)

Voltage on any pins relative to V_SS

Voltage on V_DDrelative to V_SS

V_IN, V_OUT

V_DD

–0.5

–1.0

–0.5

5

2.3

95

V

%

Voltage on V_{DD Q}relative to V_SS

Storage Humidity (without condensation)

V_DDQ

H_STG

1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation

at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability

3.2

DC Operating Conditions

This chapter describes the operating conditions.

TABLE 9

Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Max.

DIMM Module Operating Temperature Range (ambient)

DRAM Component Case Temperature Range

Storage Temperature

T_OPR

T_CASE

T_STG

0

+55

+95

+100

+105

90

°C

kPa

%

1)2)3)4)

5)

0

–50

+69

10

Barometric Pressure (operating & storage)

Operating Humidity (relative)

PBar

H_OPR

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.

3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs.

4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C case

temperature before initiating self-refresh operation.

5) Up to 3000 m

Rev. 1.11, 2006-09

15

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 10

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Note

Nom.

Max.

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

1.9

V

1)

2)

V_DDQ

V_REF

V_DDSPD

V_{IH (DC)}

V_{IL (DC)}

I_L

1.7

1.8

1.9

V

0.49 x V_DDQ

0.5 x V_DDQ

0.51 x V_DDQ

V

1.7

—

3.6

V

DC Input Logic High

V

_REF+ 0.125

V

5

_DDQ+ 0.3

V

DC Input Logic Low

–0.30

–5

_REF– 0.125

V

3)

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise variations in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

.

Rev. 1.11, 2006-09

16

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3.3

AC Characteristics

This chapter describes the AC characteristics.

3.3.1

Speed Grades Definitions

This chapter contains the Speed Grade Definition tables.

TABLE 11

Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400

Speed Grade

DDR2–533C

DDR2–400B

Unit

Note

IFX Sort Name

–3.7

–5

CAS-RCD-RP latencies

4–4–4

3–3–3

t_CK

Parameter

Symbol

Min.

Max.

Min.

Max.

—

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

5

8

5

8

ns

t_CK

3.75

45

8

5

8

t_CK

8

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

40

55

15

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal

OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,

input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

4) The output timing reference voltage level is V_TT

.

5) _RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI

t

.

Rev. 1.11, 2006-09

17

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3.3.2

AC Timing Parameters

This chapter contains the AC Timing Parameters.

TABLE 12

Timing Parameter by Speed Grade - DDR2-400 & DDR2-533

Parameter

Symbol

DDR2–533

DDR2–400

Unit Note¹⁾²⁾

3)4)5)6)7)

Min.

Max.

Min.

Max.

DQ output access time from CK/CK

CAS A to CAS B command period

CK,CK high-level width

t_AC

–500

2

+500

—

–600

2

+600

—

ps

t_CCD

t_CH

t_CK

0.45

3

0.55

—

0.45

3

0.55

—

CKE minimum high and low pulse

width

t_CKE

CK,CK low-level width

t_CL

0.45

0.55

—

0.45

0.55

—

t_CK

Auto-Precharge write recovery +

precharge time

t_DAL

WR + t_RP

Minimum time clocks remain ON after t_DELAY

CKE asynchronously drops LOW

t_IS+ t_CK+ t_IH––

t

_IS+ t_CK+ t_IH

—

––

—

ns

ps

t_CK

DQ and DM input hold time

(differential data strobe)

t

_DH(base)

225

––

—

275

25

DQ and DM input hold time (single

ended data strobe)

_DH1(base) –25

DQ and DM input pulse width (each

input)

t_DIPW

0.35

DQS output access time from CK/CK t_DQSCK

–450

0.35

+450

–500

0.35

+500

ps

DQS input low (high) pulse width

(write cycle)

t_DQSL,H

—

t_CK

DQS-DQ skew (for DQS & associated t_DQSQ

DQ signals)

—

300

+ 0.25

—

350

+ 0.25

—

ps

t_CK

ps

t_CK

ns

Write command to 1st DQS latching

transition

t_DQSS

– 0.25

100

– 0.25

150

25

DQ and DM input setup time

(differential data strobe)

t

_DS(base)

DQ and DM input setup time (single

ended data strobe)

_DS1(base) –25

—

DQS falling edge hold time from CK

(write cycle)

t_DSH

t_DSS

t_FAW

0.2

—

0.2

—

DQS falling edge to CK setup time

(write cycle)

—

0.2

—

Four Activate Window period

37.5

—

37.5

—

8)

50

ns

Clock half period

t_HP

t_HZ

MIN. (t_CL,t_CH

)

MIN. (t_CL,t_CH)

Data-out high-impedance time from

CK/CK

—

t_AC.MAX

—

t_AC.MAX

ps

Address and control input hold time

t_IH(base)

375

—

475

—

Rev. 1.11, 2006-09

18

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Parameter

Symbol

DDR2–533

DDR2–400

Unit Note¹⁾²⁾

3)4)5)6)7)

Min.

Max.

Min.

Max.

Address and control input pulse width t_IPW

0.6

—

0.6

—

t_CK

(each input)

Address and control input setup time t_IS(base)

DQ low-impedance time from CK / CK t_LZ(DQ)

250

—

350

—

ps

ns

2 x t_AC.MIN

t_AC.MIN

0

t_AC.MAX

12

2 ξ t_AC.MIN

t_AC.MIN

0

t_AC.MAX

12

DQS low-impedance from CK / CK

t_LZ(DQS)

t_MOD

Mode register set command to ODT

update delay

Mode register set command cycle time t_MRD

2

0

—

2

0

—

t_CK

OCD drive mode output delay

Data output hold time from DQS

Data hold skew factor

t_OIT

12

—

12

ns

t_QH

t

_HP– t_QHS

t_HPQ– t_QHS

—

t_QHS

t_REFI

—

400

7.8

3.9

—

450

7.8

3.9

—

ps

9)

Average periodic refresh Interval

—

µs

10)

—

µs

Auto-Refresh to Active/Auto-Refresh t_RFC

127.5

ns

command period

Precharge-All (8 banks) command

period

t_RP

15 + 1t_CK

—

15 + 1t_CK

—

ns

Read preamble

Read postamble

t_RPRE

t_RPST

t_RRD

0.9

1.1

0.60

—

0.9

1.1

0.60

—

t_CK

0.40

7.5

0.40

7.5

11)

Active bank A to Active bank B

command period

ns

Internal Read to Precharge command t_RTP

7.5

—

7.5

—

ns

delay

Write preamble

Write postamble

t_WPRE

t_WPST

t_WR

0.35 x t_CK

0.40

—

0.35 x t_CK

0.40

—

t_CK

ns

0.60

—

0.60

—

Write recovery time for write without

Auto-Precharge

15

Write recovery time for write with Auto- WR

Precharge

t

_WR/t_CK

—

t_WR/t_CK

—

t_CK

Internal Write to Read command delay t_WTR

7.5

2

—

10

2

—

ns

Exit power down to any valid

command

t_XARD

t_CK

(other than NOP or Deselect)

Exit active power-down mode to Read t_XARDS

command (slow exit, lower power)

6 – AL

2

—

6 – AL

2

—

t_CK

Exit precharge power-down to any

valid command (other than NOP or

Deselect)

t_XP

Exit Self-Refresh to non-Read

command

t_XSNR

t

_RFC+10

—

t

_RFC+10

—

ns

Exit Self-Refresh to Read command t_XSRD

200

t_CK

1) For details and notes see the relevant QIMONDA component data sheet

2)

_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V. See notes ^4)5)6)7)

V

Rev. 1.11, 2006-09

19

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down

and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew

Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,

input reference level is the crosspoint when in differential strobe mode

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis recognized as low.

7) The output timing reference voltage level is V_TT

8) x16 (2k page size), not on 256 Mbit component

9) 0 ≤ T_CASE≤ 85 °C

.

10) 85 °C < T_CASE≤ 95 °C

11) x4 & x8

Rev. 1.11, 2006-09

20

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3.3.3

ODT AC Electrical Characteristics

This chapter contains the ODT AC electrical characteristics tables.

TABLE 13

ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400

Symbol

Parameter / Condition

Values

Unit

Note

Min.

Max.

t_AOND

t_AON

ODT turn-on delay

2

t_CK

ns

t_CK

ns

t_CK

1)

2)

ODT turn-on

t_AC.MIN

t_AC.MAX+ 1 ns

t_AONPD

t_AOFD

t_AOF

ODT turn-on (Power-Down Modes)

ODT turn-off delay

t

_AC.MIN+ 2 ns

2 t_{CK +}t_AC.MAX+ 1 ns

2.5

ODT turn-off

t_AC.MIN

t_AC.MAX+ 0.6 ns

t_AOFPD

t_ANPD

t_AXPD

ODT turn-off (Power-Down Modes)

ODT to Power Down Mode Entry Latency

ODT Power Down Exit Latency

t

_AC.MIN+ 2 ns

2.5 t_{CK +}t_AC.MAX+ 1 ns

3

8

—

1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when

the ODT resistance is fully on. Both are measure from t_AOND

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.

.

Both are measured from t_AOFD

.

Rev. 1.11, 2006-09

21

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3.4

Currents Specifications and Conditions

TABLE 14

I_DDMeasurement Conditions

Parameter

Symbol Note^{1)2)3)4)5)6)7)8)}

Operating Current 0

I_DD0

One bank Active - Precharge; t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS= t_RAS.MIN, CKE is HIGH, CS is

HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs

are SWITCHING.

Operating Current 1

I_DD1

One bank Active - Read - Precharge; I_OUT= 0 mA, BL = 4, t_CK= t_CK.MIN, t_RC= t_RC.MIN, t_RAS

_RAS.MIN, t_RCD= t_RCD.MIN, AL = 0, CL = CL_.MIN; CKE is HIGH, CS is HIGH between valid

=

t

commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.

Precharge Standby Current

I_DD2N

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are

SWITCHING, Data bus inputs are SWITCHING

Precharge Power-Down Current

Other control and address inputs are STABLE, Data bus inputs are FLOATING_.

I_DD2P

I_DD2Q

Precharge Quiet Standby Current

All banks idle; CS is HIGH; CKE is HIGH; t_CK= t_CK.MIN; Other control and address inputs are

STABLE, Data bus inputs are FLOATING.

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data

bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);

I_DD3P(0)

I_DD3P(1)

I_DD3N

Active Power-Down Current

All banks open; t_CK= t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data

bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);

Active Standby Current

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX, t_RP= t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address

inputs are SWITCHING; Data Bus inputs are SWITCHING; I_OUT= 0 mA.

Operating Current

I_DD4R

I_DD4W

I_DD5B

I_DD5D

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX., t_RP= t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address

inputs are SWITCHING; Data Bus inputs are SWITCHING; I_OUT= 0 mA.

Operating Current

Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_MIN; t_CK= t_CK.MIN

;

t

_RAS= t_RAS.MAX., t_RP= t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address

inputs are SWITCHING; Data Bus inputs are SWITCHING;

Burst Refresh Current

t

_CK= t_CK.MIN., Refresh command every t_RFC= t_RFC.MINinterval, CKE is HIGH, CS is HIGH

between valid commands, Other control and address inputs are SWITCHING, Data bus inputs

are SWITCHING.

Distributed Refresh Current

t

_CK= t_CK.MIN, Refresh command every t_RFC= t_REFIinterval, CKE is LOW and CS is HIGH

between valid commands, Other control and address inputs are SWITCHING, Data bus inputs

are SWITCHING.

Rev. 1.11, 2006-09

22

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Parameter

Symbol Note^{1)2)3)4)5)6)7)8)}

Self-Refresh Current

I_DD6

CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are

FLOATING, Data bus inputs are FLOATING. RESET is LOW. I_DD6current values are

guaranteed up to T_CASEof 85 °C max.

All Bank Interleave Read Current

I_DD7

All banks are being interleaved at minimum t_RCwithout violating t_RRDusing a burst length of 4.

Control and address bus inputs are STABLE during DESELECTS. I_OUT= 0 mA.

1)

V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V

2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.

3) Definitions for I_DDsee Table 15

4)

I_DD1, I_DD4Rand I_DD7current measurements are defined with the outputs disabled (I_OUT= 0 mA). To achieve this on module level the output

buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.

5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode I_DD2P

6) RESET signal is HIGH for all currents, except for I_DD6(Self Refresh)

7) All current measurements includes Register and PLL current consumption

8) For details and notes see the relevant QIMONDA component data sheet

TABLE 15

Definitions for I_DD

Parameter

Description

LOW

V_IN≤ V_IL(ac).MAX, HIGH is defined as V_IN≥ V_IH(ac).MIN

inputs are stable at a HIGH or LOW level

inputs are V_REF= V_DDQ/2

STABLE

FLOATING

SWITCHING

inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control

signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ

signals not including mask or strobes.

Rev. 1.11, 2006-09

23

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 16

_DDSpecification for HYS72T512020HR-3.7-A

I

Product Type

Organization

HYS72T512020HR–3.7–A

Unit

Note¹⁾

4 G

2 Ranks

×72

–3.7

Symbol

Max.

2)

3)

2)

3)

2)

I_DD0

1950

2130

2160

710

mA

I_DD1

I_DD2N

I_DD2P

I_DD2Q

1650

2300

1110

720

I_DD3N

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD4R

3210

3120

3930

750

I_DD4W

I_DD5B

I_DD5D

I_DD6

205

I_DD7

4740

1) ModuleI_DDis calculated on the basis of component I_DDand includes currents of Registers and PLL. ODT disabled. I_DD1,

defined with the outputs disabled.

I_DD4R,and I_DD7,are

2) The other rank is in I_DD2PPrecharge Power-Down Standby Current mode

3) Both ranks are in the same I_DDcurrent mode

Rev. 1.11, 2006-09

24

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 17

_DDSpecification for HYS72T512020HR–5–A

I

Product Type

Organization

HYS72T512020HR–5–A

Unit

Note¹⁾

4 G

2 Ranks

×72

–5

Symbol

Max.

2)

3)

2)

3)

2)

I_DD0

1770

1950

1670

610

mA

I_DD1

I_DD2N

I_DD2P

I_DD2Q

1410

1850

870

I_DD3N

I_{DD3P( MRS = 0)}

I_{DD3P( MRS = 1)}

I_DD4R

620

2580

2490

3750

660

I_DD4W

I_DD5B

I_DD5D

I_DD6

205

I_DD7

4200

1) ModuleI_DDis calculated on the basis of component I_DDand includes currents of Registers and PLL. ODT disabled. I_DD1,

defined with the outputs disabled.

I_DD4R,and I_DD7,are

2) The other rank is in I_DD2PPrecharge Power-Down Standby Current mode

3) Both ranks are in the same I_DDcurrent mode

Rev. 1.11, 2006-09

25

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

3.4.1

Currents Test Conditions

For testing the I_DDparameters, the following timing parameters are used:

TABLE 18

I

_DDMeasurement Test Conditions for DDR2–400 and DDR2–533

Parameter

Symbol

–3.7

–5

Unit

DDR2–533C

DDR2–400B

CAS Latency

CL_(IDD)

t_CK(IDD)

t_RCD(IDD)

t_RC(IDD)

4

3

t_CK

ns

Clock Cycle Time

3.75

15

60

5

Active to Read or Write delay

15

55

Active to Active / Auto-Refresh command period

Active bank A to Active bank B command delay

Active to Precharge Command

t_RAS.MIN(IDD)

t_RAS.MAX(IDD)

t_RP(IDD)

45

40

ns

µs

70000

15

70000

15

Precharge Command Period

Auto-Refresh to Active / Auto-Refresh command period

Average periodic Refresh interval

t_RFC(IDD)

t_REFI

127.5

7.8

127.5

7.8

3.4.2

On Die Termination (ODT) Current

The ODT function adds additional current consumption to the

DDR2 SDRAM when enabled by the EMRS(1). Depending on

address bits A[6,2] in the EMRS(1) a “weak” or “strong”

termination can be selected. The current consumption for any

terminated input pin, depends on the input pin is in tri-state or

driving 0 or 1, as long a ODT is enabled during a given period

of time.

TABLE 19

ODT current per terminated pin

Parameter

Symbol Min.

Typ.

Max.

Unit

EMRS(1) State

Enabled ODT current per DQODT is HIGH; Data I_ODTO

Bus inputs are FLOATING

5

6

7.5

3.75

15

mA/DQ

A6 = 0, A2 = 1

A6 = 1, A2 = 0

A6 = 0, A2 = 1

A6 = 1, A2 = 0

2.5

10

5

3

Active ODT current per DQODT is HIGH; worst

case of Data Bus inputs are STABLE or

SWITCHING.

I_ODTT

12

6

7.5

Rev. 1.11, 2006-09

26

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

4

SPD Codes

This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands

for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.

List of SPD Code Tables

•

Table 20 “SPD codes for PC2–4200R–444” on Page 27

Table 21 “SPD codes for PC2–3200R–333” on Page 31

TABLE 20

SPD codes for PC2–4200R–444

Product Type

Organization

HYS72T512020HR–3.7–A

4 GByte

×72

2 Ranks (×4)

PC2–4200R–444

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0E

0B

61

48

00

05

3D

50

02

82

04

00

0C

08

38

00

01

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

Rev. 1.11, 2006-09

27

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Product Type

Organization

HYS72T512020HR–3.7–A

4 GByte

×72

2 Ranks (×4)

PC2–4200R–444

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

DIMM Attributes

07

01

3D

50

60

3C

1E

3C

2D

02

25

37

10

22

3C

1E

00

06

3C

7F

80

1E

28

0F

51

60

37

1D

23

1E

1F

Component Attributes

t

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

_RAS.MIN[ns]

Module Density per Rank

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ∆T_4R4WDelta

T

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

Rev. 1.11, 2006-09

28

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Product Type

Organization

HYS72T512020HR–3.7–A

4 GByte

×72

2 Ranks (×4)

PC2–4200R–444

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

∆T_3P.slow(DT3P slow)

16

43

22

2A

C4

8C

61

78

11

A7

7F

51

00

xx

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

37

32

54

35

31

32

30

32

30

48

52

33

2E

37

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Rev. 1.11, 2006-09

29

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Product Type

Organization

HYS72T512020HR–3.7–A

4 GByte

×72

2 Ranks (×4)

PC2–4200R–444

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

87

88

89

90

91

92

93

94

Product Type, Char 15

41

20

5x

xx

00

FF

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

95 - 98 Module Serial Number

99 - 127 Not used

128 -

255

Blank for customer use

Rev. 1.11, 2006-09

30

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

TABLE 21

SPD codes for PC2–3200R–333

Product Type

Organization

HYS72T512020HR–5–A

4 GByte

×72

2 Ranks (×4)

PC2–3200R–333

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

0

Programmed SPD Bytes in EEPROM

Total number of Bytes in EEPROM

Memory Type (DDR2)

80

08

0E

0B

61

48

00

05

50

60

02

82

04

00

0C

08

38

00

01

07

01

50

60

50

60

3C

1E

3C

1

2

3

Number of Row Addresses

Number of Column Addresses

DIMM Rank and Stacking Information

Data Width

4

5

6

7

Not used

8

Interface Voltage Level

9

t

_CK@ CL_MAX(Byte 18) [ns]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

_ACSDRAM @ CL_MAX(Byte 18) [ns]

Error Correction Support (non-ECC, ECC)

Refresh Rate and Type

Primary SDRAM Width

Error Checking SDRAM Width

Not used

Burst Length Supported

Number of Banks on SDRAM Device

Supported CAS Latencies

DIMM Mechanical Characteristics

DIMM Type Information

DIMM Attributes

Component Attributes

t

_CK@ CL_MAX-1 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-1 [ns]

_CK@ CL_MAX-2 (Byte 18) [ns]

_ACSDRAM @ CL_MAX-2 [ns]

_RP.MIN[ns]

_RRD.MIN[ns]

_RCD.MIN[ns]

Rev. 1.11, 2006-09

31

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Product Type

Organization

HYS72T512020HR–5–A

4 GByte

×72

2 Ranks (×4)

PC2–3200R–333

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

_RAS.MIN[ns]

Module Density per Rank

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

t

28

02

35

47

15

27

3C

28

1E

00

06

37

7F

80

23

2D

0F

51

60

33

1A

23

18

16

35

21

25

C4

8C

59

5C

11

t

_AS.MINand t_CS.MIN[ns]

_AH.MINand t_CH.MIN[ns]

_DS.MIN[ns]

_DH.MIN[ns]

_WR.MIN[ns]

_WTR.MIN[ns]

_RTP.MIN[ns]

Analysis Characteristics

t

_RCand t_RFCExtension

_RC.MIN[ns]

_RFC.MIN[ns]

_CK.MAX[ns]

_DQSQ.MAX[ns]

_QHS.MAX[ns]

PLL Relock Time

_CASE.MAXDelta / ∆T_4R4WDelta

T

Psi(T-A) DRAM

∆T₀(DT0)

∆T_2N(DT2N, UDIMM) or ∆T_2Q(DT2Q, RDIMM)

∆T_2P(DT2P)

∆T_3N(DT3N)

∆T_3P.fast(DT3P fast)

∆T_3P.slow(DT3P slow)

∆T_4R(DT4R) / ∆T_4R4WSign (DT4R4W)

∆T_5B(DT5B)

∆T₇(DT7)

Psi(ca) PLL

Psi(ca) REG

∆T_PLL(DTPLL)

∆T_REG(DTREG) / Toggle Rate

SPD Revision

Rev. 1.11, 2006-09

32

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Product Type

Organization

HYS72T512020HR–5–A

4 GByte

×72

2 Ranks (×4)

PC2–3200R–333

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Checksum of Bytes 0-62

Manufacturer’s JEDEC ID Code (1)

Manufacturer’s JEDEC ID Code (2)

Manufacturer’s JEDEC ID Code (3)

Manufacturer’s JEDEC ID Code (4)

Manufacturer’s JEDEC ID Code (5)

Manufacturer’s JEDEC ID Code (6)

Manufacturer’s JEDEC ID Code (7)

Manufacturer’s JEDEC ID Code (8)

Module Manufacturer Location

Product Type, Char 1

D5

7F

51

00

xx

37

32

54

35

31

32

30

32

30

48

52

35

41

20

5x

xx

Product Type, Char 2

Product Type, Char 3

Product Type, Char 4

Product Type, Char 5

Product Type, Char 6

Product Type, Char 7

Product Type, Char 8

Product Type, Char 9

Product Type, Char 10

Product Type, Char 11

Product Type, Char 12

Product Type, Char 13

Product Type, Char 14

Product Type, Char 15

Product Type, Char 16

Product Type, Char 17

Product Type, Char 18

Module Revision Code

Test Program Revision Code

Module Manufacturing Date Year

Module Manufacturing Date Week

xx

95 - 98 Module Serial Number

xx

Rev. 1.11, 2006-09

33

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Product Type

Organization

HYS72T512020HR–5–A

4 GByte

×72

2 Ranks (×4)

PC2–3200R–333

Rev. 1.1

HEX

Label Code

JEDEC SPD Revision

Byte#

Description

99 - 127 Not used

00

128 -

255

Blank for customer use

FF

Rev. 1.11, 2006-09

34

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

5

Package Outlines

FIGURE 2

Package Outline Raw Card ZZ L-DIM-240-42

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Rev. 1.11, 2006-09

35

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

6

Product Type Nomenclature

Qimonda’s nomenclature uses simple coding combined with

some propriatory coding. Table 22 provides examples for

module and component product type number as well as the

field number. The detailed field description together with

possible values and coding explanation is listed for modules

in Table 23 and for components in Table 24.

TABLE 22

Nomenclature Fields and Examples

Example for

Field Number

1

2

3

4

5

6

7

8

9

10

11

Micro-DIMM

DDR2 DRAM

HYS

HYB

64

18

T

0

2

0

K

A

M

C

–5

–A

1G

16

TABLE 23

DDR2 DIMM Nomenclature

Field

Description

Values

Coding

1

2

Qimonda Module Prefix

Module Data Width [bit]

HYS

64

Constant

Non-ECC

ECC

72

3

4

DRAM Technology

T

DDR2

Memory Density per I/O [Mbit];

Module Density¹⁾

32

256 MByte

512 MByte

1 GByte

2 GByte

4 GByte

64

128

256

512

0 .. 9

0, 2, 4

0 .. 9

A .. Z

D

5

6

7

8

9

Raw Card Generation

Number of Module Ranks

Product Variations

Look up table

1, 2, 4

Look up table

SO-DIMM

Package, Lead-Free Status

Module Type

M

Micro-DIMM

Registered

Unbuffered

Fully Buffered

R

U

F

Rev. 1.11, 2006-09

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Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Field

Description

Values

Coding

10

Speed Grade

–2.5F

–2.5

–3

PC2–6400 5–5–5

PC2–6400 6–6–6

PC2–5300 4–4–4

PC2–5300 5–5–5

PC2–4200 4–4–4

PC2–3200 3–3–3

First

–3S

–3.7

–5

11

Die Revision

–A

–B

Second

1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall

module memory density in MBytes as listed in column “Coding”.

TABLE 24

DDR2 DRAM Nomenclature

Field

Description

Values

Coding

1

2

3

4

Qimonda Component Prefix

Interface Voltage [V]

HYB

18

Constant

SSTL_18

DRAM Technology

T

DDR2

Component Density [Mbit]

256

512

1G

2G

40

256 Mbit

512 Mbit

1 Gbit

2 Gbit

5+6

Number of I/Os

×4

80

×8

16

×16

7

8

Product Variations

Die Revision

0 .. 9

A

Look up table

First

B

Second

9

Package, Lead-Free Status

Speed Grade

C

FBGA, lead-containing

FBGA, lead-free

DDR2-800 5-5-5

DDR2-800 6-6-6

DDR2-667 4-4-4

DDR2-667 5-5-5

DDR2-533 4-4-4

DDR2-400 3-3-3

F

10

–25F

–2.5

–3

–3S

–3.7

–5

Rev. 1.11, 2006-09

37

03062006-TZ8J-GNDA

Internet Data Sheet

HYS72T512020HR–[3.7/5]–A

Registered DDR2 SDRAM Modules

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.4

3.4.1

3.4.2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4

5

6

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Rev. 1.11, 2006-09

38

03062006-TZ8J-GNDA

Internet Data Sheet

Edition 2006-09

Published by Qimonda AG

Gustav-Heinemann-Ring 212

D-81739 München, Germany

Legal Disclaimer

The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics

(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,

including without limitation warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please

contact your nearest Qimonda Office.

Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a

failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect

the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human

body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health

of the user or other persons may be endangered.

www.qimonda.com

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