HYS64D128020GBDL-[6/7]-A
DDR-SDRAM SO-DIMM Modules
Operating, Standby and Refresh Currents
1GB, 2 banks
-6
PC2700S-2533 PC2100S-2033
1GB, 2 banks
-7
Notes
Symbol Parameter/Condition
Unit
4
1
TYP
MAX
TYP
MAX
Operating Current: one bank; active / precharge; tRC = tRC MIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs
changing once every two clock cycles
IDD0
1360
1560
1208
1400
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current: one bank; active/read/precharge; burst length 4;
Refer to the following page for detailed test conditions.
IDD1
1552
120
1760
176
1416
112
1600
160
1, 3
2
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE <= VIL MAX
IDD2P
IDD2F
IDD2Q
IDD3P
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN =
VREF for DQ, DQS and DM.
576
656
496
560
2
Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; address and other control inputs stable
at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
440
528
384
448
2
Active Power-Down Standby Current: one bank active; power-down mode;
CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM.
256
320
224
288
2
Active Standby Current: one bank active; CS >= VIH MIN; CKE >= VIH MIN;
IDD3N tRC = tRAS MAX; DQ, DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
688
800
608
720
2
Operating Current: one bank active; burst length 2; reads; continuous burst; address and
IDD4R control inputs changing once per clock cycle; 50% of data outputs changing on every clock
edge; CL = 2 for DDR200 and DDR266(A), CL=3 for DDR333 and DDR400; IOUT = 0mA
1680
1600
2328
40
1960
1880
2600
56
1424
1368
2200
40
1680
1600
2480
56
1, 3
1
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and
IDD4W control inputs changing once per clock cycle; 50% of data outputs changing on every clock
edge; CL = 2 for DDR200 and DDR266(A), CL=3 for DDR333 and DDR400
Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
Self-Refresh Current: CKE <= 0.2V; external clock on
IDD5
IDD6
IDD7
1
Operating Current: four bank; four bank interleaving with burst length 4;
Refer to the following page for detailed test conditions.
3056
3440
2536
3000
1, 3
1. The module IDD values are calculated from the component IDD datasheet values as: IDDx[component] * m + IDD3N[component] * n
with m, n number of components of bank 1 and 2; n=0 for 1 bank modules
2. The module IDD values are calculated from the component IDD datasheet values as: IDDx[component] * (m + n)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C
INFINEON Technologies AG
6
V0.6, 2003-01-07
