WV3HG128M72EER-D7
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = +1.8V 0.1V
Symbol Parameter Condition
806
665
534
403
Unit
Operating
one bank
active-
tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between valid
CC CC
commands; Address bus inputs are SWITCCCHING; Data bus inputs are SWITCHING
ICC0*
1,210 1,165 1,120
mA
TBD
precharge;
Operating
one bank
active-
IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is
CC
CC
ICC1*
HIGH, CS# is HIGH between valid commanCdCs; Address bus inputs are SWITCHING;
1,300 1,255 1,210
mA
mA
TBD
TBD
read-
Data bus inputs are SWITCHING; Data pattern is same as ICC4W.
precharge;
Precharge
power-
All banks idle; tCK = tCK(I ); CKE is LOW; Other control and address bus inputs are
CC
ICC2P**
508
508
508
down
STABLE; Data bus inputs are FLOATING
current;
Precharge
quite
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; DatCaCbus inputs are FLOATING
ICC2Q**
760
805
715
760
715
760
mA
mA
TBD
TBD
standby
current;
Precharge
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and address bus
inputs are STABLE; DatCaCbus inputs are SWITCHING
ICC2N** standby
current;
Fast PDN Exit
Active
670
508
625
508
625
508
mA
mA
TBD
TBD
All banks open; tCK = tCK(I ), CKE is LOW; Other control
CC
MRS(12) = 0
power-
ICC3P**
and address bus inputs are STABLE; Data bus inputs are
down
current;
Slow PDN Exit
MRS(12) = 1
FLOATING
Active
ICC3N** standby
current;
All banks open; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS#
CC
is HIGH between valid coCmCmands; OthCeCr control and address bus inputs are
850
805
805
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
SWITCHING; Data bus inputs are SWITCHING
Operating All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(I
;
)
CC
ICC4W* burst write tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between valid commands;
1,795 1,570 1,435
1,795 1,570 1,435
2,380 2,335 2,290
CC
CC
current;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0;
ICC4R* burst read tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between
CC
CC
CC
current;
valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W.
Burst auto tCK = tCK(I ); Refresh command at every tRC(I ) interval; CKE is HIGH; CS# is HIGH
refresh
current;
CC
CC
ICC5**
between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self
refresh
current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus
Normal
ICC6**
90
90
90
inputs are FLOATING; Data bus inputs are FLOATING
Operating
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(I ) - 1*tCK(I
;
)
CC
tCK = tCK(I ); tRC = tRC(I ); tRRD = tRRD MIN(I ) = 1*tCK(I ); CKE is HIGH; CS# is HIGCHC
bank
CC
CC
CC
between valid commands; Address bus inputs are STCACBLE during DESELECTs; Data
ICC7*
interleave
read
current;
3,100 2,920 2,740
mA
TBD
bus inputs are SWITCHING
Notes:
CC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
I
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
May 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
