请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

HYS72T512341HHP

型号：

HYS72T512341HHP

描述：

240引脚注册DDR2 SDRAM模组[ 240-Pin Registered DDR2 SDRAM Modules ]

品牌：

QIMONDA[ QIMONDA AG ]

页数：

32 页

PDF大小：

1705 K

下载PDF手册
December 2006  
HYS72T512341HHP–[3.7/5]–B  
HYS72T512341HJP–[3.7/5]–B  
HYS72T512341HKP–[3.7/5]–B  
240-Pin Registered DDR2 SDRAM Modules  
DDR2 SDRAM  
RoHs Compliant Products  
Internet Data Sheet  
Rev. 1.0  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
HYS72T512341HHP–[3.7/5]–B  
, HYS72T512341HJP–[3.7/5]–B, HYS72T512341HKP–[3.7/5]–B  
Revision History: 2006-12, Rev. 1.0  
Page  
Subjects (major changes since last revision)  
All  
Qimonda update  
All  
Adapted internet edition  
All  
Added HYS672T512341HJP-[3.7/5]-B and HYS72T512341HKP-[3.7/5]-B modules  
SPD codes updated  
Chapter 4  
Previous Revision: 2006-07, Rev. 0.5  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send your proposal (including a reference to this document) to:  
techdoc@qimonda.com  
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07  
11032006-VX0M-M6IH  
2
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
1
Overview  
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules product family and describes its main  
characteristics.  
1.1  
Features  
•
•
240-pin PC2–4200 and PC2–3200 DDR2 SDRAM  
memory modules.  
Four rank 512M ×72 module organization, and 512M ×4  
chip organization  
Registered DIMM Parity bit for address and control bus  
4 GB module built with 512 Mbit DDR2 SDRAMs in SG-  
A4FBGA-60 and PG-A4FBGA-60 chipsize packages.  
Standard Double-Data-Rate-Two Synchronous DRAMs  
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power  
supply  
•
•
•
•
•
Programmable self refresh rate via EMRS2 setting  
Programmable partial array refresh via EMRS2 settings  
DCC enabling via EMRS2 setting  
All inputs and outputs SSTL_18 compatible  
Off-Chip Driver Impedance Adjustment (OCD) and On-Die  
Termination (ODT)  
•
•
•
•
Serial Presence Detect with E2PROM  
RDIMM Dimensions (nominal): 18,30 mm high, 133.35  
mm wide  
•
•
•
All speed grades faster than DDR2–400 comply with  
DDR2–400 timing specifications.  
•
•
Programmable CAS Latencies (3, 4, 5),  
Burst Length (4 & 8) and Burst Type  
Auto Refresh (CBR) and Self Refresh  
RoHS compliant products1)  
TABLE 1  
Performance Table  
Product Type Speed Code  
Speed Grade  
–3.7  
–5  
Unit  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
—
Max. Clock Frequency  
@CL5  
@CL4  
@CL3  
fCK5  
fCK4  
fCK3  
tRCD  
tRP  
266  
266  
200  
15  
200  
200  
200  
15  
MHz  
MHz  
MHz  
ns  
Min. RAS-CAS-Delay  
Min. Row Precharge Time  
Min. Row Active Time  
Min. Row Cycle Time  
15  
15  
ns  
tRAS  
tRC  
45  
40  
ns  
60  
55  
ns  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
Rev. 1.0, 2006-12  
3
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
1.2  
Description  
The Qimonda HYS72T512341H[H/J/K]P–[3.7/5]–B module  
family are Very Low Profile Registered DIMM (with parity)  
modules with 18,3 mm height based on DDR2 technology.  
DIMMs are available as ECC modules in 512M ×72 (4 GB)  
organization and density, intended for mounting into 240-Ball  
connector sockets.  
capacitive loading to the system bus, but adds one cycle to  
the SDRAM timing. Decoupling capacitors are mounted on  
the PCB board. The DIMMs feature serial presence detect  
based on a serial E2PROM device using the 2-ball I2C  
protocol. The first 128 bytes are programmed with  
configuration data and the second 128 bytes are available to  
the customer.  
The memory array is designed with 512-Mbit Double-Data-  
Rate-Two (DDR2) Synchronous DRAMs. All control and  
address signals are re-driven on the DIMM using register  
devices and a PLL for the clock distribution. This reduces  
TABLE 2  
Ordering Information for RoHS Compliant Products  
Product Type1)  
Compliance Code2)  
Description  
SDRAM Technology  
PC2–4200  
HYS72T512341HHP–3.7–B  
HYS72T512341HJP–3.7–B  
HYS72T512341HKP–3.7–B  
PC2–3200  
4 GB 4R×4 PC2–4200P–444–12–ZZ  
4 GB 4R×4 PC2–4200P–444–12–ZZ  
4 GB 4R×4 PC2–4200P–444–12–ZZ  
4 Rank ECC  
4 Rank ECC  
4 Rank ECC  
4 GB (×4)  
4 GB (×4)  
4 GB (×4)  
HYS72T512341HHP–5–B  
HYS72T512341HJP–5–B  
HYS72T512341HKP–5–B  
4 GB 4R×4 PC2–3200P–333–12–ZZ  
4 GB 4R×4 PC2–3200P–333–12–ZZ  
4 GB 4R×4 PC2–3200P–333–12–ZZ  
4 Rank ECC  
4 Rank ECC  
4 Rank ECC  
4 GB (×4)  
4 GB (×4)  
4 GB (×4)  
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T512341HJP-3.7-B, indicating Rev.  
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data  
sheet.  
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12”, where 4200P  
means Registered DIMM modules (Parity bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)  
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2.  
TABLE 3  
Address Format  
DIMM Density Module Organization Memory Ranks ECC/  
Non-ECC  
# of SDRAMs # of row/bank/column bits  
4 GB  
512M ×72  
4
ECC  
18 ×4  
14/2/11  
TABLE 4  
Components on Modules  
Product Type  
DRAM Components  
DRAM Density  
DRAM Organisation  
512M ×4  
Note  
1)  
HYS72T512341HHP  
HYS72T512341HJP  
HYS72T512341HKP  
HYB18T2G401BHF  
512 Mbit  
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.  
Rev. 1.0, 2006-12  
4
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
2
Pin Configuration  
2.1  
Pin Configuration  
The pin configuration of the Registered DDR2 SDRAM DIMM  
is listed by function in Table 5 (240 pins). The abbreviations  
used in columns Pin and Buffer Type are explained in Table 6  
and Table 7 respectively. The pin numbering is depicted in  
Figure 1.  
TABLE 5  
Pin Configuration of RDIMM  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
Clock Signals  
185  
186  
52  
CK0  
CK0  
CKE0  
CKE1  
NC  
I
SSTL  
SSTL  
SSTL  
SSTL  
—
Clock Signal CK0, Complementary Clock Signal CK0  
I
I
Clock Enables 1:0  
Note: 2-Ranks module  
171  
I
NC  
Not Connected  
Note: 1-Rank module  
Control Signals  
193  
S0  
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
CMOS  
Chip Select Rank 3:0  
76  
S1  
220  
S2  
221  
S3  
192  
RAS  
CAS  
WE  
RESET  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
74  
73  
18  
Register Reset  
Address Signals  
71  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
190  
54  
Bank Address Bus 2  
Greater than 512Mb DDR2 SDRAMS  
NC  
I
SSTL  
Not Connected  
Less than 1Gb DDR2 SDRAMS  
Rev. 1.0, 2006-12  
5
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
188  
183  
63  
A0  
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
—
Address Bus 12:0, Address Signal 10/AutoPrecharge  
A1  
I
A2  
I
182  
61  
A3  
I
A4  
I
60  
A5  
I
180  
58  
A6  
I
A7  
I
179  
177  
70  
A8  
I
A9  
I
A10  
AP  
A11  
A12  
A13  
NC  
I
I
57  
I
176  
196  
I
I
Address Signal 13  
NC  
Not Connected  
Note: Non CA parity modules based on 256 Mbit component  
174  
A14  
A15  
I
I
SSTL  
SSTL  
Not Connected  
Not Connected  
173  
Data Signals  
3
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
DQ9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
4
9
10  
122  
123  
128  
129  
12  
13  
Rev. 1.0, 2006-12  
6
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
21  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ48  
DQ49  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
Data Input/Output pins  
22  
131  
132  
140  
141  
24  
25  
30  
31  
143  
144  
149  
150  
33  
34  
39  
40  
152  
153  
158  
159  
80  
81  
86  
87  
199  
200  
205  
206  
89  
Data Bus 63:0  
90  
95  
96  
208  
209  
214  
215  
98  
99  
Rev. 1.0, 2006-12  
7
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
107  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Bus 63:0  
108  
217  
218  
226  
227  
110  
111  
116  
117  
229  
230  
235  
236  
Check Bits  
42  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Check Bits 7:0  
Check Bit Input / Output pins  
43  
48  
49  
161  
162  
167  
168  
Data Strobe Bus  
7
DQS0  
DQS0  
DQS1  
DQS1  
DQS2  
DQS2  
DQS3  
DQS3  
DQS4  
DQS4  
DQS5  
DQS5  
DQS6  
DQS6  
DQS7  
DQS7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
6
16  
15  
28  
27  
37  
36  
84  
83  
93  
92  
105  
104  
114  
113  
Rev. 1.0, 2006-12  
8
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
46  
DQS8  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Strobes 17:0  
45  
DQS8  
125  
126  
134  
135  
146  
147  
155  
156  
202  
203  
211  
212  
223  
224  
232  
233  
164  
165  
Data Mask  
125  
134  
146  
155  
202  
211  
223  
232  
164  
EEPROM  
120  
119  
239  
240  
101  
Parity  
55  
DQS9  
DQS9  
DQS10  
DQS10  
DQS11  
DQS11  
DQS12  
DQS12  
DQS13  
DQS13  
DQS14  
DQS14  
DQS15  
DQS15  
DQS16  
DQS16  
DQS17  
DQS17  
DM0  
DM1  
DM2  
DM3  
DM4  
DM5  
DM6  
DM7  
DM8  
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Data Masks 8:0  
Note: ×8 based module  
SCL  
SDA  
SA0  
SA1  
SA2  
I
CMOS  
OD  
Serial Bus Clock  
I/O  
Serial Bus Data  
I
I
I
CMOS  
CMOS  
CMOS  
Serial Address Select Bus 2:0  
ERR_OUT  
PAR_IN  
O
I
CMOS  
CMOS  
Parity bits  
Rev. 1.0, 2006-12  
9
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Pin No.  
Name  
Pin  
Buffer  
Function  
Type Type  
Power Supplies  
1
VREF  
AI  
—
—
—
I/O Reference Voltage  
EEPROM Power Supply  
I/O Driver Power Supply  
238  
VDDSPD  
PWR  
PWR  
51, 56, 62, 72, 75, VDDQ  
78, 170, 175,, 181,  
191, 194  
53, 59, 64, 67, 69, VDD  
172, 178, 184,,  
187, 189, 197  
PWR  
GND  
—
—
Power Supply  
Ground Plane  
2, 5, 8, 11, 14, 17, VSS  
20, 23, 26, 29, 32,  
35, 38, 41, 44, 47,  
50, 65, 66, 79, 82,  
85, 88, 91, 94, 97,  
100, 103, 106, 109,  
112, 115, 118, 121,  
124, 127, 130, 133,  
136, 139, 142, 145,  
148, 151, 154, 157,  
160, 163, 166, 169,  
198, 201, 204, 207,  
210, 213, 216, 219,  
222, 225, 228, 231,  
234, 237  
Other Pins  
19, 55, 68, 102,  
137, 138, 173  
NC  
NC  
—
Not connected  
195  
77  
ODT0  
ODT1  
NC  
I
SSTL  
SSTL  
—
On-Die Termination Control 1:0  
Note: 2-Ranks module  
I
NC  
Note: 1-Rank modules  
Rev. 1.0, 2006-12  
10  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
TABLE 6  
Abbreviations for Buffer Type  
Abbreviation  
Description  
SSTL  
CMOS  
OD  
Serial Stub Terminated Logic (SSTL_18)  
CMOS Levels  
Open Drain. The corresponding pin has 2 operational states, active low and tristate,  
and allows multiple devices to share as a wire-OR.  
TABLE 7  
Abbreviations for Pin Type  
Abbreviation  
Description  
I
Standard input-only pin. Digital levels.  
Output. Digital levels.  
I/O is a bidirectional input/output signal.  
Input. Analog levels.  
Power  
O
I/O  
AI  
PWR  
GND  
NU  
NC  
Ground  
Not Usable  
Not Connected  
Rev. 1.0, 2006-12  
11  
11032006-VX0M-M6IH  
                                           
                                            
                                             
                                                                                                                    
                                                                                                                     
                                                                                                                      
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
FIGURE 1  
Pin Configuration for RDIMM (240 pins)  
95()  
'4ꢀ  
966  
'46ꢀ  
'4ꢈ  
966  
'4ꢇ  
'46ꢁ  
966  
1&  
'4ꢁꢀ  
966  
'4ꢁꢂ  
'46ꢈ  
966  
'4ꢁꢇ  
'4ꢈꢉ  
966  
'46ꢅ  
'4ꢈꢊ  
966  
&%ꢁ  
'46ꢋ  
966  
&%ꢅ  
9''4  
9''  
1&  
$ꢁꢁ  
9''  
$ꢉ  
ꢃ 3LQꢄꢀꢀꢁ  
ꢃ 3LQꢄꢀꢀꢅ  
ꢃ 3LQꢄꢀꢀꢆ  
ꢃ 3LQꢄꢀꢀꢂ  
ꢃ 3LQꢄꢀꢀꢇ  
ꢃ 3LQꢄꢀꢁꢁ  
ꢃ 3LQꢄꢀꢁꢅ  
ꢃ 3LQꢄꢀꢁꢆ  
ꢃ 3LQꢄꢀꢁꢂ  
ꢃ 3LQꢄꢀꢁꢇ  
3LQꢄꢁꢈꢁ ꢃ 966  
3LQꢄꢁꢈꢈ ꢃ '4ꢉ  
966  
'4ꢁ  
'46ꢀ ꢃ 3LQꢄꢀꢀꢊ  
966  
'4ꢅ  
'4ꢋ  
966  
'46ꢁ ꢃ 3LQꢄꢀꢁꢊ  
5(6(7 ꢃ 3LQꢄꢀꢁꢋ  
ꢃ 3LQꢄꢀꢀꢈ  
ꢃ 3LQꢄꢀꢀꢉ  
3LQꢄꢁꢈꢅ ꢃ '4ꢆ  
3LQꢄꢁꢈꢉ ꢃ 966  
3LQꢄꢁꢈꢆ ꢃ '0ꢀꢌ'46ꢇ  
3LQꢄꢁꢈꢊ ꢃ 1&ꢌ'46ꢇ  
3LQꢄꢁꢈꢂ ꢃ 966  
ꢃ 3LQꢄꢀꢀꢋ  
ꢃ 3LQꢄꢀꢁꢀ  
ꢃ 3LQꢄꢀꢁꢈ  
ꢃ 3LQꢄꢀꢁꢉ  
3LQꢄꢁꢈꢋ ꢃ '4ꢊ  
3LQꢄꢁꢈꢇ ꢃ '4ꢂ  
3LQꢄꢁꢅꢀ ꢃ 966  
3LQꢄꢁꢅꢁ ꢃ '4ꢁꢈ  
3LQꢄꢁꢅꢈ ꢃ '4ꢁꢅ  
3LQꢄꢁꢅꢅ ꢃ 966  
3LQꢄꢁꢅꢉ ꢃ '0ꢁꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢆ ꢃ 1&ꢌ'46ꢁꢀ  
3LQꢄꢁꢅꢊ ꢃ 966  
3LQꢄꢁꢅꢂ ꢃ 1&  
3LQꢄꢁꢅꢇ ꢃ 966  
3LQꢄꢁꢅꢋ ꢃ 1&  
3LQꢄꢁꢉꢀ ꢃ '4ꢁꢉ  
3LQꢄꢁꢉꢁ ꢃ '4ꢁꢆ  
966  
ꢃ 3LQꢄꢀꢈꢀ  
ꢃ
ꢃ
3LQꢄꢀꢈꢁ  
3LQꢄꢀꢈꢅ  
ꢃ 3LQꢄꢀꢈꢆ  
ꢃ 3ꢄLQꢄꢀꢈꢂ  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
'4ꢁꢁ  
'4ꢁꢊ  
966  
'46ꢈ  
'4ꢁꢋ  
966  
'4ꢈꢆ  
'46ꢅ  
966  
'4ꢈꢂ  
&%ꢀ  
966  
'46ꢋ  
&%ꢈ  
966  
&.(ꢀ  
3LQꢄꢀꢈꢈ  
3LQꢄꢀꢈꢉ  
3LQꢄꢁꢉꢈ  
3LQꢄꢁꢉꢉ  
3LQꢄꢁꢉꢊ  
3LQꢄꢁꢉꢋ  
3LQꢄꢁꢆꢀ  
3LQꢄꢁꢆꢈ  
3LQꢄꢁꢆꢉ  
3LQꢄꢁꢆꢊ  
3LQꢄꢁꢆꢋ  
3LQꢄꢁꢊꢀ  
3LQꢄꢁꢊꢈ  
3LQꢄꢁꢊꢉ  
3LQꢄꢁꢊꢊ  
3LQꢄꢁꢊꢋ  
3LQꢄꢁꢂꢀ  
3LQꢄꢁꢂꢈ  
3LQꢄꢁꢂꢉ  
3LQꢄꢁꢂꢊ  
3LQꢄꢁꢂꢋ  
3LQꢄꢁꢋꢀ  
3LQꢄꢁꢋꢈ  
3LQꢄꢁꢋꢉ  
966  
3LQꢄꢁꢉꢅ ꢃ '4ꢈꢀ  
3LQꢄꢁꢉꢆ ꢃ 966  
3ꢄLQꢄꢁꢉꢂ ꢃ 1&ꢌ'46ꢁꢁ  
3LQꢄꢁꢉꢇ ꢃ '4ꢈꢈ  
3LQꢄꢁꢆꢁ ꢃ 966  
3LQꢄꢁꢆꢅ ꢃ '4ꢈꢇ  
3LQꢄꢁꢆꢆ ꢃ '0ꢅꢌ'46ꢁꢈ  
3LQꢄꢁꢆꢂ ꢃ 966  
3LQꢄꢁꢆꢇ ꢃ '4ꢅꢁ  
3LQꢄꢁꢊꢁ ꢃ &%ꢉ  
3LQꢄꢁꢊꢅ ꢃ 966  
3LQꢄꢁꢊꢆ ꢃ 1&ꢌ'46ꢁꢂ  
3LQꢄꢁꢊꢂ ꢃ &%ꢊ  
3LQꢄꢁꢊꢇ ꢃ 966  
3LQꢄꢁꢂꢁ ꢃ 1&ꢌ&.(ꢁ  
3LQꢄꢁꢂꢅ ꢃ 1&ꢄꢌꢄ$ꢁꢆ  
3LQꢄꢁꢂꢆ ꢃ 9''4  
3LQꢄꢁꢂꢂ ꢃ $ꢇ  
'4ꢈꢁ  
'0ꢈꢌ'46ꢁꢁ  
966  
'4ꢈꢅ  
'4ꢈꢋ  
966  
1&ꢌ'46ꢁꢈ  
'4ꢅꢀ  
966  
&%ꢆ  
'0ꢋꢌ'46ꢁꢂ  
966  
&%ꢂ  
9''4  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢀꢈꢊ  
3LQꢄꢀꢈꢋ  
3LQꢄꢀꢅꢀ  
3LQꢄꢀꢅꢈ  
3LQꢄꢀꢅꢉ  
3LQꢄꢀꢅꢊ  
3LQꢄꢀꢅꢋ  
3LQꢄꢀꢉꢀ  
3LQꢄꢀꢉꢈ  
3LQꢄꢀꢉꢉ  
3LQꢄꢀꢉꢊ  
3LQꢄꢀꢉꢋ  
3LQꢄꢀꢆꢀ  
3LQꢄꢀꢆꢈ  
ꢃ 3LQꢄꢀꢈꢇ  
ꢃ 3LQꢄꢀꢅꢁ  
ꢃ 3LQꢄꢀꢅꢅ  
ꢃ 3LQꢄꢀꢅꢆ  
ꢃ 3LQꢄꢀꢅꢂ  
ꢃ 3LQꢄꢀꢅꢇ  
ꢃ 3LQꢄꢀꢉꢁ  
ꢃ 3LQꢄꢀꢉꢅ  
ꢃ 3LQꢄꢀꢉꢆ  
ꢃ 3LQꢄꢀꢉꢂ  
ꢃ 3LQꢄꢀꢉꢇ  
ꢃ 3LQꢄꢀꢆꢁ  
ꢃ 3LQꢄꢀꢆꢅ  
ꢃ 3LQꢄꢀꢆꢆ  
ꢃ 3LQꢄꢀꢆꢂ  
ꢃ 3LQꢄꢀꢆꢇ  
ꢃ 3LQꢄꢀꢊꢁ  
ꢃ 3LQꢄꢀꢊꢅ  
9''  
1&ꢌ$ꢁꢉ  
$ꢁꢈ  
9''  
$ꢊ  
ꢃ
1&ꢌ%$ꢈ 3LQꢄꢀꢆꢉ  
9''4  
$ꢂ  
$ꢆ  
9''4  
9''  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
3LQꢄꢀꢆꢊ  
3LQꢄꢀꢆꢋ  
3LQꢄꢀꢊꢀ  
3LQꢄꢀꢊꢈ  
3LQꢄꢀꢊꢉ  
3LQꢄꢁꢂꢇ ꢃ $ꢋ  
3LQꢄꢁꢋꢁ ꢃ 9''4  
3LQꢄꢁꢋꢅ ꢃ $ꢁ  
$ꢅ  
9''  
$ꢈ  
966  
ꢃ 3LQꢄꢀꢊꢆ  
ꢃ 3LQꢄꢀꢊꢂ  
ꢃ 3LQꢄꢀꢊꢇ  
ꢃ 3LQꢄꢀꢂꢁ  
ꢃ 3LQꢄꢀꢂꢅ  
ꢃ 3LQꢄꢀꢂꢆ  
3LQꢄꢁꢋꢆ ꢃ &.ꢀ  
3LQꢄꢁꢋꢂ ꢃ 9''  
3LQꢄꢁꢋꢇ ꢃ 9''  
3LQꢄꢁꢇꢁ ꢃ 9''4  
3LQꢄꢁꢇꢅ ꢃ 6ꢀ  
3LQꢄꢁꢇꢆ ꢃ 2'7ꢀ  
3LQꢄꢁꢇꢂ ꢃ 9''  
3LQꢄꢁꢇꢇ ꢃ '4ꢅꢊ  
3LQꢄꢈꢀꢁ ꢃ 966  
3LQꢄꢈꢀꢅ ꢃ 1&ꢌ'46ꢁꢅ  
3LQꢄꢈꢀꢆ ꢃ '4ꢅꢋ  
3LQꢄꢈꢀꢂ ꢃ 966  
3LQꢄꢈꢀꢇ ꢃ '4ꢉꢆ  
3LQꢄꢈꢁꢁ ꢃ '0ꢆꢌ'46ꢁꢉ  
3LQꢄꢈꢁꢅ ꢃ 966  
3LQꢄꢈꢁꢆ ꢃ '4ꢉꢂ  
3LQꢄꢈꢁꢂ ꢃ '4ꢆꢈ  
3LQꢄꢈꢁꢇ ꢃ 966  
3LQꢄꢈꢈꢁ ꢃ 6ꢅ  
3LQꢄꢈꢈꢅ ꢃ '0ꢊꢌ'46ꢁꢆ  
3LQꢄꢈꢈꢆ ꢃ 966  
3LQꢄꢈꢈꢂ ꢃ '4ꢆꢆ  
3LQꢄꢈꢈꢇ ꢃ '4ꢊꢀ  
3LQꢄꢈꢅꢁ ꢃ 966  
3LQꢄꢈꢅꢅ ꢃ 1&ꢌ'46ꢁꢊ  
3LQꢄꢈꢅꢆ ꢃ '4ꢊꢈ  
3LQꢄꢈꢅꢂ 966  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
966  
1&  
3LQꢄꢀꢊꢊ  
3LQꢄꢀꢊꢋ  
3LQꢄꢁꢋꢊ  
3LQꢄꢁꢋꢋ  
3LQꢄꢁꢇꢀ  
3LQꢄꢁꢇꢈ  
3LQꢄꢁꢇꢉ  
3LQꢄꢁꢇꢊ  
3LQꢄꢁꢇꢋ  
3LQꢄꢈꢀꢀ  
3LQꢄꢈꢀꢈ  
3LQꢄꢈꢀꢉ  
3LQꢄꢈꢀꢊ  
3LQꢄꢈꢀꢋ  
3LQꢄꢈꢁꢀ  
3LQꢄꢈꢁꢈ  
3LQꢄꢈꢁꢉ  
3LQꢄꢈꢁꢊ  
3LQꢄꢈꢁꢋ  
3LQꢄꢈꢈꢀ  
3LQꢄꢈꢈꢈ  
3LQꢄꢈꢈꢉ  
3LQꢄꢈꢈꢊ  
3LQꢄꢈꢈꢋ  
3LQꢄꢈꢅꢀ  
3LQꢄꢈꢅꢈ  
3LQꢄꢈꢅꢉ  
3LQꢄꢈꢅꢊ  
3LQꢄꢈꢅꢋ  
3LQꢄꢈꢉꢀ  
&.ꢀ  
$ꢀ  
%$ꢁ  
5$6  
9''4  
1&ꢌ$ꢁꢅ  
966  
'4ꢅꢂ  
'0ꢉꢌ'46ꢁꢅ  
966  
'4ꢅꢇ  
'4ꢉꢉ  
966  
9''  
9''  
%$ꢀ  
:(  
9''4  
ꢃ
$ꢁꢀꢌ$3 3LQꢄꢀꢂꢀ  
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
9''4  
&$6  
1&ꢌ6ꢁ  
9''4  
'4ꢅꢈ  
966  
'46ꢉ  
'4ꢅꢉ  
966  
'4ꢉꢁ  
'46ꢆ  
966  
'4ꢉꢅ  
'4ꢉꢋ  
966  
1&  
'46ꢊ  
966  
'4ꢆꢁ  
'4ꢆꢊ  
966  
'46ꢂ  
'4ꢆꢋ  
966  
3LQꢄꢀꢂꢈ  
3LQꢄꢀꢂꢉ  
3LQꢄꢀꢂꢊ  
3LQꢄꢀꢂꢋ  
3LQꢄꢀꢋꢀ  
3LQꢄꢀꢋꢈ  
3LQꢄꢀꢋꢉ  
3LQꢄꢀꢋꢊ  
3LQꢄꢀꢋꢋ  
3LQꢄꢀꢇꢀ  
3LQꢄꢀꢇꢈ  
3LQꢄꢀꢇꢉ  
3LQꢄꢀꢇꢊ  
3LQꢄꢀꢇꢋ  
3LQꢄꢁꢀꢀ  
3LQꢄꢁꢀꢈ  
3LQꢄꢁꢀꢉ  
3LQꢄꢁꢀꢊ  
3LQꢄꢁꢀꢋ  
3LQꢄꢁꢁꢀ  
3LQꢄꢁꢁꢈ  
3LQꢄꢁꢁꢉ  
3LQꢄꢁꢁꢊ  
3LQꢄꢁꢁꢋ  
3LQꢄꢁꢈꢀ  
1&ꢌ2'7ꢁ ꢃ 3LQꢄꢀꢂꢂ  
966  
ꢃ 3LQꢄꢀꢂꢇ  
ꢃ 3LQꢄꢀꢋꢁ  
ꢃ 3LQꢄꢀꢋꢅ  
ꢃ 3LQꢄꢀꢋꢆ  
ꢃ 3LQꢄꢀꢋꢂ  
ꢃ 3LQꢄꢀꢋꢇ  
ꢃ 3LQꢄꢀꢇꢁ  
ꢃ 3LQꢄꢀꢇꢅ  
ꢃ 3LQꢄꢀꢇꢆ  
ꢃ 3LQꢄꢀꢇꢂ  
ꢃ 3LQꢄꢀꢇꢇ  
ꢃ 3LQꢄꢁꢀꢁ  
ꢃ 3LQꢄꢁꢀꢅ  
ꢃ 3LQꢄꢁꢀꢆ  
ꢃ 3LQꢄꢁꢀꢂ  
ꢃ 3LQꢄꢁꢀꢇ  
ꢃ 3LQꢄꢁꢁꢁ  
ꢃ 3LQꢄꢁꢁꢅ  
ꢃ 3LQꢄꢁꢁꢆ  
ꢃ 3LQꢄꢁꢁꢂ  
ꢃ 3LQꢄꢁꢁꢇ  
'4ꢅꢅ  
'46ꢉ  
966  
'4ꢅꢆ  
'4ꢉꢀ  
966  
'46ꢆ  
'4ꢉꢈ  
966  
'4ꢉꢇ  
6$ꢈ  
1&ꢌ'46ꢁꢉ  
'4ꢉꢊ  
966  
'4ꢆꢅ  
6ꢈ  
966  
966  
1&ꢌ'46ꢁꢆ  
'4ꢆꢉ  
966  
'4ꢊꢁ  
'0ꢂꢌ'46ꢁꢊ  
966  
'4ꢊꢅ  
9''63'  
6$ꢁ  
'46ꢊ  
'4ꢆꢀ  
966  
'4ꢆꢂ  
'46ꢂ  
966  
'4ꢆꢇ  
6'$  
3LQꢄꢈꢅꢇ 6$ꢀ  
0337ꢀꢁꢂꢀB)6  
6&/  
Rev. 1.0, 2006-12  
11032006-VX0M-M6IH  
12  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
3
Electrical Characteristics  
3.1  
Absolute Maximum Ratings  
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.  
TABLE 8  
Absolute Maximum Ratings  
Symbol  
Parameter  
Rating  
Min.  
Unit  
Note  
Max.  
1)  
VDD  
Voltage on VDD pin relative to VSS  
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
–1.0  
–0.5  
–0.5  
–0.5  
–55  
+2.3  
+2.3  
+2.3  
+2.3  
+100  
V
1)2)  
1)2)  
1)  
VDDQ  
VDDL  
V
V
VIN, VOUT  
TSTG  
V
1)2)  
°C  
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.  
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.  
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other  
conditions above those indicated in the operational sections of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods may affect reliability.  
TABLE 9  
DRAM Component Operating Temperature Range  
Symbol  
Parameter  
Rating  
Unit  
Note  
Min.  
Max.  
1)2)3)4)  
TOPER  
Operating Temperature  
0
90  
°C  
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.  
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case  
temperature must be maintained between 0 - 90 °C under all other specification parameters.  
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs  
4) When operating this product in the 80 °C to 90 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%  
Rev. 1.0, 2006-12  
13  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
3.2  
D.C. Characteristics  
TABLE 10  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Max.  
Operating temperature (ambient)  
DRAM Case Temperature  
TOPR  
TCASE  
TSTG  
0
+65  
+90  
+100  
+105  
90  
°C  
°C  
°C  
kPa  
%
1)2)3)4)  
5)  
0
Storage Temperature  
– 50  
+69  
10  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
PBar  
HOPR  
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported  
3) Above 80 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs  
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.  
5) Up to 3000 m.  
TABLE 11  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Typ.  
Max.  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
1.9  
V
1)  
2)  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
0.49 × VDDQ  
0.5 × VDDQ  
0.51 × VDDQ  
V
VDDSPD  
VIH(DC)  
VIL (DC  
IL  
1.7  
—
—
—
—
3.6  
V
DC Input Logic High  
VREF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
)
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ  
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
Rev. 1.0, 2006-12  
14  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
3.3  
AC Characteristics  
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns).  
TABLE 12  
Speed Grade Definition Speed Bins for DDR2–533C and DDR2–400B  
Speed Grade  
DDR2–533C  
DDR2–400B  
Unit  
Note  
QAG Sort Name  
CAS-RCD-RP latencies  
–3.7  
–5  
4–4–4  
3–3–3  
tCK  
Parameter  
Symbol  
Min.  
Max.  
Min.  
Max.  
—
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)5)  
1)2)3)4)  
1)2)3)4)  
1)2)3)4)  
Clock Frequency  
@ CL = 3  
@ CL = 4  
@ CL = 5  
tCK  
5
8
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
3.75  
3.75  
45  
8
5
8
tCK  
8
5
8
Row Active Time  
Row Cycle Time  
RAS-CAS-Delay  
Row Precharge Time  
tRAS  
tRC  
tRCD  
tRP  
70000  
—
40  
55  
15  
15  
70000  
—
60  
15  
—
—
15  
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal  
OCD drive strength (EMRS(1) A1 = 0) only.  
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,  
input reference level is the crosspoint when in differential strobe mode  
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.  
4) The output timing reference voltage level is VTT  
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI  
t
.
Rev. 1.0, 2006-12  
15  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
3.4  
IDD Specifications and Conditions  
List of tables defining IDD Specifications and Conditions.  
•
•
•
Table 13 “IDD Measurement Conditions” on Page 16  
Table 14 “Definitions for IDD” on Page 17  
Table 15 “IDD Specification for HYS72T512341H[HJ/K]P–[3.7/5]–B” on Page 18  
TABLE 13  
DD Measurement Conditions  
I
Parameter  
Symbol Note  
1)2)3)4)5)  
Operating Current 0  
IDD0  
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between  
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.  
6)  
Operating Current 1  
IDD1  
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN  
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and  
control inputs are SWITCHING, Databus inputs are SWITCHING.  
Precharge Standby Current  
IDD2N  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,  
Databus inputs are SWITCHING.  
Precharge Power-Down Current  
Other control and address inputs are STABLE, Data bus inputs are FLOATING.  
IDD2P  
IDD2Q  
Precharge Quiet Standby Current  
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,  
Data bus inputs are FLOATING.  
Active Standby Current  
IDD3N  
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);  
IDD3P(0)  
IDD3P(1)  
IDD4R  
Active Power-Down Current  
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs  
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);  
6)  
Operating Current - Burst Read  
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX  
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data  
bus inputs are SWITCHING; IOUT = 0mA.  
Operating Current - Burst Write  
IDD4W  
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN  
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are  
SWITCHING; Data Bus inputs are SWITCHING;  
Burst Refresh Current  
IDD5B  
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Rev. 1.0, 2006-12  
16  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Parameter  
Symbol Note  
1)2)3)4)5)  
Distributed Refresh Current  
IDD5D  
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid  
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.  
Self-Refresh Current  
IDD6  
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data  
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.  
6)  
All Bank Interleave Read Current  
IDD7  
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control  
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.  
1)  
2)  
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V  
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.  
3) Definitions for IDD see Table 14  
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P  
5) For details and notes see the relevant Qimonda component data sheet  
6)  
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output  
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.  
TABLE 14  
Definitions for IDD  
Parameter  
LOW  
Description  
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN  
Inputs are stable at a HIGH or LOW level  
Inputs are VREF = VDDQ /2  
STABLE  
FLOATING  
SWITCHING  
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control  
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ  
signals not including mask or strobes  
Rev. 1.0, 2006-12  
17  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
TABLE 15  
DD Specification for HYS72T512341H[HJ/K]P–[3.7/5]–B  
I
Product Type  
Organization  
HYS72T512341H[H/J/K]P–3.7–B  
HYS72T512341H[HJ/K]P–5–B  
Unit  
Note1)  
4 GB  
4 Ranks  
×72  
4 GB  
4 Ranks  
×72  
–3.7  
–5  
Symbol  
Max.  
Max.  
2)  
IDD0  
2780  
2960  
3970  
1730  
3750  
4330  
3250  
1880  
3590  
3590  
3950  
1880  
360  
2450  
2610  
3420  
1480  
3280  
3780  
2700  
1620  
3060  
3060  
3600  
1620  
504  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
2)  
IDD1  
3)  
IDD2N  
3)  
IDD2P  
3)  
IDD2Q  
3)  
IDD3N  
3)4)  
3)5)  
2)  
IDD3P( MRS = 0)  
IDD3P( MRS = 1)  
IDD4R  
2)  
IDD4W  
IDD5B  
2)  
3)6)  
3)6)  
2)  
IDD5D  
IDD6  
IDD7  
4220  
3890  
1) Calculated values from component data. ODT disabled. IDD1,  
I
DD4R, and IDD7, are defined with the outputs disabled.  
2) The other rank is in IDD2P Precharge Power-Down Current mode  
3) Both ranks are in the same IDDcurrent mode  
4) Fast: MRS(12)=0  
5) Slow: MRS(12)=1  
6)  
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C  
Rev. 1.0, 2006-12  
18  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
4
SPD Codes  
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands  
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.  
List of SPD Code Tables  
•
•
Table 16 “SPD Codes for PC2-4200P-444” on Page 19  
Table 17 “SPD Codes for PC2-3200P-333” on Page 24  
TABLE 16  
SPD Codes for PC2-4200P-444  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–4200P–444 PC2–4200P–444 PC2–4200P–444  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
0
Programmed SPD Bytes in EEPROM  
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
80  
08  
08  
0E  
0B  
03  
48  
00  
05  
3D  
50  
06  
81  
04  
80  
08  
08  
0E  
0B  
03  
48  
00  
05  
3D  
50  
06  
81  
04  
80  
08  
08  
0E  
0B  
03  
48  
00  
05  
3D  
50  
06  
81  
04  
1
2
3
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
4
5
6
7
Not used  
8
Interface Voltage Level  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
10  
11  
12  
13  
AC SDRAM @ CLMAX (Byte 18) [ns]  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Rev. 1.0, 2006-12  
19  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–4200P–444 PC2–4200P–444 PC2–4200P–444  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
Error Checking SDRAM Width  
Not used  
04  
00  
0C  
04  
38  
01  
01  
05  
07  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
25  
37  
10  
22  
3C  
1E  
1E  
00  
04  
00  
0C  
04  
38  
01  
01  
05  
07  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
25  
37  
10  
22  
3C  
1E  
1E  
00  
04  
00  
0C  
04  
38  
01  
01  
05  
07  
3D  
50  
50  
60  
3C  
1E  
3C  
2D  
01  
25  
37  
10  
22  
3C  
1E  
1E  
00  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]  
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
Rev. 1.0, 2006-12  
20  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–4200P–444 PC2–4200P–444 PC2–4200P–444  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
00  
3C  
69  
80  
1E  
28  
0F  
50  
7A  
43  
29  
36  
21  
41  
2A  
40  
1E  
22  
C4  
8C  
61  
78  
12  
9F  
7F  
7F  
00  
3C  
69  
80  
1E  
28  
0F  
50  
7A  
43  
29  
36  
21  
41  
2A  
40  
1E  
22  
C4  
8C  
61  
78  
12  
9F  
7F  
7F  
00  
3C  
69  
80  
1E  
28  
0F  
50  
7A  
43  
29  
36  
21  
41  
2A  
40  
1E  
22  
C4  
8C  
61  
78  
12  
9F  
7F  
7F  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
PLL Relock Time  
CASE.MAX Delta / ∆T4R4W Delta  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)  
∆T2P (DT2P)  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
Manufacturer’s JEDEC ID Code (1)  
Manufacturer’s JEDEC ID Code (2)  
Rev. 1.0, 2006-12  
21  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–4200P–444 PC2–4200P–444 PC2–4200P–444  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
Manufacturer’s JEDEC ID Code (3)  
Manufacturer’s JEDEC ID Code (4)  
Manufacturer’s JEDEC ID Code (5)  
Manufacturer’s JEDEC ID Code (6)  
Manufacturer’s JEDEC ID Code (7)  
Manufacturer’s JEDEC ID Code (8)  
Module Manufacturer Location  
Product Type, Char 1  
7F  
7F  
7F  
51  
00  
00  
xx  
7F  
7F  
7F  
51  
00  
00  
xx  
7F  
7F  
7F  
51  
00  
00  
xx  
37  
32  
54  
35  
31  
32  
33  
34  
31  
48  
48  
50  
33  
2E  
37  
42  
20  
20  
2x  
37  
32  
54  
35  
31  
32  
33  
34  
31  
48  
4A  
50  
33  
2E  
37  
42  
20  
20  
0x  
37  
32  
54  
35  
31  
32  
33  
34  
31  
48  
4B  
50  
33  
2E  
37  
42  
20  
20  
0x  
Product Type, Char 2  
Product Type, Char 3  
Product Type, Char 4  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Rev. 1.0, 2006-12  
22  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–4200P–444 PC2–4200P–444 PC2–4200P–444  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
92  
93  
94  
Test Program Revision Code  
xx  
xx  
xx  
xx  
00  
FF  
xx  
xx  
xx  
xx  
00  
FF  
xx  
xx  
xx  
xx  
00  
FF  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
95 - 98 Module Serial Number  
99 - 127 Not used  
128 -  
255  
Blank for customer use  
Rev. 1.0, 2006-12  
23  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
TABLE 17  
SPD Codes for PC2-3200P-333  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–3200P–333 PC2–3200P–333 PC2–3200P–333  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
0
Programmed SPD Bytes in EEPROM  
Total number of Bytes in EEPROM  
Memory Type (DDR2)  
80  
08  
08  
0E  
0B  
03  
48  
00  
05  
50  
60  
06  
81  
04  
04  
00  
0C  
04  
38  
01  
01  
05  
07  
50  
80  
08  
08  
0E  
0B  
03  
48  
00  
05  
50  
60  
06  
81  
04  
04  
00  
0C  
04  
38  
01  
01  
05  
07  
50  
80  
08  
08  
0E  
0B  
03  
48  
00  
05  
50  
60  
06  
81  
04  
04  
00  
0C  
04  
38  
01  
01  
05  
07  
50  
1
2
3
Number of Row Addresses  
Number of Column Addresses  
DIMM Rank and Stacking Information  
Data Width  
4
5
6
7
Not used  
8
Interface Voltage Level  
9
t
t
CK @ CLMAX (Byte 18) [ns]  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
AC SDRAM @ CLMAX (Byte 18) [ns]  
Error Correction Support (non-ECC, ECC)  
Refresh Rate and Type  
Primary SDRAM Width  
Error Checking SDRAM Width  
Not used  
Burst Length Supported  
Number of Banks on SDRAM Device  
Supported CAS Latencies  
DIMM Mechanical Characteristics  
DIMM Type Information  
DIMM Attributes  
Component Attributes  
t
CK @ CLMAX -1 (Byte 18) [ns]  
Rev. 1.0, 2006-12  
24  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–3200P–333 PC2–3200P–333 PC2–3200P–333  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
t
t
t
t
t
t
t
AC SDRAM @ CLMAX -1 [ns]  
CK @ CLMAX -2 (Byte 18) [ns]  
AC SDRAM @ CLMAX -2 [ns]  
RP.MIN [ns]  
60  
50  
60  
3C  
1E  
3C  
28  
01  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
2D  
0F  
50  
7A  
3B  
60  
50  
60  
3C  
1E  
3C  
28  
01  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
2D  
0F  
50  
7A  
3B  
60  
50  
60  
3C  
1E  
3C  
28  
01  
35  
47  
15  
27  
3C  
28  
1E  
00  
00  
37  
69  
80  
23  
2D  
0F  
50  
7A  
3B  
RRD.MIN [ns]  
RCD.MIN [ns]  
RAS.MIN [ns]  
Module Density per Rank  
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]  
AH.MIN and tCH.MIN [ns]  
DS.MIN [ns]  
DH.MIN [ns]  
WR.MIN [ns]  
WTR.MIN [ns]  
RTP.MIN [ns]  
Analysis Characteristics  
t
t
t
t
t
t
RC and tRFC Extension  
RC.MIN [ns]  
RFC.MIN [ns]  
CK.MAX [ns]  
DQSQ.MAX [ns]  
QHS.MAX [ns]  
PLL Relock Time  
CASE.MAX Delta / ∆T4R4W Delta  
T
Psi(T-A) DRAM  
∆T0 (DT0)  
Rev. 1.0, 2006-12  
25  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–3200P–333 PC2–3200P–333 PC2–3200P–333  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)  
∆T2P (DT2P)  
25  
36  
1E  
38  
2A  
38  
1D  
21  
C4  
8C  
59  
5C  
12  
D3  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
25  
36  
1E  
38  
2A  
38  
1D  
21  
C4  
8C  
59  
5C  
12  
D3  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
25  
36  
1E  
38  
2A  
38  
1D  
21  
C4  
8C  
59  
5C  
12  
D3  
7F  
7F  
7F  
7F  
7F  
51  
00  
00  
xx  
∆T3N (DT3N)  
∆T3P.fast (DT3P fast)  
∆T3P.slow (DT3P slow)  
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)  
∆T5B (DT5B)  
∆T7 (DT7)  
Psi(ca) PLL  
Psi(ca) REG  
∆TPLL (DTPLL)  
∆TREG (DTREG) / Toggle Rate  
SPD Revision  
Checksum of Bytes 0-62  
Manufacturer’s JEDEC ID Code (1)  
Manufacturer’s JEDEC ID Code (2)  
Manufacturer’s JEDEC ID Code (3)  
Manufacturer’s JEDEC ID Code (4)  
Manufacturer’s JEDEC ID Code (5)  
Manufacturer’s JEDEC ID Code (6)  
Manufacturer’s JEDEC ID Code (7)  
Manufacturer’s JEDEC ID Code (8)  
Module Manufacturer Location  
Product Type, Char 1  
37  
32  
54  
37  
32  
54  
37  
32  
54  
Product Type, Char 2  
Product Type, Char 3  
Rev. 1.0, 2006-12  
26  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Product Type  
Organization  
4 GByte  
×72  
4 GByte  
×72  
4 GByte  
×72  
4 Ranks (×4)  
4 Ranks (×4)  
4 Ranks (×4)  
Label Code  
PC2–3200P–333 PC2–3200P–333 PC2–3200P–333  
JEDEC SPD Revision  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Rev. 1.2  
HEX  
Byte#  
Description  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
Product Type, Char 4  
35  
31  
32  
33  
34  
31  
48  
48  
50  
35  
42  
20  
20  
20  
20  
2x  
xx  
xx  
xx  
xx  
00  
FF  
35  
31  
32  
33  
34  
31  
48  
4A  
50  
35  
42  
20  
20  
20  
20  
0x  
xx  
xx  
xx  
xx  
00  
FF  
35  
31  
32  
33  
34  
31  
48  
4B  
50  
35  
42  
20  
20  
20  
20  
0x  
xx  
xx  
xx  
xx  
00  
FF  
Product Type, Char 5  
Product Type, Char 6  
Product Type, Char 7  
Product Type, Char 8  
Product Type, Char 9  
Product Type, Char 10  
Product Type, Char 11  
Product Type, Char 12  
Product Type, Char 13  
Product Type, Char 14  
Product Type, Char 15  
Product Type, Char 16  
Product Type, Char 17  
Product Type, Char 18  
Module Revision Code  
Test Program Revision Code  
Module Manufacturing Date Year  
Module Manufacturing Date Week  
95 - 98 Module Serial Number  
99 - 127 Not used  
128 -  
255  
Blank for customer use  
Rev. 1.0, 2006-12  
27  
11032006-VX0M-M6IH  
                                                             
                                                             
                                                              
                                                              
                                                               
                                                                
                                                                
                                                                 
ꢉꢆꢍꢆꢄꢄ  
                                    
                                     
                                      
                                      
ꢆꢍꢇ 0$  
;ꢍꢄꢄ  
                                                                                                                
                                                                                                                 
                                                                                                                 
                                                                                                                  
ꢁꢉꢍꢂꢄꢄ  
                           
                            
                             
                             
ꢁꢄꢄ  
ꢁꢈꢀꢄꢄ  
                                                                                               
                                                                                               
                                                                                                
                                                                                                
ꢈꢍꢆ  
                                                              
                                                              
ꢄꢄ  
“
ꢈꢂꢄꢄ  
                                                                                                                                                   
ꢀꢍꢁꢄꢄ  
                                                                                                                                                   
                                                                                                                                                    
                                                                                                                                                     
                                                                                                               
                                                                                                               
                                                                                                                
                                                                                                                
ꢊꢅ  
                                             
                                              
ꢄꢄ  
ꢆꢆꢄꢄ  
                                                                                  
                                                                                   
“
                                                                                
ꢀꢍꢁꢄꢄ  
                                                                                 
                                                                                  
                                                                                  
ꢁꢍꢆꢄꢄ  
                                                            
                                                             
ꢁꢈꢁ  
                        
                         
                         
                         
ꢄꢄ  
ꢈꢉꢀꢄꢄ  
                                                                                               
                                                                                               
                                                                                                
                                                                                                
ꢅꢄ  
                            
0,1ꢍꢄꢄ  
                             
                             
                              
“
                                                                                                                                
ꢀꢍꢁꢄꢄ  
                                                                                                                                 
                                                                                                                                  
                                                                                                                                  
5ꢈꢄꢄ  
                                                                                                 
                                                                                                  
'HW  
                         
                         
                          
                          
DLO  
                           
                           
                           
ꢄRI  
                            
                             
ꢄF  
                              
                               
RQWDFWVꢄꢄ  
                               
                                
                                
                                 
                                 
                                  
                                  
                                   
                                   
                                   
                                    
“
                                                          
ꢀꢍ  
                                                          
                                                           
ꢀꢆꢄꢄ  
                                                            
                                                            
                                                             
ꢀꢍꢋꢄꢄ  
                                           
                                           
ꢀꢍꢁꢄ$ꢄꢄ%ꢄꢄ&ꢄꢄ  
                                                    
                                                    
                                                     
*/  
                                                                                                                                                
                                                                                                                                                
                                                                                                                                                 
'ꢀꢁꢁ  
                                                                                                                                                 
                                                                                                                                                  
                                                                                                                                                   
                                                                                                                                                   
                                                                                                                                                   
                                                                                                                                                    
                                                                                                                                                    
                                                                                                                                                     
ꢇꢁꢄꢄ  
                                                                                                                                                     
                                                                                                                                                      
                                                                                                                                                      
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
5
Package Outlines  
In this chapter the Package Outline L-DIM-240-55 is included.  
FIGURE 2  
Package Outline L-DIM-240-55  
ꢁꢅ  
                                                             
                                                             
ꢅ
                                                              
                                                              
ꢍ
ꢍ
                                                               
ꢅ
                                                                
ꢆ
                                                                
                                                                 
ꢄꢄ  
ꢄꢄ  
ꢁꢈꢋ  
ꢇꢆ  
ꢉꢄꢄ  
&ꢄꢄ  
ꢁꢍ  
ꢆꢄꢄ  
$ꢄꢄ  
%ꢄꢄ  
ꢁꢄꢄ  
Notes  
1. Drawing according to ISO 8015  
2. Dimensions in mm  
3. General tolerances +/- 0.15  
4. Heat sink is not included in the drawing. Additional width might be required.  
Rev. 1.0, 2006-12  
28  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
6
Product Type Nomenclature  
Qimonda’s nomenclature uses simple coding combined with  
some propriatory coding. Table 18 provides examples for  
module and component product type number as well as the  
field number. The detailed field description together with  
possible values and coding explanation is listed for modules  
in Table 19 and for components in Table 20.  
TABLE 18  
Nomenclature Fields and Examples  
Example for  
Field Number  
1
2
3
4
5
6
7
8
9
10  
11  
Micro-DIMM  
DDR2 DRAM  
HYS  
HYB  
64  
18  
T
T
64/128  
0
2
0
0
K
A
M
C
–5  
–5  
–A  
512/1G 16  
TABLE 19  
DDR2 DIMM Nomenclature  
Field  
Description  
Values  
Coding  
1
2
Qimonda Module Prefix  
Module Data Width [bit]  
HYS  
64  
Constant  
Non-ECC  
ECC  
72  
3
4
DRAM Technology  
T
DDR2  
Memory Density per I/O [Mbit];  
Module Density1)  
32  
256 MByte  
512 MByte  
1 GByte  
2 GByte  
4 GByte  
64  
128  
256  
512  
0 .. 9  
0, 2, 4  
0 .. 9  
A .. Z  
D
5
6
7
8
9
Raw Card Generation  
Number of Module Ranks  
Product Variations  
Look up table  
1, 2, 4  
Look up table  
Look up table  
SO-DIMM  
Package, Lead-Free Status  
Module Type  
M
Micro-DIMM  
Registered  
Unbuffered  
Fully Buffered  
R
U
F
Rev. 1.0, 2006-12  
29  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Field  
Description  
Values  
Coding  
10  
Speed Grade  
–2.5F  
–2.5  
–3  
PC2–6400 5–5–5  
PC2–6400 6–6–6  
PC2–5300 4–4–4  
PC2–5300 5–5–5  
PC2–4200 4–4–4  
PC2–3200 3–3–3  
First  
–3S  
–3.7  
–5  
11  
Die Revision  
–A  
–B  
Second  
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall  
module memory density in MBytes as listed in column “Coding”.  
TABLE 20  
DDR2 DRAM Nomenclature  
Field  
Description  
Values  
Coding  
1
2
3
4
Qimonda Component Prefix  
Interface Voltage [V]  
HYB  
18  
Constant  
SSTL_18  
DRAM Technology  
T
DDR2  
Component Density [Mbit]  
256  
512  
1G  
2G  
40  
256 Mbit  
512 Mbit  
1 Gbit  
2 Gbit  
5+6  
Number of I/Os  
×4  
80  
×8  
16  
×16  
7
8
Product Variations  
Die Revision  
0 .. 9  
A
Look up table  
First  
B
Second  
9
Package, Lead-Free Status  
Speed Grade  
C
FBGA, lead-containing  
FBGA, lead-free  
DDR2-800 5-5-5  
DDR2-800 6-6-6  
DDR2-667 4-4-4  
DDR2-667 5-5-5  
DDR2-533 4-4-4  
DDR2-400 3-3-3  
F
10  
–25F  
–2.5  
–3  
–3S  
–3.7  
–5  
Rev. 1.0, 2006-12  
30  
11032006-VX0M-M6IH  
Internet Data Sheet  
HYS72T512341H[H/J/K]P-[3.7/5]-B  
Registered DDR2 SDRAM Modules  
Table of Contents  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
2.1  
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
3.1  
3.2  
3.3  
3.4  
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Rev. 1.0, 2006-12  
31  
11032006-VX0M-M6IH  
Internet Data Sheet  
Edition 2006-12  
Published by Qimonda AG  
Gustav-Heinemann-Ring 212  
D-81739 München, Germany  
© Qimonda AG 2006.  
All Rights Reserved.  
Legal Disclaimer  
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics  
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any  
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation warranties of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in question please  
contact your nearest Qimonda Office.  
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a  
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human  
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health  
of the user or other persons may be endangered.  
www.qimonda.com  
厂商 型号 描述 页数 下载

INFINEON

 		HYS64-72V2200GU-8 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块[ 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module ] 17 页

INFINEON

 		HYS64-74V8200GU 3.3 V 8M ×64 /72- 1位银行SDRAM模块3.3 V 16M ×64 /72- 2位银行SDRAM模块[ 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module ] 17 页

INFINEON

 		HYS6472V16200GU 3.3 V 16M ×64 /72-位SDRAM模块3.3 V 32M ×64 /72-位SDRAM模块3.3 V 64M ×64 /72-位SDRAM模块[ 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules ] 17 页

INFINEON

 		HYS6472V4200GU 3.3V 4M ×64 /72- 1位BANK SDRAM模块3.3V 8M ×64 /72- 2位BANK SDRAM模块[ 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module ] 15 页

INFINEON

 		HYS64D128020GBDL-6-A [ DDR DRAM Module, 128MX64, 0.7ns, CMOS, SO-DIMM-200 ] 11 页

ETC

 		HYS64D128020GBDL-7-A ？ 1GB （ 1024Mx64 ） PC2100 2银行？\n[ ?1GB (1024Mx64) PC2100 2-bank? ] 11 页

INFINEON

 		HYS64D128020GU-7-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

INFINEON

 		HYS64D128020GU-8-A 2.5 V 184针无缓冲DDR- SDRAM我模块[ 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules ] 18 页

QIMONDA

 		HYS64D128020GU-8-A [ DDR DRAM Module, 128MX64, 0.8ns, CMOS, PDMA184 ] 18 页

INFINEON

 		HYS64D128021 200针的小型双列直插式内存模块[ 200-Pin Small Outline Dual-In-Line Memory Modules ] 23 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.224170s