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WV3EG64M64ETSU335D3MG

型号：

WV3EG64M64ETSU335D3MG

描述：

512MB - 64Mx64 DDR SDRAM UNBUFFERED[ 512MB - 64Mx64 DDR SDRAM UNBUFFERED ]

品牌：

WEDC[ WHITE ELECTRONIC DESIGNS CORPORATION ]

页数：

10 页

PDF大小：

236 K

下载PDF手册
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY*  
512MB – 64Mx64 DDR SDRAM UNBUFFERED  
FEATURES  
DESCRIPTION  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Double-data-rate architecture  
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate  
SDRAM memory module based on 512Mb DDR SDRAM  
components. The module consists of eight 64Mx8 DDR  
SDRAMs in 66 pin TSOP packages mounted on a 184  
pin substrate.  
PC2700 @ CL 2.5  
Bi-directional data strobes (DQS)  
Differential clock inputs (CK & CK#)  
Programmable Read Latency 2,2.5 (clock)  
Programmable Burst Length (2,4,8)  
Programmable Burst type (sequential & interleave)  
Edge aligned data output, center aligned data input.  
Auto and self refresh, (8K/64ms refresh)  
Serial presence detect with EEPROM  
Power supply:  
Synchronous design allows precise cycle control with the  
use of system clock. Data I/O transactions are possible on  
both edges and Burst Lengths allow the same device to be  
useful for a variety of high bandwidth, high performance  
memory system applications.  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
• VCC = VCCQ = +2.5V 0.2V  
ꢀ
184 pin DIMM package  
• D3 PCB height: 28.58mm (1.125")  
NOTE: Consult factory for availability of:  
• RoHS compliant products  
• Vendor source control options  
• Industrial temperature option  
OPERATING FREQUENCIES  
DDR333 @CL=2.5  
166MHz  
Clock Speed  
CL-tRCD-tRP  
2.5-3-3  
August 2005  
Rev. 1  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
PIN CONFIGURATION  
PIN NAMES  
A0-A12  
Address input (Multiplexed)  
Bank Select Address  
Data Input/Output  
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL  
BA0-BA1  
1
VREF  
DQ0  
VSS  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
NC  
A0  
93  
94  
VSS  
DQ4  
DQ5  
VCCQ  
DM0  
DQ6  
DQ7  
VSS  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
VSS  
NC  
DQ0-DQ63  
DQS0-DQS7  
CK0, CK1, CK2  
2
Data Strobe Input/Output  
3
NC  
95  
A10  
Clock Input  
4
DQ1  
DQS0  
DQ2  
VCC  
DQ3  
NC  
VSS  
96  
NC  
CK0#, CK1#, CK2# Clock Input  
5
NC  
BA1  
97  
VCCQ  
NC  
VSS  
DQ36  
DQ37  
VCC  
DM4  
DQ38  
DQ39  
VSS  
DQ44  
RAS#  
DQ45  
VCCQ  
CS0#  
NC  
DM5  
VSS  
DQ46  
DQ47  
NC  
CKE0  
CS0#  
RAS#  
CAS#  
WE#  
Clock Enable input  
6
98  
Chip Select Input  
Row Address Strobe  
Column Address Strobe  
Write Enable  
7
DQ32  
VCCQ  
DQ33  
DQS4  
DQ34  
VSS  
99  
8
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
9
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
NC  
VSS  
NC  
DM0-DM7  
VCC  
Data-in-mask  
Power Supply  
Power Supply for DQS  
Ground  
NC  
DQ8  
DQ9  
DQS1  
VCCQ  
CK1  
CK1#  
VSS  
DQ10  
DQ11  
CKE0  
VCCQ  
DQ16  
DQ17  
DQS2  
VSS  
A9  
DQ18  
A7  
VCCQ  
DQ19  
A5  
DQ24  
VSS  
VCCQ  
DQ12  
DQ13  
DM1  
VCC  
VCCQ  
BA0  
VSS  
DQ35  
DQ40  
VCCQ  
WE#  
DQ41  
CAS#  
VSS  
VREF  
Power Supply for Reference  
Serial EEPROM Power Supply  
Serial data I/O  
VCCSPD  
SDA  
DQ14  
DQ15  
NC  
VCCQ  
NC  
DQ20  
A12  
VSS  
DQ21  
A11  
DM2  
VCC  
DQ22  
A8  
DQ23  
VSS  
A6  
DQ28  
DQ29  
VCCQ  
DM3  
A3  
DQ30  
VSS  
DQ31  
NC  
NC  
VCCQ  
CK0  
CK0#  
SCL  
Serial clock  
SA0-SA2  
VCCID  
NC  
Address in EEPROM  
VCC Indentification Flag  
No Connect  
DQS5  
DQ42  
DQ43  
VCC  
NC  
DQ48  
DQ49  
VSS  
VCCQ  
DQ52  
DQ53  
NC  
CK2#  
CK2  
VCCQ  
DQS6  
DQ50  
DQ51  
VSS  
VCCID  
DQ56  
DQ57  
VCC  
DQS7  
DQ58  
DQ59  
VSS  
NC  
SDA  
SCL  
VCC  
DM6  
DQ54  
DQ55  
VCCQ  
NC  
DQ25  
DQS3  
A4  
DQ60  
DQ61  
VSS  
VCC  
DQ26  
DQ27  
A2  
DM7  
DQ62  
DQ63  
VCCQ  
SA0  
VSS  
A1  
NC  
SA1  
NC  
SA2  
VCC  
VCCSPD  
August 2005  
Rev. 1  
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
FUNCTIONAL BLOCK DIAGRAM  
CS0#  
DQS0  
DM0  
DQS4  
DM4  
DM  
CS#  
DQS  
DM  
CS#  
DQS  
DQ0  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ32  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQS1  
DM1  
DQS5  
DM5  
DM  
CS#  
DQS  
DM  
CS#  
DQS  
DQ8  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQS2  
DM2  
DQS6  
DM6  
DM  
CS#  
DQS  
DM  
CS#  
DQS  
DQ16  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ48  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQS3  
DM3  
DQS7  
DM7  
DM  
CS#  
DQS  
DM  
CS#  
DQS  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ7  
DQ6  
DQ1  
DQ0  
DQ5  
DQ4  
DQ3  
DQ2  
SERIAL PD  
*Clock Net Wiring  
SCL  
WP  
Clock Wiring  
SDA  
DRAM 1  
A0 A1  
A2  
Clock  
Input  
DDR SDRAMs  
SA0 SA1 SA2  
1.5PF  
CK0, CK0#  
CK1, CK1#  
CK2, CK2#  
2 DDR SDRAMs  
3 DDR SDRAMs  
3 DDR SDRAMs  
R = 120 Ohm  
DRAM 3  
Card  
Edge  
1.5PF  
BA0-BA1  
A0-A12  
RAS#  
BA0-BA1: DDR SDRAMs  
A0-A12: DDR SDRAMs  
RAS#: DDR SDRAMs  
CAS#: DDR SDRAMs  
CKE: DDR SDRAMs  
WE#: DDR SDRAMs  
DRAM 5  
VCCSPD  
SPD  
1.5PF  
VCC/VCCQ  
VREF  
DDR SDRAMs  
DDR SDRAMs  
DDR SDRAMs  
CAS#  
CKE0  
WE#  
VSS  
Notes:  
1. DQ-to-I/O wiring is shown as recommended but may be changed.  
2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.  
NOTE: All datalines are terminated through a 22 ohm series resistor.  
August 2005  
Rev. 1  
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Voltage on any pin relative to VSS  
Symbol  
VIN, VOUT  
Value  
-0.5 to 3.6  
Units  
V
Voltage on VCC supply relative to VSS  
Voltage on VCCQ supply relative to VSS  
Storage Temperature  
Operating Temperature  
Power Dissipation  
VCC  
VCCQ  
TSTG  
TA  
-1.0 to 3.6  
-1.0 to 3.6  
-55 to +150  
0 to +70  
8
V
V
°C  
°C  
W
PD  
Short Circuit Current  
IOS  
50  
mA  
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability  
DC CHARACTERISTICS  
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V 0.2V  
Parameter  
Symbol  
VCC  
Min  
2.3  
Max  
2.7  
Unit  
Note  
Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)  
I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)  
I/O Reference voltage  
VCCQ  
2.3  
2.7  
V
V
VREF  
VTT  
VIH(DC)  
VIL(DC)  
VIN(DC)  
VID(DC)  
VIX(DC)  
0.49*VCCQ  
VREF-0.04  
VREF+0.15  
-0.3  
0.51*VCCQ  
VREF+0.04  
VCCQ+0.30  
VREF-0.15  
VCCQ+0.30  
VCCQ+0.60  
VCCQ+0.60  
16  
1
2
I/O Termination voltage  
V
Input logic high voltage  
V
Input logic low voltage  
V
Input voltage level, CK and CK#  
Input differential voltage, CK and CK#  
Input crossing point voltage, CK and CK#  
-0.3  
V
0.36  
V
3
0.3  
V
Addr, CAS#,  
RAS#, WE#  
CS#, CKE  
CK, CK#  
DM  
-16  
uA  
-16  
-6  
-2  
-5  
16  
6
2
5
—
—
—
—
uA  
uA  
uA  
uA  
mA  
mA  
mA  
mA  
Input leakage current  
II  
Output leakage current  
IOZ  
IOH  
IOL  
IOH  
IOL  
Output high current (normal strengh); VOUT = V +0.84V  
Output high current (normal strengh); VOUT = VTT -0.84V  
Output high current (half strengh); VOUT = VTT +0.45V  
Output high current (half strengh); VOUT = VTT -0.45V  
-16.8  
16.8  
-9  
9
NOTES:  
1.  
V
REF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2ꢀ of the DC  
value  
2.  
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF  
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.  
CAPACITANCE  
TA = 25°C, f = 1MHz, VCC = VCCQ = 2.5V  
Parameter  
Symbol  
CIN1  
CIN2  
CIN3  
CIN4  
Min  
20  
20  
20  
10  
8
Max  
28  
28  
28  
13  
9
Unit  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)  
Input Capacitance (CKE0)  
Input Capacitance (CS0#)  
Input Capacitance (CK0 to CK2, CK0# to CK2#)  
Input Capacitance (DM0-DM7)  
Data and DQS input/output capacitance (DQ0-DQ63)  
CIN5  
COUT1  
8
9
August 2005  
Rev. 1  
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
IDD SPECIFICATIONS AND TEST CONDITIONS  
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V 0.2V  
Includes DDR SDRAM component only  
Parameter  
Symbol  
Conditions  
DDR333 @  
CL = 2.5  
Unit  
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN)  
;
Operating current  
Operating current  
IDD0*  
DQ, DM and DQS inputs change once per clock cycle; Address and control  
inputs change once every two clock cycles  
1000  
mA  
One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN)  
IOUT = 0mA; Address and control inputs change once per clock cycle  
;
IDD1*  
1200  
40  
mA  
mA  
Percharge power-  
down standby current  
IDD2P**  
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW  
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address  
and other control inputs changing once per clock cycle. VIN = VREF for DQ,  
DQS and DM  
Idle standby current  
IDD2F**  
IDD3P**  
IDD3N**  
IDD4R*  
IDD4W*  
240  
240  
mA  
mA  
mA  
mA  
mA  
Active power-down  
standby current  
One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW  
CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX)  
;
Active standby  
current  
tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address  
and other control inputs changing once per clock cycle  
400  
Burst = 2; Reads; Continuous burst; One device bank active; Address and  
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA  
Operating current  
Operating current  
1440  
1480  
Burst = 2; Writes; Continuous burst; One device bank active; Address and  
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and  
DQS inputs change twice per clock cycle  
Auto refresh current  
Self refresh current  
IDD5**  
IDD6**  
tRC = tRFC(MIN)  
CKE < 0.2V  
2000  
40  
mA  
mA  
Four device bank interleaving Reads Burst = 4 with auto precharge;  
tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during  
Active READ, or WRITE commands  
Orerating current  
IDD7*  
3120  
mA  
Note: These specifications apply to modules built with Samsung components only.  
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.  
** Value calculated as all module ranks in this operation condition.  
August 2005  
Rev. 1  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND  
RECOMMENDED AC OPERATING CONDITIONS  
335  
Parameter  
Symbol  
Unit  
Min  
60  
72  
42  
18  
18  
12  
15  
1
Max  
Row cycle time  
Refresh row cycle time  
Row active time  
RAS to CAS delay  
Row precharge time  
Row active to Row active delay  
Write recovery time  
Last data into Read command  
Clock cycle time  
Clock high level width  
tRC  
tRFC  
tRAS  
tRCD  
tRP  
tRRD  
tWR  
tWTR  
tCK  
tCH  
tCL  
tDQSCK  
tAC  
tDQSQ  
tRPRE  
tRPST  
tDQSS  
tWPRES  
tWPRE  
tDSS  
tDSH  
tDQSH  
tDQSL  
tIS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
ns  
tCK  
tCK  
ns  
ns  
ns  
tCK  
tCK  
tCK  
ns  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
ns  
ns  
ns  
ns  
ns  
70K  
CL = 2.5  
6
12  
0.45  
0.45  
-0.6  
-0.7  
—
0.9  
0.4  
0.75  
0
0.25  
0.2  
0.2  
0.35  
0.35  
0.75  
0.75  
0.8  
0.8  
-0.7  
-0.7  
0.67  
0.55  
0.55  
+0.6  
+0.7  
0.45  
1.1  
Clock low level width  
DQS-out access time from CK/CK  
Output data access time from CK/CK  
Data strobe edge to ouput data edge  
Read Preamble  
Read Postamble  
CK to valid DQS-in  
DQS-in setup time  
DQS-in hold time  
DQS falling edge to CK rising-setup time  
DQS falling edge from CK rising-hold time  
DQS-in high level width  
0.6  
1.25  
DQS-in low level width  
Address and Control Input setup time (fast)  
Address and Control Input hold time (fast)  
Address and Control Input setup time (slow)  
Address and Control Input hold time (slow)  
Data-out high impedence time from CK/CK  
Data-out low impedence time from CK/CK  
Output Slew Rate Matching Ratio (rise to fall)  
Note: These specifications apply to modules built with Samsung components only.  
tIH  
tIS  
F
tIH  
F
tHZ  
+0.7  
+0.7  
1.5  
S
tLZ  
S
tSLMR  
August 2005  
Rev. 1  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND  
RECOMMENDED AC OPERATING CONDITIONS (continued)  
335  
Parameter  
Symbol  
Unit  
Min  
12  
0.45  
0.45  
2.2  
1.75  
75  
200  
Max  
Mode register set cycle time  
DQ & DM setup time to DQS  
DQ & DM hold time to DQS  
Control & Address input pulse width  
DQ & DM input pulse width  
Exit self refresh to non-Read command  
Exit self refresh to read command  
Refresh interval time  
Output DQS valid window  
Clock half period  
Data hold skew factor  
DQS write postamble time  
tMRD  
tDS  
tDH  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
us  
ns  
ns  
ns  
ns  
tIPW  
tDIPW  
tXSNR  
tXSRD  
tREFI  
tQH  
7.8  
—
—
0.55  
0.6  
tHP-tQHS  
tCLmin or tCHmin  
tHP  
tQHS  
tWPST  
tRAP  
tDAL  
0.4  
18  
(tWR/tCK) +  
(tRP/tCK  
Active to Read with Auto precharge command  
Autoprecharge write recovery + Precharge time  
tCK  
)
AC OPERATING TEST CONDITIONS  
VCC = 2.5V, VCCQ = 2.5V, 0°C ≤ TA ≤ 70°C  
Parameter/Condition  
Input High (Logic 1) Voltage  
Input Low (Logic 0) Voltage  
Input Differential Voltage, CK and CK# inputs  
Input Crossing Point Voltage, CK and CK# inputs  
Symbol  
VIH(AC)  
VIL(AC)  
VID(AC)  
VIX(AC)  
Min  
VREF +0.31  
Max  
Unit  
V
V
V
V
Note  
1
1
VREF -0.31  
VCCQ+0.6  
0.5*VCCQ+0.2  
0.7  
0.5*VCCQ-0.2  
NOTES:  
1.  
V
IH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.  
IL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.  
V
August 2005  
Rev. 1  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
ORDERING INFORMATION FOR D3  
Part Number  
WV3EG64M64ETSU335D3xG  
Speed  
166MHz/333Mb/s  
CAS Latency tRCD  
2.5  
tRP  
3
Height*  
28.58 (1.125")  
Temperature  
0°C to 70°C  
3
NOTES:  
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)  
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be  
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)  
• Consult factory for availability of industrial temperature (-40°C to 85°C) option  
PACKAGE DIMENSIONS FOR D3  
133.35 0.15  
(5.25 0.006)  
3.30  
128.95  
(0.130)  
(5.077")  
MAX  
4.00  
(0.158 (2x))  
28.58 0.15  
(1.125 0.006)  
17.80  
(0.70)  
2.30  
(0.10)  
(2x)  
1.27 (0.050)  
10.00  
2.175  
(0.393)  
(0.085)  
49.53  
(1.95)  
1.27 0.10  
64.77  
3.00  
(0.118)  
(4x)  
(0.050 0.004)  
(2.550)  
1.80  
(0.071)  
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)  
August 2005  
Rev. 1  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
PART NUMBERING GUIDE  
WV 3 E G 64M 64 E T S U xxx D3 x G  
WEDC  
MEMORY  
DDR  
GOLD  
DEPTH  
BUS WIDTH  
x8  
TSOP  
2.5V  
UNBUFFERED  
SPEED (MHz)  
PACKAGE 184 PIN  
COMPONENT VENDOR  
NAME  
(M = Micron)  
(S = Samsung)  
G = ROHS COMPLIANT  
August 2005  
Rev. 1  
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WV3EG64M64ETSU-D3  
White Electronic Designs  
PRELIMINARY  
Document Title  
512MB – 64Mx64 DDR SDRAM UNBUFFERED  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Created  
7-05  
Advanced  
Rev 1  
1.1 Update to DC, IDD and AC specifications  
1.2 Changed from Advanced to Preliminary  
8-05  
Preliminary  
August 2005  
Rev. 1  
10  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
厂商 型号 描述 页数 下载

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