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QT300-D

型号：

QT300-D

描述：

电容数字转换器[ CAPACITANCE TO DIGITAL CONVERTER ]

品牌：

QUANTUM[ QUANTUM RESEARCH GROUP ]

页数：

14 页

PDF大小：

381 K

下载PDF手册
LQ  
QT300  
CAPACITANCE TO  
DIGITAL  
CONVERTER  
ꢀ Capacitance to Digital Converter (CDC) IC  
ꢀ Direct-to-digital conversion, 16 bits  
ꢀ Log response: Wide dynamic range  
ꢀ Outputs raw data to a host device  
ꢀ Single wire UART interface  
DRDY  
SCK  
1
2
3
4
8
7
6
5
Vdd  
SDO  
ꢀ Master or Slave mode SPI interface  
ꢀ Programmable clock speed  
REQ / 1W  
SNS2  
SNS1  
Vss  
ꢀ Turns objects into intrinsic touch sensors  
ꢀ One external sample capacitor to control gain  
ꢀ Multiple QT300’s possible on one SPI bus  
APPLICATIONS  
The QT300 charge-transfer (“QT’”) IC is a self-contained Capacitance-to-  
Digital-Converter (CDC) capable of detecting femotofarad level changes in  
capacitance. While designed primarily for instrumentation applications, it can be used  
also for touch control applications where signal processing is best handled by a host  
MCU.  
ꢀ Fluid level sensors  
ꢀ Prox sensors  
ꢀ Moisture detection  
ꢀ Position sensing  
ꢀ Transducer driver  
ꢀ Material sensors  
Primary applications include fluid level sensors, distance sensors, transducer  
‘amplifiers’ for pressure and humidity sensing functions, material detectors, and other  
uses requiring quantified capacitance data.  
Unlike other Quantum products, the QT300 does not process its acquired data. Its only result is raw, unprocessed binary  
data which can be transmitted to a host via either a bidirectional SPI interface or a simple polled single wire UART type  
interface. This allows the designer to treat the device as a capacitance-to-digital-converter (CDC) for measurement  
applications. It is ideal for situations where there are unique signal processing requirements.  
The device requires only a single sampling capacitor to function. The value of this capacitor controls the gain of the sensor,  
and it can be adjusted over 2½ decades of range from 1nF to 500nF. No external switches, opamps, or other components  
are required.  
The device operates on demand, and can be synchronized to allow several QT300’s to operate near each other without  
cross-interference.  
AVAILABLE OPTIONS  
TA  
00C to +700C  
-400C to +850C  
SOIC  
-
QT300-IS  
8-PIN DIP  
QT300-D  
-
LQ  
Copyright © 2002 QRG Ltd  
QT300 R1.02/0204  
Table 1-1 SPI Mode Pin Description  
Vdd  
100nF  
Pin  
Name  
/DRDY  
SCK  
Function  
HOST  
MICRO  
QT300  
1
8
1
2
3
4
5
6
7
8
Data Ready  
Serial data clock  
Sense 1 line  
Vdd  
DRDY  
DRDY  
SNS1  
VSS  
3
5
SNS1  
Negative supply (ground)  
Sense 2 line  
Request input  
2
6
SCK  
REQ  
SCK  
SNS2  
/REQ  
SDO  
Rs  
REQ  
Cs  
SNS2  
Serial data out  
7
SDI  
SDO  
ELECTRODE  
Cx  
VDD  
Positive supply  
Vss  
4
Table 1-2 1W UART Mode Pin Description  
Pin  
Name  
-
Function  
Figure 1-1 Basic QT300 Circuit in SPI mode.  
1
2
3
4
5
6
7
8
Connect to Vdd or Vss  
Connect to Vdd or Vss  
Sense 1 line  
-
Vdd  
SNS1  
VSS  
SNS2  
1W  
-
100nF  
HOST  
Negative supply (ground)  
Sense 2 line  
MICRO  
QT300  
1
8
Vdd  
1W UART Line  
Connect to Vdd or Vss  
Positive supply  
DRDY  
3
5
SNS1  
2
6
VDD  
SCK  
Rs  
1W UART  
1W  
Cs  
SNS2  
7
SDO  
ELECTRODE  
Cx  
Table 1-3 Alternate Cloning Pin Functions  
Vss  
Pin  
Name  
Function  
4
2
6
7
SCK  
SDI  
Serial clone data clock  
Serial clone data in  
Serial clone data out  
Figure 1-2 Basic QT300 Circuit in UART mode.  
SDO  
The type of serial port and its mode can be selected via the  
cloning process using a QTM300CA programming adapter.  
The QT300 operates only on request from a host device.  
After initiation via a trigger signal, the QT300 generates an  
acquisition burst and sends the resulting raw signal data  
back via one of the serial modes.  
1 - OVERVIEW  
The QT300 is a digital burst mode charge-transfer (QT)  
capacitance-to-digital converter (CDC) designed for  
applications requiring raw signal information such as fluid  
level sensing and distance gauging; it outputs raw digital  
signal data over a serial interface. The output data is in a  
16-bit format; signal levels depend on load (Cx) and the  
sampling capacitor value (Cs).  
1.2 Burst Length  
The burst length (and hence the signal level and sensitivity)  
is described by the following formula:  
k$CS  
Sensitivity is a function of electrode size, shape, orientation,  
the composition and aspect of the object being sensed, the  
thickness and composition of any dielectric overlaying the  
electrode, and the degree of mutual coupling between the  
electrode and the object being sensed, in addition to the  
electrical parameters Cs and Cx as described in Section 1.2  
below.  
BL =  
CX  
where Cs is the reference capacitor, Cx is the unknown load  
capacitance (including internal pin and wiring capacitance)  
and ‘k’ is a constant, typically 0.51, which varies very slightly  
from device to device.  
The device has an internal Cx, Csns, which adds to the Cx in  
the formula. This capacitance is about 11pF.  
1.1 Basic Operation  
The QT300 does no internal signal processing; data is simply  
returned via one of two serial port types.  
Each doubling of Cs increases the signal level and  
differential sensitivity by a factor of two. Likewise, doubling  
Cx reduces the signal level and differential sensitivity by a  
factor of two (Figures 7-4, 7-5, 7-7, 7-7, page 11).  
There are two basic types of serial interface: 4-wire SPI and  
a simple single wire (‘1W’) UART. The SPI interface allows  
multiple devices to be connected on one SPI bus, while  
the1W UART requires that the controller have one dedicated  
pin for each QT300. There are two types of SPI mode,  
master and slave.  
The response can be linearized over a particular Cx range to  
a great extent by making the delta-Cx of interest a small part  
of the background level of Cx. If the delta Cx is 10pF on top  
of 20pF, the response will be linear to 10% of full scale. But if  
the desired delta-Cx range is 10pF on top of 100pF, the  
LQ  
2
QT300 R1.02/0204  
Signal Level  
% Error  
or 1W pin. The QT300 only acquires when requested. While  
waiting for a new request the part stays in a low power mode.  
Figure 1-3 Linearity vs Cx, Over Cx= 100pF...110pF  
3%  
2%  
2%  
1%  
1%  
0%  
300  
250  
200  
150  
100  
50  
3 - SPI Port  
3.1 SPI Specifications  
The QT300 can operate in master or slave mode, and thus is  
compatible with virtually all SPI-capable microcontrollers. The  
SPI interface has the following specifications:  
Max clock rate, Fckm 40KHz (master mode)  
Max clock rate, Fcks 40KHz (slave mode)  
Data length  
Inter-byte delay  
0
2 bytes (16 bits total)  
≥8µs (master mode)*  
≥12µs (slave mode)  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
Cx, pF  
Clock idle logic level  
Clock edge  
Data sequence  
Low or High*  
Data out on rising or falling edge*  
High byte first, MSB first  
linearity decreases to under 3% (Figure 1-3). The largest  
error occurs near the middle of the desired Cx span.  
*Determined by Setups  
The linearity error can be corrected using polynomials or a  
piece-wise linear correction method in a microcontroller.  
The host can clock the SPI at any rate up to and including  
the maximum. The maximum clock rate of the part in Master  
mode is determined in Setups via cloning.  
2 - Timing  
Figure 2-1 shows the basic QT300 acquisition timing  
parameters. The basic timing parameters are:  
3.2 Protocol Overview  
The QT300 only transmits data on request, after an  
acquisition burst. The host requests an acquire by setting the  
/REQ line low for at least 30µs; the device then acquires.  
When finished, the DRDY line is pulled low by the QT300 to  
indicate it is ready to send data. (Figure 2-1). The transfer is  
done as two bytes, with the highest byte transferred first.  
Tbd  
Tacq Acquire response time (2.2)  
Tbs Burst Spacing (2.3)  
Burst duration  
(2.1)  
2.1 Tbd - Burst duration  
The burst duration depends on the values of Cs and Cx and  
to a lesser extent, Vdd. The burst is composed of  
charge-transfer cycles operating at about 240kHz.  
In master mode, /DRDY goes high between bytes for the  
period determined by Setup parameter MLS; this is a multiple  
of 6µs.  
The length of this burst is an important parameter as it is  
directly related to the signal value. The burst duration also  
affects the response time of the sensor; the  
larger Cs is, the longer the burst, the slower the  
possible acquisition rate.  
2.2 Tacq - Acquire Response Time  
The time from the /REQ or 1W line going low  
until the completion of data transmission is  
Tacq. Tacq depends on the acquisition burst  
length as well as the serial transmission time.  
SPI Mode: In SPI mode Tacq depends in part on  
the serial clock speed and the space between  
the returned high and low bytes. In SPI slave  
mode the clock speed and the inter-byte spacing  
time Tbdly is determine by the host. In SPI  
Master mode these timings are set by Setup  
parameters SCD and MLS.  
1W mode: Tacq depends in part on the Baud  
rate as well as the inter-byte spacing. The Baud  
rate is auto-set by the trigger pulse width; the  
inter-byte spacing is set by the MLS parameter.  
See Section 4.  
2.3 Tbs - Burst Spacing  
Burst spacing is the time from the start of one  
acquisition burst to the start of the next burst. It  
depends on the host’s trigger rate on the /REQ  
Figure 2-1 Signal Acquisition - Slave SPI Mode  
LQ  
3
QT300 R1.02/0204  
Figure 3-1 Multiple QT300's on the same SPI port  
/REQ should return high before the end of the burst. If  
/REQ is still low at the end of the burst the part will go into  
Setup mode. The minimum duration of /REQ is 30µs.  
Vdd  
Vdd  
100nF  
SDO - Serial Data Output; Output-only. This is the data  
output to the host during an SPI transfer. When not in use,  
this pin floats. This pin should be connected to the SDI  
input pin of the host device.  
HOST MICRO  
DRDY  
QT300  
1
8
Vdd  
DRDY  
3
5
SNS1  
2
6
SCK  
REQ  
SCK  
SCK - SPI clock; Idle high or idle low; input-only SPI clock  
from the host. The idle state is determined in Setups by  
the serial mode (SM) parameter.  
Rs  
REQ  
Cs  
SNS2  
7
SDI  
SDO  
ELECTRODE  
Cx  
Vss  
If SM is set for idle-low SCK: Data is shifted out of the  
QT300 on the rising edge of SCK and should be shifted  
into the host on the falling edge of SCK.  
4
Vdd  
Vdd  
100nF  
QT300  
1
8
Vdd  
If SM is set for idle-high SCK: Data is shifted out of the  
QT300 on the falling edge of SCK and should be shifted  
into the host on the rising edge of SCK.  
DRDY  
3
5
SNS1  
2
6
SCK  
Rs  
Cs  
REQ  
The maximum clock speed is 40kHz, and the timings  
should obey the parameters Tskh and Tskl in Table 7-1.  
SNS2  
7
SDO  
ELECTRODE  
Cx  
/DRDY - Data Ready; active low output only. This indicates to  
the host that the device is ready to send data back to the  
host. During idle times this pin floats and therefore must  
be connected to a pullup resistor. The host must wait until  
/DRDY goes low before starting an SPI transfer.  
Vss  
4
Vdd  
100nF  
QT300  
1
8
Vdd  
DRDY  
Between the high and low byte clockings, the host should  
observe a delay of ≥12µs.  
3
5
SNS1  
2
6
SCK  
Rs  
Cs  
REQ  
A typical SPI slave mode communication sequence is:  
SNS2  
7
SDO  
ELECTRODE  
Cx  
1) Host pulses /REQ low for ≥30µs to initiate an acquire.  
2) QT300 acquires a signal in response to /REQ.  
3) QT300 pulls /DRDY low when ready to send data back.  
4) Host detects /DRDY is low.  
Vss  
4
When not communicating, all SPI lines float to allow multiple  
chips to connect over the same SPI lines. A pullup or  
pulldown resistor is required on SCK depending on the  
selected clock phase, determined by Setups. A pullup  
resistor is required on /DRDY. /REQ may require a pullup if  
the host ever allows this line to float.  
5) Host clocks out the high byte of data from the QT300.  
6) Host waits for ≥12µs.  
7) Host clocks out the low byte of data from the QT300.  
8) QT300 releases /DRDY to float high.  
3.5 SPI Master Mode  
Refer to Figure 7-2 and Table 7-2, page 7.  
3.3 SPI Bus Sharing  
All SPI float transfers making it possible to have several  
QT300 devices (or other unrelated devices) share the SPI  
control signals (Figure 3-1).  
In master SPI mode the QT300 generates the clock signal  
after an acquire initiated from the host via the /REQ line. The  
clock speed and the spacing between the two bytes is set via  
the Setup process (Section 6).  
Each part needs an individual /REQ line, but /DRDY, SCK  
and SDO can be connected together.  
SCD setup parameter determines the master-mode clock  
rate. The default value is 55 (resulting in a 2.55KHz rate).  
The relationship is:  
3.4 SPI Slave Mode  
Refer to Figure 7-1 and Table 7-1, page 7.  
Fscd = 1200/(30+ (SCD x 8)) in Khz  
Where SCD = 0..255  
In SPI Slave mode, /DRDY is used to let the host know when  
data is ready for collection in response to a request so that  
the host can clock over the data.  
MLS setup parameter determines the spacing between the  
two return bytes; this can be important to allow a slow host  
device to recover from receiving the first byte to prevent an  
SPI Slave mode uses 4 signals:  
/REQ - Request Acquisition Input; Active low input-only.  
When /REQ is pulled low, the QT300 wakes and starts an  
acquire. The IC will transmit the resulting data only when  
the acquire has finished.  
LQ  
4
QT300 R1.02/0204  
If SM is set for idle-low SCK: Data is shifted out  
of the QT300 on the rising edge of SCK and should  
be shifted into the host on the falling edge of SCK.  
If SM is set for idle-high SCK: Data is shifted out  
of the QT300 on the falling edge of SCK and  
should be shifted into the host on the rising edge of  
SCK.  
The maximum clock speed is 40kHz, and the  
timings should obey the parameters Tskh and Tskl  
in Table 7-2.  
/DRDY - Data Ready (Optional); active low output  
only. This indicates to the host that the device is  
ready to send data back to the host. During idle  
times this pin floats and therefore must be  
connected to a pullup resistor.  
The DRDY line can be used as a Slave Select line  
(SS). The host does not need this line to operate in  
many cases. DRDY can be used to 'frame' byte  
transmissions.  
Between bytes /DRDY will go high for a period  
determined by the MLS setup parameter; the  
minimum period is 8.3µs.  
A typical Master mode SPI sequence is:  
1) Host pulses /REQ low for ≥30µs.  
2) QT300 acquires a signal in response to /REQ.  
3) QT300 pulls /DRDY low when ready to send data.  
4) Host detects /DRDY low and prepares to receive  
data.  
5) QT300 clocks out first byte of data (MSB).  
6) QT300 sets /DRDY high for a duration determined  
by Setup parameter MLS.  
7) QT300 pulls /DRDY low.  
8) QT300 clocks out the low byte (LSB).  
9) QT300 releases /DRDY to float high.  
Figure 4-1 UART and Trigger Pulse Signal.  
overrun. The default value is 148 (resulting in a 500µs gap).  
The relationship is:  
4 Serial 1W UART Interface  
The single wire ('1W') UART interface allows all  
communications to take place over a single bidirectional line  
with a 10K pullup resistor. The host device triggers the  
QT300 to acquire by means of a pulse sent to the QT300  
over the wire. The Baud rate is established by the width of  
this pulse; the pulse width establishes the bit rate of the  
UART transmission to follow. The QT300 then acquires, and  
responds by sending two bytes of data back over the 1W line  
with a delay between the bytes as determined by parameter  
MLS.  
Tmls (in µs) = (10 + MLS x 4) / 1.2  
Where MLS = 0..255 (from user setup MLS)  
Master SPI mode requires at least 3 signals to operate:  
/REQ - Request Acquisition Input; Active low input-only.  
When /REQ is pulled low, the QT300 wakes and starts an  
acquire. The IC will transmit the resulting data only when  
the acquire has finished.  
/REQ must return high before the end of the burst. If  
/REQ is still low at the end of the burst the part goes into  
Setup mode. The minimum duration of /REQ is 30µs.  
1W operation permits a device to be controlled from a single  
pin on a host controller, using either a hardware or software  
UART. Several QT300’s can coexist on a single host pin,  
provided there is some logic steering.  
SDO - Serial Data Output; Idle low output-only. This is the  
data output to the host during an SPI transfer. When not in  
use, this pin floats. This pin should be connected to the  
SDI input pin of the host device.  
This mode is set via the cloning process using parameter SM  
(see Section 6).  
SCK - SPI clock; Idle high or idle low, output-only. The idle  
state is determined in Setups by the serial mode (SM)  
parameter.  
LQ  
5
QT300 R1.02/0204  
Vdd; Vdd fluctuations often happen when additional loads  
are switched on or off such as LEDs etc.  
4.1 1W UART Specifications  
The QT300 operates in 1W UART mode with the following  
specifications:  
If the power supply is shared with another electronic system,  
care should be taken to assure that the supply is free of  
spikes, sags, and surges. It is best practice to use a  
regulator just for the QT300 (or one for a set of QT300's).  
Baud rate range  
Data length  
Stop bit  
Parity  
Idle state  
4,800 to 9,600 bits/sec  
2 bytes (16 bits total)  
1 (each byte)  
None  
5.2.2 SUPPLY  
R
EQUIREMENTS  
High  
Vdd can range from 2 to 5 volts nominal. Current drain will  
vary depending on Vdd. During writing of the internal  
EEPROM, Vdd must be at least 2.2 volts.  
The 1W line must have a pullup resistor on it (i.e. 10K), or  
1W communications will not function.  
If desired, the supply can be regulated using a conventional  
regulator, for example CMOS LDO regulators, or standard  
78Lxx-series 3-terminal devices.  
4.2 UART 1W Protocol  
The QT300 acquires and transmits only on request. The  
sequence is:  
For proper operation a 100nF (0.1uF) ceramic bypass  
capacitor must be used between Vdd and Vss; the bypass  
cap should be placed very close to the Vdd and Vss pins.  
1) Host generates pulse on 1W pin; pulse width must  
match Baud rate (bit width) of desired return rate. This  
actually sets the Baud rate, so it can vary from one  
acquire to another. See Section 4.3 and Figure 4-1.  
5.3 PCB LAYOUT  
2) The 1W pulse width is measured by the QT300 to  
determine the Baud rate.  
5.3.1 GROUND  
P
LANES  
The use of ground planes around the device is encouraged  
for noise reasons, but ground or power should not be  
coupled too close to the sense pins in order to reduce Cx  
load. Likewise, the traces leading from the sense pins to the  
electrode should not be placed directly over a ground plane;  
rather, the ground plane should be relieved by at least 3  
times the width of the sense traces directly under it, with  
periodic thin bridges over the gap to provide ground  
continuity.  
3) The host floats 1W high.  
4) The QT300 acquires the signal to completion.  
5) QT300 returns data in the following UART format:  
start bit (low)  
8 bits, high byte  
stop bit (high)  
delay (determined by MLS setup)  
start bit (low)  
8 bits, low byte  
stop bit (high)  
5.3.2 NOISE  
S
YNCHRONIZATION  
External fields can cause interference leading to a noisy and  
unstable signal. The most common external fields usually are  
from AC mains power.  
6) The QT300 floats the 1W line and enters idle mode.  
4.3 Trigger pulse description  
The /REQ line of the QT300 can be used to synchronize the  
acquisition to a repetitive external source of interference  
such as the power line frequency in order to dramatically  
reduce signal noise.  
The part wakes from low power mode when the first negative  
edge is detected on the 1W pin (Figure 4-1, bottom). The  
negative pulse must be at least 30µs wide.  
The host then generates the positive pulse that actually sets  
the Baud rate. The QT300 measure this pulse and uses its  
length to set the Baud bit (shift out) rate. 30µs (or more) of  
logic-low must follow this pulse.  
If line frequency is present near the sensors, this feature  
should be used.  
The host must then float the 1W line to allow the QT300 to  
start the signal acquisition.  
Figure 6-1 Clone interface wiring  
CLONING SIGNAL  
5 Circuit Guidelines  
Vdd  
Vdd  
5.1 Sample capacitors  
100nF  
QT300  
1
8
Cs capacitors can be virtually any plastic film or low to  
medium-K ceramic capacitor. The normal usable Cs range is  
from 1nF ~ 500nF depending on the sensitivity required;  
larger values of Cs require higher stability to ensure low drift.  
Acceptable capacitor types include NP0 or C0G ceramic,  
PPS film, and Y5E and X7R ceramics in that order.  
Vdd  
DRDY  
DRDY  
3
5
SNS1  
2
6
SCK  
REQ  
SCK  
Rs  
REQ  
Cs  
SNS2  
7
5.2 Power Supply  
SDI  
SDO  
ELECTRODE  
Cx  
Vss  
5.2.1 STABILITY  
4
The QT300 makes use of the power supply as a reference  
voltage. The acquired signal will shift slightly with changes in  
LQ  
6
QT300 R1.02/0204  
The connections required for cloning are shown in Figure  
6-1. Further information on the cloning process can be found  
in the QTM300CA instruction guide. The parameters which  
can be altered are shown in Table 7-4.  
6 Parameter Setups Cloning  
A special interface is provided to allow user-defined Setups  
to be loaded into internal eeprom or read back out for  
development and production purposes.  
The internal eeprom has a life expectancy of 100,000  
erase/write cycles and the minimum voltage for a write cycle  
is 2.2 Volts.  
The QTM300CA cloning board in conjunction with QT3View  
software simplifies the Setups cloning process greatly. The  
E3A eval board has been designed with a connector to  
facilitate direct connection with the QTM300CA. The  
QTM300CA in turn connects to any PC with a serial port  
which can run QT3View software (included with the  
QTM300CA and available free on Quantum’s web site).  
A serial interface specification for the device can be obtained  
by contacting Quantum.  
LQ  
7
QT300 R1.02/0204  
7 Electrical specifications  
7.1 ABSOLUTE MAXIMUM SPECIFICATIONS  
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . as designated by suffix  
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65OC to +125OC  
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +6V  
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA  
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite  
Short circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite  
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to (Vdd + 0.5) Volts  
7.2 RECOMMENDED OPERATING CONDITIONS  
V
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2 to 5V  
DD min required to reprogram eeprom Setups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.2V  
V
Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mV  
Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mV  
Cs value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 to 500nF  
Cx value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 100pF  
7.3 AC SPECIFICATIONS  
Vdd = 3.0, Ta = recommended operating range, Cs=100nF unless noted  
Parameter  
Description  
Min  
Typ  
Max  
Units  
Notes  
T
PC  
Charge/transfer duration  
Burst length  
830  
ns  
T
BL  
0.5  
30  
25  
ms  
Cs = 4.7nF to 200nF; Cx = 0  
TRQP  
Request pulse  
Burst constant  
µs  
K
0.51  
7.4 DC specifications  
Vdd = 3.0V, Cs = 10nF, Cx = 5pF, Ta = recommended range, unless otherwise noted  
Parameter  
Description  
Supply voltage  
Min  
2
Typ  
Max  
5.5  
Units  
Notes  
V
DD  
DD  
IL  
IH  
OL  
OH  
V
µA  
V
I
Supply current  
60  
1,500  
0.3 Vdd  
Dependent on duty cycle  
Vdd = 2.5 to 5.0V  
V
Input low voltage  
Input high voltage  
Low output voltage  
High output voltage  
Acquisition resolution  
Resolution per bit  
V
0.6 Vdd  
Vdd-0.6  
1,000  
V
Vdd = 2.5 to 5.0V  
V
0.4  
V
V
V
A
R
16  
7
bits  
fF  
S
Figs 7-4, 7-5  
CSNS  
Internal pin capacitance  
11  
pF  
Combined for both SNS pins  
LQ  
8
QT300 R1.02/0204  
Figure 7-1 SPI Slave Mode  
Tskd  
Tskh  
Tskl  
DRDY  
{from QT300}  
SCK  
{from host}  
D15 D14 D13 D12 D11 D10 D9 D8  
D7 D6 D5 D4 D3 D2 D1 D0  
SDO  
{from QT300}  
Thso  
Tds  
Tmls  
Tsosh  
Figure 7-2 SPI Master Mode  
Tmls  
Tskd  
Tskh  
Tskl  
DRDY  
{from QT300}  
SCK  
{from QT300}  
D15 D14 D13 D12 D11 D10 D9 D8  
D7 D6 D5 D4 D3 D2 D1 D0  
SDO  
{from QT300}  
Thso  
Tds  
Tsosh  
Table 7-1 Slave SPI Timing  
Table 7-2 Master SPI Timing  
Symbol  
TSKD  
Parameter  
min  
25  
max Units Symbol  
Parameter  
min  
25  
max Units  
Clock Duration  
SCK High Duration  
SCK Low Duration  
-
-
-
TSKD  
TSKH  
TSKL  
Clock Duration  
1,725  
862.5  
862.5  
µs  
µs  
µs  
µs  
µs  
µs  
TSKH  
13  
SCK High Duration  
SCK Low Duration  
12.5  
12.5  
TSKL  
12  
SCK High To SDO Ready  
Setup Time  
SCK High To SDO Ready  
Setup Time  
TSOSH  
-
10  
TSOSH  
4
7
µs  
µs  
THSO  
TMLS  
SDO Hold Time  
7
-
THSO  
TMLS  
SDO Hold Time  
12.5  
8.3  
-
-
µs  
µs  
MSB-LSB Spacing  
12  
1,000  
MSB-LSB Spacing  
1,708  
µs  
DRDY Low To SCK High  
Delay  
DRDY Low To SCK High  
Delay  
TDS  
12  
1,000  
TDS  
12.5  
-
-
µs  
LQ  
9
QT300 R1.02/0204  
Figure 7-3 1W UART Mode  
1W UART  
Tmls  
Tacq  
8bits MSB  
8bits LSB  
Twu  
Tbr  
Tsb  
Tstop  
Tstar t  
Table 7-3 1W UART Timing  
Symbol  
Parameter  
Wake level  
min  
30  
max  
5,000  
210  
Notes  
Units  
µs  
Twu  
Tbr  
-
-
-
-
-
Baud set pulse  
Baud end level  
Baud rate range  
104  
30  
µs  
Tsb  
5,000  
9,600  
2
µs  
4,800  
Baud rate match accuracy  
Acquisition time  
%
ms  
Tacq  
-
400  
Depends on Cs and Cx  
-
Tstart  
Start pulse  
Stop pulse  
Tbr  
Tbr  
Tstop  
-
-
Tmls  
MSB  
MSB-LSB spacing  
-
8
850  
µs  
µs  
8 x Tbr  
8 x Tbr  
8 bits data, LSB first  
LSB  
Description  
Mode  
-
µs  
Table 7-4 Setups summary chart  
Symbol  
Valid Values  
Default  
Calculation / Notes  
Unit  
0
1
1W UART  
Master Clock  
Idle Low  
3
Master Clock  
Idle High  
2
3
4
SM  
Slave Clock  
Idle Low  
-
-
Slave Clock  
Idle Low  
Slave Clock  
Idle High  
Clock Speed  
SCD  
MLS  
0 - 255  
0 - 255  
55  
Tscd = (30 + (SCD x 8))/1.2  
Tmls = (10 + (MLS x 4))/1.2  
µs  
µs  
MSB-LSB  
Spacing  
148  
LQ  
10  
QT300 R1.02/0204  
10000  
9000  
8000  
7000  
6000  
5000  
4000  
3000  
2000  
1000  
0
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
22nF  
10nF  
4.7nF  
200nF  
120nF  
80nF  
40nF  
0
10  
20  
30  
40  
50  
0
10  
20  
30  
40  
50  
Cx Load, pF  
Cx Load, pF  
Figure 7-4 Typical Burst Length versus Cx & Cs;  
VDD = 5.0 Volts  
Figure 7-5 Typical Burst Length versus Cx & Cs;  
VDD= 5.0 Volts  
150  
500  
Cs  
125  
100  
75  
50  
25  
0
43nF  
Cs  
400  
9nF  
74nF  
19nF  
124nF  
200nF  
43nF  
300  
74nF  
124nF  
200  
100  
0
200nF  
0
11  
21  
34  
48  
0
11  
21  
Cx Load, pF  
34  
48  
Cx Load, pF  
Figure 7-7 Typical resolution vs Cx & Cs;  
Vdd = 3.0 Volts  
Figure 7-6 Typical resolution vs Cx & Cs;  
Vdd = 3.0 Volts  
LQ  
11  
QT300 R1.02/0204  
5.00%  
4.00%  
3.00%  
2.00%  
1.00%  
0.00%  
-1.00%  
-2.00%  
-3.00%  
-4.00%  
-5.00%  
-10 -5  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85  
Temperature, C  
Figure 7-8 Typical Signal Deviation vs. Temperature  
Vdd = 5.0 Volts, Cx = 10pF, Cs = 5~200nF PPS Film  
6000  
5000  
4000  
3000  
2000  
1000  
0
200nF PPS  
100nF PPS  
4.7nF PPS  
-10  
0
10  
20  
30  
40  
50  
60  
70  
80  
Temperature, °C  
Figure 7-9 Typical Signal Vs. Cs & Temp  
Vdd = 5.0 Volts, Cx = 10pF, PPS film capacitors  
LQ  
12  
QT300 R1.02/0204  
M
A
F
S1  
S
a
A
r
L2  
Pin 1  
x
m
L1  
L
Q
Package type: 8-pin Dual-In-Line  
Millimeters  
Inches  
SYMBOL  
Min  
Max  
7.11  
8.26  
10.16  
-
Notes  
Min  
0.24  
0.3  
Max  
0.28  
0.325  
0.4  
Notes  
a
A
6.1  
7.62  
9.02  
7.62  
0.69  
0.356  
1.14  
0.203  
2.54  
0.38  
2.92  
-
M
m
Q
L
0.355  
0.3  
Typical  
-
Typical  
0.94  
0.559  
1.78  
0.305  
-
0.027  
0.014  
0.045  
0.008  
0.1  
0.037  
0.022  
0.07  
0.012  
-
L1  
L2  
F
BSC  
BSC  
r
-
0.015  
0.115  
-
-
S
3.81  
5.33  
10.9  
0.15  
0.21  
0.43  
S1  
x
M
M
a
H
A
φ
e
h
Pin 1  
E
F
L
Package type: 8-pin Wide SOIC  
Millimeters  
Inches  
SYMBOL  
Min  
5.21  
7.62  
Max  
5.41  
8.38  
Notes  
Min  
0.205  
0.3  
Max  
0.213  
0.33  
Notes  
a
A
M
F
L
5.16  
1.27  
5.38  
0.203  
0.05  
0.212  
BSC  
BSC  
0.305  
0.102  
1.78  
0.508  
0.33  
2.03  
0.012  
0.004  
0.07  
0.02  
0.013  
0.08  
h
H
e
0.178  
0.508  
o
0.254  
0.889  
o
0.007  
0.02  
o
0.01  
0.035  
o
E
φ
0
8
0
8
LQ  
13  
QT300 R1.02/0204  
lQ  
Copyright © 2002 QRG Ltd. All rights reserved.  
Patented and patents pending  
Corporate Headquarters  
1 Mitchell Point  
Ensign Way, Hamble SO31 4RF  
Great Britain  
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939  
admin@qprox.com  
www.qprox.com  
North America  
651 Holiday Drive Bldg. 5 / 300  
Pittsburgh, PA 15220 USA  
Tel: 412-391-7367 Fax: 412-291-1015  
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject  
to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order  
acknowledgement. QProx, QTouch, QMatrix, QLevel, and QSlide are trademarks of QRG. QRG products are not suitable for medical  
(including life-saving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's  
Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection  
with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customers are entirely  
responsible for their products and applications which incorporate QRG's products.  
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