OMNIVISION TECHNOLOGIES, Inc.
SINGLE IC CMOS MONOCHROME CAMERA WITH NTSC ANALOG OUTPUT
OV5116N
1. Introduction
This section describes the features and functions of the OV5116N, a monochrome CMOS video camera integrated circuit.
2. Pin Assignments:
Table 1.
Pin #
Pin Descriptions
Name
Class
Function
1, 2, 20,
23, 26
AVDD, SVDD,
DVDD, OVDD
DEVDD
Bias
Power (+5V) connections.
3
4
5
6
VRCHG
N50
OA
I-Ø
Internal voltage reference. Connect to AGND with a 0.1uF capacitor.
Set low(Ø)=standard NTSC. Set high (1)=50hz light (For use in Japan Only);
Auto brightness level descending function off
ABOFF
VCBRT
I-Ø
OA
Bias
Video DC Output Black level, leave it open in usual case
Ground connections. Connect to supply common.
7, 21,
25, 28
SGND, DGND,
DEGND, AGND
8
NTSC
BKLT
XTAL2
XTAL1
FSI
I-1
I-Ø
XO
XI
Set high(1)=EIA/NTSC mode
*9
10
11
12
Backlight mode 1
Oscillator clock output or crystal output.
External oscillator input or crystal input: 12.288MHz
I-Ø
External frame sync input. A rising edge on FSI sets the chip timing to vertical sync.
Leave open if unused.
13
14
OENB
G4X
I-Ø
I-Ø
A logic level input to enable or tri-state CVO. Logic high(1)=tri-state;low(Ø)=enabled.
A logic level input which when high places the maximum AGC gain to 4x. When low the
sensor AGC gain is 2x.
15
FAST
I-Ø
A logic level input to enable/disable AGC/AEC FAST mode. High enables, low disables,
which provides slow and smooth AGC/AEC mode.
16
17
BPED
I-Ø
I-1
A logic level input to disable on chip edge enhancement. High disable, low enable.
GAMMA
A logic level pin to select the transfer characteristic of output voltage versus light input.
Logic high for g=0.45; low for g=1.
18
19
22
FSO/MIRR
PCLK/G8X
CVO
I/O
In/out pin.Frame Sync Output. Digital frame sync output pin. Positive pulse occurs during
the CVO vertical sync period. Input is a logic level input to enable mirror function.
Low(Ø)=Standard, High(1)=Mirror.
Ø/Ø
I/O
Digital pixel clock output. Provides 2 functions: When high a valid pixel is present at CVO
and in sync with PCLK. Input is a logic level input to enable maximum AGC gain to 8x
(only effective when pin 14 is set to high(1))
Ø/Ø
Q
The composite video output signal. The output is a source follower capable of directly
driving a 1V p-p signal into a 108 Ω load.(75Ω external and 33Ω internal)
*24
27
ATBLKT
VREQ
I-Ø
OA
Backlight mode 2
Internal voltage reference level. Connect to AGND with a 0.1uF capacitor.
* Pin 9 and Pin 24 must be used in a logical combination as per the following table:
ATBLK(Pin 24)
BLKT(Pin 9)
Mode
Normal Mode
Mode 1 - Manual Back light
Mode 2 – Automatic Back light (Chip determination)
Future Use
Ø
Ø
1
Ø
1
Ø
1
1
Class
I-1
Default Level
digital input, with 100k pull up
digital input, with 100k pull down
digital CMOS level input and output
analog CMOS reference voltage
75 ohm output
I-
Ø
I/O
OA
Q
XI/XO
crystal input/output
Bias
power supply bias
: Low; O: Output
Ø
May 4, 2001
Version 2.1
2
