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OV5017

型号：

OV5017

描述：

单芯片1/4的视频图像传感器[ Single chip 1/4 video image sensor ]

品牌：

ETC[ ETC ]

页数：

20 页

PDF大小：

140 K

下载PDF手册
OV5017  
Features  
Overview  
n Single chip 1/4” video image sensor  
n Progressive scan  
The OV5017 is a black and white digital camera  
chip that uses OmniVision’s CMOS image core  
technology. Combining the CMOS sensor technol-  
ogy and an easy to use digital interface, the  
OV5017 offers a low cost solution for high-quality  
video image applications.  
n Built-in analog-to-digital (A/D) 8-bit pixel  
resolution  
n Programmable features  
n Frame rate of 50 ~ 0.5 frames per second  
The digital video port supplies a continuous byte-  
wide image data. On-chip programmable features  
include variable frame rate, exposure setting, and  
image size. All the camera features are register  
based, accessing the video data and configuring  
the chip is as easy as read/write of a static mem-  
ory.  
(fps)  
n Exposure setting: 1 frame ~ 1/100 frame  
n Image size: 4.2 mm x 3.2 mm  
n AGC (auto gain control): 0 ~ 18 dB  
n Gamma correction: 0.45/1.0  
n Pixel elements - 384 x 288  
n Pixel dimension of 11 um x 11 um  
n External frame sync capability  
n Signal-to-noise (S/N) ratio > 42 dB  
n Minimum illumination of 0.5 lux at f1.4 at 50  
AGND  
N/C  
N/C  
7
8
9
42 VR2  
41 ZVDD  
40 OVDD  
39 D7  
38 D6  
37 D5  
36 D4  
35 D3  
34 D2  
33 D1  
fps  
n Single 5-volt supply operation for analog  
N/C 10  
N/C 11  
N/C 12  
N/C 13  
N/C 14  
N/C 15  
N/C 16  
N/C 17  
A3 18  
and 5/3.3 volts for digital  
OV5017  
n Power consumption  
— Active: less than 100 mW at 50 fps  
— Standby: less than 100 mA  
32 D0  
31 OGND  
n 48-pin package  
OV5017 PIN ASSIGNMENTS  
OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function, or  
design. OmniVision Technologies, Inc. does not assume any liability arising out of the application or use of any product or circuit described  
herein; neither does it convey any license under its patent rights nor the rights of others. No part of this publication may be copied or repro-  
duced, in any form without the prior written consent of OmniVision Technologies, Inc.  
Distributed by :COMedia Ltd, Rm802, Nan Fung tr, Castle Peak Rd, Tsuen Wan, NT, Hong Kong  
Tel: (852) 2498 6248 Fax: (852)2414 3050  
Version 1.6, October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
The Image Core is a complete analog video camera with 384 x 288 pixel size, which can run at full video  
speed. The analog video signal complies with CCIR standards. At 50 fps, it may be too fast for many  
applications; therefore, the frame rate or pixel rate can be programmed to match the external system  
requirements. The on-chip 8-bit A/D can convert the video signal at 50 fps, and the conversion is syn-  
chronized with the actual pixel rate.  
The OV5017 also outputs standard timing reference signals such as VSYNC, HREF, PCLK. Databus is  
shared by negating OEB.  
The exposure control can be set to auto or manual operation. Automatic exposure computation is based  
on full size image array and an exposure range over 100X. The AGC operation is tied to AEC in auto  
operation. Therefore, use automatic exposure control when selecting full image size. Manual exposure  
control allows individually adjusting exposure and gain based on actual application. Therefore, use man-  
ual exposure time if the window is smaller than full size or if the target object is brighter or darker than  
the average background.  
The frame rate divider can achieve various frame rates on the fly without changing the input clock fre-  
quency.  
Single frame operation provides one frame data transfer by controlling the assertion of HREF for one  
complete frame period. Setting FCTL(7) signals the control to assert the HREF in the next frame. Clear-  
ing this bit before the new frame cancels the assertion of HREF.  
Table 1.Pin Descriptions  
Pin #  
Class Pin Name  
Description  
Sensor ground. Connect to supply common.  
1
2
3
4
Bias  
Bias  
Bias  
I-0  
SGND  
SVDD  
AVDD  
FSI  
Sensor power (+5V) connection.  
Analog power (+5V) connection.  
External frame sync input. A rising edge on FSI sets the chip vertical sync timing.  
For proper operation, the frequency of FSI must be half of the programmed frame  
rate. Internally pulled down with a 100k resistor. Leave open or ground if unused.  
5
Bias  
Bias  
Bias  
FT  
VrCR  
AGND  
AGND  
N/C  
Internal reference voltage. Requires a 0.1uF external capacitor to AGND.  
Analog ground. Connect to supply common.  
6
7
Analog ground. Connect to supply common.  
8-17  
Factory test. Leave open.  
18, 19,  
20, 46  
I
A3-A0  
Address inputs for internal the registers. Requires CSB = 0 to access the registers.  
21  
I
OEB  
Output enable for the eight bit data bus. OEB = 0 enables the data bus drivers.  
OEB = 1 puts the data bus in tristate.  
2
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Table 1.Pin Descriptions (Continued)  
Pin #  
Class Pin Name  
Description  
22  
I
WEB  
Write enable input for the internal registers. When the chip is selected (CSB = 0),  
external data is latched into the registers with the rising edge of WEB.  
23  
I
CSB  
Chip select for the device. CSB = 0 selects the device.  
24, 25  
OD  
XCLKI,  
XCLKO  
Crystal oscillator in/out pins. Nominal clock frequency is 14.31MHz for CCIR 50 Hz  
timing. The maximum pixel rate is limited to one half of the clock frequency. To  
connect an external clock to XCLKI, leave XCLKO open.  
26  
27  
28  
OD  
OD  
OD  
HREF  
Horizontal timing reference output. Asserted high during every valid line for the  
duration of the valid window width. The window sizing function affects the number  
of valid lines in a frame as well as the number of valid pixels in a line. HREF and  
status(1), are identical valid pixel timing information.  
PCLK  
Pixel clock output. Defaulted to be a continuous clock. Can be programmed via the  
internal register to be on during the valid pixel window only. Video data at output  
bus (D0-D7) is updated with the rising edge of PCLK and is guaranteed to be valid  
at the falling edge of PCLK.  
VSYNC  
Vertical timing reference output. It is high once per frame for the duration of the  
vertical sync period. VSYNC and status (2) are identical vertical sync timing  
information.  
29  
Bias  
Bias  
Bias  
OD  
DVDD  
DGND  
OGND  
D0-D7  
Digital power (+5V) connection.  
30  
Digital ground. Connect to supply common  
Digital output ground. Connect to supply common  
31  
32-39  
Bi-directional data bus for video output data and internal register read/write  
operations.  
40  
41  
42  
43  
44  
45  
47  
48  
Bias  
Bias  
Bias  
Bias  
Bias  
Bias  
Bias  
Q
OVDD  
ZVDD  
VR2  
Digital output power (+5V/+3.3V) connection.  
Analog power (+5V) connection.  
Internal reference voltage. Requires a 0.1uF external capacitor to AGND.  
Analog ground. Connect to supply common.  
Decoder ground. Connect to supply common.  
Decoder power (+5V) connection.  
ZGND  
DEGND  
DEVDD  
VVDD  
AVO  
Video output power (+5V) connection.  
Composite video output. It is capable of driving 150 W load, Vp-p is 2.0 V.  
Pin Type and Default Level:  
I: digital input, floating, I-1: digital input, with 100k pull up, I-0: digital input, with 100k pull down, OD: digital CMOS level output, OA: analog  
CMOS, level output, XI/XO: xtal IO, K: analog input, Q: 75W output, FT: factory test, Bias: power supply bias  
October 20, 1997  
Version 1.6  
3
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
1. Video Data Bus  
PROGRAMMED HORIZONTAL WINDOW WIDTH  
HREF  
A[3:0]  
CSB  
VIDEO PORT ADDRESS  
OEB  
PCLK  
DATA[7:0]  
VD  
VD  
VD  
VD  
VD  
PIXEL DATA  
Figure 1. Video Data Timing Showing Continuous Pixel Reading  
The eight bit video data from the A/D converter is synchronous to PCLK. The lowest level is ‘h00’ and the  
highest is ‘hff’, no reserved code for blanking or sync.  
PCLK is the pixel clock that is either continuously on or present only during valid pixel window. If the con-  
tinuous clock is used, HREF is often used to qualify the pixel data. HREF is asserted during the pro-  
grammed horizontal and vertical window region. Video data is updated at the rising edge of PCLK and  
can be latched at the falling edge of PCLK.  
As shown in Figure 1, reading of the video data is not different from reading other on-chip registers, it  
requires the assertion of OEB and CSB and the correct address. To maintain uninterrupted video data  
stream, OV5017 video data will be updated at each pixel clock as long as the OEB, CSB, and correct  
address are asserted as shown in Figure 1.  
Since the video data is continuous during the active window, to prevent new data overruns the previous  
one, the host has to make sure at least one video data is read in every pixel clock period. The status reg-  
ister bit RDY and OV allows host to perform polling and error detection.  
1.1 Register Control  
The register read/write is the same as normal memory access, using pins DATA[7:0], A[3:0], WEB, OEB,  
and CSB. As shown in Figure 2 and Figure 3, the read cycle can be chip select controlled or address  
controlled. The write cycle also can be chip select controlled or write enable controlled. The memory  
cycle is fully asynchronous to the frame or pixel timing. Write cycle affects only the registers which are  
writable, it does not affect read only registers such as video port status register. Since writing to certain  
4
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
registers affects the basic camera operation, care must be taken when write occurs during the middle of  
active window. These effects are described in the individual register section. As a guide line, registers  
affects the frame rate, exposure time, window size, are better updated during the vertical sync  
.
CSB  
OEB  
WEB  
A[3:0]  
ADDN  
ADD0  
DATA[7:0]  
DATA0  
DATAN  
READ CYCLE  
READ CYCLE  
(ADDRESS CONTROLLED)  
(CS CONTROLLED)  
Figure 2. Register Access Showing a Single Byte Read  
OEB  
CSB  
WEB  
A[3:0]  
ADDN  
ADD0  
DATA[7:0]  
DATA0  
DATAN  
WRITE CYCLE  
WRITE CYCLE  
(CS CONTROLLED)  
(WE CONTROLLED)  
Figure 3. Register Access Showing Single Byte Write  
October 20, 1997  
Version 1.6  
5
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
2. Registers  
Table 2. Register Sets  
Register  
Default  
A[3:0]  
R/W  
Bit Name  
Function  
Value  
Name  
10xx  
VPORT  
R
R
VD[7:0]  
Video data  
xxxxxxxx  
00xxxxxx  
0000  
0001  
STATUS  
TO2,TO1, , ,OV,  
VSYNC, HREF, RDY  
Status register  
FCTL  
W
SFR, FSET, , ,  
SKIP, FBLC, STOP,  
SRST  
Single frame flow control  
system control  
00xx0000  
11111111  
0010  
EXCTL  
R/W  
AUTO, EX[6:0]  
Auto or manual exposure  
value  
0011  
0100  
0101  
GCTL  
FRCTL  
MCTL  
R/W  
R/W  
R/W  
GN[2:0]  
Gain value  
xxxxx000  
xx000000  
00000000  
FDIV[5:0]  
Frame rate divider  
Miscellaneous controls  
GAMMA, MIR, DN,  
BKL, FZEX, PCKS,  
PCKI, BPSHP  
0110  
0111  
1110  
1111  
HWCTL  
VWCTL  
TST  
R/W  
R/W  
W
HWS[3:0], HWE[3:0]  
VWS[3:0], VWE[3:0]  
TST[7:0]  
Window control  
Window control  
Reserved for test  
Reserved for test  
00000000  
00000000  
xxxxxxxx  
xxxxxxxx  
TOPT  
W
TOPT[7:0]  
Note: Unimplemented bits in all the R/W registers return “0” in the read cycle, no effect in the write cycle.  
2.1 Detailed Register Descriptions  
The following table describes the function of each bit within a register:  
Table 3. Bit descriptions  
Register  
Bit name  
Range  
VD[7:0]  
Function  
Name  
VPORT  
VD  
This register selects the video data port. The video data is not latched  
in this VPORT, as long as VPORT remains selected. The video data  
is updated as new pixel signals are converted.  
STATUS  
TO2  
STA7  
Reserved bit.  
6
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Table 3. Bit descriptions (Continued)  
Register  
Bit name  
Range  
Function  
Name  
TO1  
STA6  
Reserved bit.  
OV  
STA3  
Pixel data overrun flag. It is set each time pixel data is updated if  
STA0 has been set already. Reading of this register clears the bit.  
VSYNC  
HREF  
RDY  
STA2  
STA1  
STA0  
This bit duplicates the signal at pin VSYNC.  
This bit duplicates the signal at pin HREF.  
This bit is set each time pixel data is updated, and is cleared by read-  
ing the VPORT register. This bit will not be set if the VPORT register  
is being read while pixel data is updating.  
FCTL  
FSET  
SFR  
FCTL[7]  
FCTL[6]  
Set to initiate single frame transfer. This bit works only if FCTL[6] is  
also set. If this bit is set in the middle of a frame, HREF will not be  
asserted until the next new frame. This bit is cleared automatically at  
the end of the new frame so that it can be set again.  
Set to enable single frame operation mode. Since the video data is a  
continuous non-stop byte stream, the validity of the data is qualified  
only by assertion of HREF. In a continuous frame operation, HREF  
is asserted in every frame. In a single frame operation, HREF is  
asserted only for the first frame immediately after setting the FCTL[7].  
The actual duration of HREF assertion is programmed by the window  
size.  
SKIP  
FCTL[3]  
FCTL[2]  
Makes VSYNC and HREF to skip every other frame. This function  
does not alter the pixel rate; it simply blocks their assertion in every  
other frame.  
Chooses how frequent the black level calibration is performed inter-  
nally. It is set once every frame and cleared once every line. Line BLC  
can set the BLC within a fraction of a frame time. This is useful to  
speed up BLC process after power up or activation after standby  
mode. However, frame BLC provides better image stability.  
FBLC  
STOP  
SRST  
FCTL[1]  
FCTL[0]  
Set to stop chip clock and enter low power standby mode. This func-  
tion does not alter register content. The chip is put in default state and  
all image data is lost. Setting this bit does not prevent further register  
access. Upon clearing this bit, it generally takes about two frames for  
the chip to become stable.  
Software reset enable. Setting this bit resets all the on-chip registers  
and puts the chip in default state. Upon clearing this bit, it generally  
takes about two frames for the chip to become stable.  
October 20, 1997  
Version 1.6  
7
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Table 3. Bit descriptions (Continued)  
Register  
Bit name  
Range  
Function  
Name  
EXCTL  
AUTO  
EXCTL[7]  
Enables auto exposure. To select auto exposure mode, set this bit. To  
select manual exposure mode, clear this bit.  
EX  
EXCTL[6:0]  
GCTL[2:0]  
FRCTL[5:0]  
Sets the exposure time, where 7fh is the 1/50s, and 00h is the 1/  
(50*128*2)s. This register is used in manual exposure mode only.  
After updates are made to this register, it takes two frames for the  
chip to become stable.  
GCTL  
GN  
Selects the post amplifier gain, where 111 is the 18dB gain and 000 is  
the 0dB in a linear relationship. This register is used in manual expo-  
sure mode only. After updates are made to this register, it takes two  
frames for the chip to become stable.  
FRCTL  
FDIV  
Divides the frame rate by 1 to 64 in steps of 1 by using this formula:  
Frame Rate = F / (FDIV+1)  
0
Pixel Rate = f  
/ [(FDIV +1)*2]  
osc  
where f  
is the main clock frequency of XCLKi  
osc  
F = f  
/ (458*625); F =50 @ 14.318Mhz  
0
0
osc  
After updates are made to this register, it takes two frames for the  
chip to become stable.  
MCTL  
GAMA  
MIR  
MCTL[7]  
MCTL[6]  
MCTL[5]  
MCTL[4]  
MCTL[3]  
Set this bit to select gamma = 0.45, and clear this bit for gamma = 1.  
Set this bit to select mirror image.  
NSR  
BKL  
Set this bit to turn on indoor mode, and clear for outdoor mode.  
Set this bit to turn on backlight compensation.  
FZEX  
Set this bit to freeze the exposure setting. This works in auto expo-  
sure mode; it has no effect in manual exposure mode.  
PCKS  
MCTL[2]  
Clear this bit to output continuous pixel clock to PCLK; set to output  
pixel clock only during the valid pixel window  
PCKI  
BPSHP  
HWS  
HWE  
VWS  
VWE  
MCTL[1]  
Set this bit to inverse the polarity of PCLK.  
Set this bit to disable sharpness function.  
Selects the start of the horizontal window.  
Selects the end of the horizontal window.  
Selects the start of the vertical window.  
Selects the end of the vertical window.  
MCTL[0]  
HWCTL/  
VWCTL  
HWCTL[7:4]  
HWCTL[3:0]  
VWCTL[7:4]  
VWCTL[3:0]  
8
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Table 3. Bit descriptions (Continued)  
Register  
Bit name  
Range  
Function  
Name  
The array is divided into 16x16 blocks as  
shown in Figure 1.1. each block is H24xV18 pixels.  
The method for selecting vertical and horizontal  
window region is the same. Each direction uses an  
eight-bit register. Bit [7:4] selects the start block  
location. Bit [3:0] selects the end block location. For  
example, to select the shaded area as the active  
region, use HWCTL=4cH,VWCTL=44H.  
HREF  
HWE  
11  
HWS  
0 1 2 3  
7
15  
This window selection feature changes only the  
assertion time of HREF and does not change the  
pixel rate or the data rate. If the end location is  
equal to or less than the start location, the window  
size is from start location to the end of the right  
most edge.  
VWS  
VWE  
– 24 X18 PIXELS  
Figure 4. Windowing  
October 20, 1997  
Version 1.6  
9
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
3. Electrical Specifications  
This section provides the electrical parameters descriptions and timing diagrams.  
3.1 Electrical Parameters  
o
o
Table 4. Electrical parameters (0 C < TA < 85 C, voltages referenced to GND)  
Symbol  
Supply  
Descriptions  
Max  
Type  
Min  
Units  
V
Supply voltage (digital/analog: DEVDD,  
ZVDD, AVDD, SVDD, VVDD, DVDD)  
5.25  
5.0  
4.75  
V
DD1  
V
Supply voltage (OVDD)  
5.5  
3.6  
5.0  
3.3  
4.5  
3.0  
V
V
DD2  
I
I
Supply Current (@ 50fps, 50pf CMOS load  
on data bus)  
40  
-
-
mA  
DD1  
Standby supply current  
100  
-
-
uA  
DD2  
Inputs  
V
V
Input voltage LOW  
Input voltage HIGH  
0.8  
-
-
-
-
V
V
IL  
2.0  
IH  
Cin  
t , t  
Input capacitor  
10  
25  
-
-
-
-
pF  
ns  
Digital input rise/fall time  
r
r
Outputs - standard load 25pf, 1.2kW to 3.0volts  
V
V
Output voltage HIGH  
Output voltage LOW  
-
-
-
2.4  
-
V
V
OH  
OL  
0.6  
Clock input / Crystal Oscillator  
f
Resonator frequency  
-
-
14.31818  
-
-
MHz  
osc  
Load capacitor  
10  
1M  
-
pF  
W
ns  
%
Parallel resistance  
Clock input rise/fall time  
Duty cycle if external clock input  
5
25  
40  
60  
Video timing  
t
t
t
PCLK cycle time (@ 50Hz fps)  
PCLK to HREF delay  
-
-
-
-
139  
ns  
ns  
ns  
PCLK  
PHD  
PDD  
25  
25  
-
-
PCLK to DATA delay  
10  
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
o
o
Table 4. Electrical parameters (0 C < TA < 85 C, voltages referenced to GND) (Continued)  
Symbol  
Descriptions  
Max  
Type  
Min  
Units  
Interface timing  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output enable access time  
Output enable to Z delay  
Register read cycle time  
Chip select pulse width  
Chip select access time  
Chip select to data invalid time  
Address access time  
15  
15  
-
-
-
-
-
-
-
ns  
ns  
OE  
OEZ  
RC  
100  
50  
ns  
-
ns  
CS  
30  
15  
30  
15  
-
ns  
CSA  
CSX  
AA  
ns  
ns  
Address data invalid time  
Register write cycle time  
Write enable pulse width  
Write cycle address set up time  
Write cycle address hold time  
Write cycle data set up time  
Write cycle data hold time  
External FSI cycle time  
Chip power up time  
-
-
ns  
AX  
100  
50  
0
ns  
WC  
WE  
AS  
-
-
ns  
-
-
ns  
-
-
0
ns  
AH  
-
-
20  
0
ns  
DS  
-
-
ns  
DH  
-
2
-
-
frame  
us  
SYNC  
PD  
100  
-
DIGIAL/Analog video parameters  
AVO Composite video level (p-p)  
AV  
-
2.0  
-
-
V
sync amplitude  
0.55  
0.6  
V
SYNC  
Ravo  
Output load resistance  
horizontal line width  
150  
458  
Ohm  
pclk  
t
t
t
t
t
H
horizontal sync width  
32  
9
pclk  
pclk  
pclk  
pclk  
HSYNC  
HF  
horizontal blank front porch  
horizontal blank back porch  
active pixel in one scan line  
33  
384  
HB  
HACT  
October 20, 1997  
Version 1.6  
11  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
o
o
Table 4. Electrical parameters (0 C < TA < 85 C, voltages referenced to GND) (Continued)  
Symbol  
Descriptions  
field 2 vertica back equaliztion width  
vertical field width  
Max  
Type  
-
Min  
Units  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
VB1  
H
H
H
H
H
H
H
H
312.5  
2.5  
3
V
vertical sync width  
VSYNC  
VF1  
field 1 vertical front equlization width  
field 1 vertica back equaliztion width  
field 2 vertical front equlization width  
field 2 vertica back equaliztion width  
active line in a field  
19  
VB1  
VF2  
2.5  
19.5  
288  
VB2  
VACT  
12  
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
3.2 Timing diagrams  
Figure 5. Video Data Timing (384 x 288), PCLK = 1/4 XCLKi  
October 20, 1997  
Version 1.6  
13  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Figure 6. Video Port Timing (192 x 144), PCLK = 1/2 XCLKi  
14  
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
October 20, 1997  
Version 1.6  
15  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Figure 7. Video Port Timing (384 x 288), PCLK = 1/2 XCLKi  
Figure 8. Pixel Timing  
16  
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
Figure 9. Register R/W Timing  
October 20, 1997  
Version 1.6  
17  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
1
DIE  
Package Center  
(0, 0)  
SENSOR  
ARRAY  
Array Center  
(-0.030, -0.017)  
Top View  
Figure 10. OV5017 Sensor Array Location Dimensions (in inches)  
18  
Version 1.6  
October 20, 1997  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
+0.010  
0.440 ±0.005  
0.040 ±0.003  
0.060 -0.005  
TYP.  
0.040 ±0.007  
31  
42  
TYP.  
NOTES:  
1) All dimensions in inches  
43  
48  
30  
0.020 ±0.003  
TYP.  
19  
6
R 0.0075  
4 CORNERS  
18  
7
R 0.0075  
48 PLCS  
0.085 ±0.010  
0.003  
0.003  
0.065 ±0.007  
0.002  
+0.012  
0.030 ±0.003  
0.560 SQ. -0.005  
0.430 SQ. ±0.005  
0.350 SQ. ±0.005  
0.015 ±0.002  
0.020 ±0.002  
42  
43  
31  
30  
31  
42  
43  
30  
48  
1
19  
6
7
6
19  
7
18  
18  
0.006 MAX.  
0.002 TYP.  
Figure 11. OV5017 Package Outline Dimensions  
October 20, 1997  
Version 1.6  
19  
OMNIVISION TECHNOLOGIES, Inc.  
Confidential Preliminary Product Specification  
OV5017  
ERRATA  
11/20/97  
1. In default mode, the video data changes on the falling edge of PCLK instead of on the rising edge. We  
recommand inverting the PCLK pin polarity by setting MCTL(1) so the video data can still be latched  
on the falling edge of PCLK. All the pclk timing parameters is applied to inverted PCLK.  
2. OV5017 default active HREF window width has one extra pixel, 385 instead of 384, the back porch  
blanking is one less, that is:  
t
= 385, t = 32.  
HB  
HACT  
2/14/98  
3. A glitch ( width 1/2 ~ 10 PCLKS) in HREF appears between VSYNC and the first valid HREF if pro-  
grammed FRCTL(5:0) >= 9.  
4. Intensity of lines (32,33,256,257) may be different from the rest of image if programmed FRCTL(5:0)=  
4,5,9~11,13~15,17~22,24~63.  
20  
Version 1.6  
October 20, 1997  
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