WV3HG2128M72EEU-AD4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
0°C ≤ TCASE < +70°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
Symbol
Proposed Conditions
806
665
534
403
Units
ICC0*
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,218 1,173 1,128
mA
TBD
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
1,308 1,263 1,218
mA
TBD
ICC2P**
ICC2Q**
ICC2N**
ICC3P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
516
516
930
516
930
mA
mA
mA
TBD
TBD
TBD
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
1,020
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
1,110 1,020 1,020
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
840
516
750
516
750
516
mA
mA
TBD
TBD
Slow PDN Exit MRS(12) = 1
ICC3N**
ICC4W*
ICC4R*
ICC5**
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
1,200 1,110 1,110
1,803 1,578 1,443
1,803 1,578 1,443
4,260 4,170 4,080
mA
mA
mA
TBD
TBD
TBD
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC),
tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as ICC4W
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
mA
TBD
TBD
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
108
108
108
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
3,108 2,928 2,748
mA
TBD
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R
;
Refer to the following page for detailed timing conditions
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in the operating condition.
February 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
