WV3HG64M72EER-D7
White Electronic Designs
PRELIMINARY
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V
Symbol
Parameter
Condition
806
665
534
403
Unit
tCK = tCK(DD); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH
CC
CC
Operating one bank
active-precharge;
ICC0*
between valid commands; Address bus inputs are SWITCHING; Data bus
1120
1120
mA
TBD
TBD
inputs are SWITCHING
Operating one
ICC1* bank active-read-
precharge;
IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I
;
)
CC
CKE is HIGH, CS# is HIGH between valid cCoCmmands; Address bus inputs aCreC
1255
1255
mA
TBD
TBD
SWITCHING; Data bus inputs are SWITCHING; Data pattern is same as ICC4W
.
Precharge power-
All banks idle; tCK = tCK(I ); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus iCnCputs are FLOATING
ICC2P**
472
670
715
670
508
472
670
715
670
508
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
down current;
Precharge quite
standby current;
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and
CC
ICC2Q**
address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control and
current;
CC
ICC2N**
address bus inputs are STABLE; Data bus inputs are SWITCHING
Fast PDN Exit
All banks open; tCK = tCK(I ), CKE is LOW; Other control
CC
MRS(12) = 0
Active power-down
current;
ICC3P**
and address bus inputs are STABLE; Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
All banks open; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH,
CC
CC
CC
Active standby
current;
ICC3N**
CS# is HIGH between valid commands; Other control and address bus inputs
850
850
mA
mA
TBD
TBD
TBD
TBD
are SWITCHING; Data bus inputs are SWITCHING
All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK
=
Operating burst
write current;
tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is HIGH between
CC CC
valid commands;CACddress bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC4W*
1480
1390
All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC);
Operating burst
read current;
AL = 0; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is
CC
HIGH between valid commandCsC; Address bus inpCuCts are SWITCHING; Data
ICC4R*
1525
1390
mA
TBD
TBD
pattern is same as ICC4W
.
tCK = tCK(I ); Refresh command at every tRC(I ) interval; CKE is HIGH; CS#
CC
is HIGH between valid commands; Other conCtrCol and address bus inputs are
1660
472
1660
472
mA
mA
Burst auto refresh
current;
ICC5**
TBD
TBD
TBD
TBD
SWITCHING; Data bus inputs are SWITCHING
CK and CK# at 0V; CKE < 0.2V; Other control and address
Normal
ICC6** Self refresh current;
bus inputs are FLOATING; Data bus inputs are FLOATING
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(I
)
CC
Operating bank
ICC7* interleave read
current;
- 1*tCK(I ); tCK = tCK(I ); tRC = tRC(I ); tRRD = tRRD MIN(I ) = 1*tCK(I ); CKE is
CC
CC
HIGH; CS# is HIGH between validCcCommands; AddreCsCs bus inpuCtsC are STABLE
2380
2380
mA
TBD
TBD
during DESELECTs; Data bus inputs are SWITCHING
Notes:
CC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different.
I
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
February 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
