WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
Component Notes
1. tHZ and tLZ transitions occur in the same access
time windows as valid data transitions. these
parameters are not referenced to a specific voltage
level but specify when the device output in no
longer driving (HZ), or begins driving (LZ).
10. Min (tCL, tCH) refers to the smaller of the actual clock
low time and the actual clock high time as provided
to the device (i.e. this value can be greater than the
minimum specification limits for tCL and tCH).....For
example, tCL and tCH are = 50% of the period, less
the half period jitter (tJIT(HP)) of the clock source,
and less the half period jitter due to crosstalk
(tJIT(crosstalk)) into the clock traces.
2. The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
11. tQH = tHP - tQHS, where:
t
HP = minimum half clock period for any given cycle
3. The specific requirement is that DQS be valid
(HIGH, LOW, or at some point on a valid transition)
on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew
rate specifications of the device. when no writes
were previously in progress on the bus, DQS will
be tran sitioning from High- Z to logic LOW. If a
previous write was in progress, DQS could be
HIGH, LOW, or transitioning from HIGH to LOW at
and is defined by clock high or clock low (tCH, tCL).
QHS accounts for 1) The pulse duration distortion
t
of on-chip clock circuits; and 2) The worst case
push-out of DQS on one tansition followed by the
worst case pull-in of DQ on the next transition, both
of which are, separately, due to data pin skew and
output pattern effects, and pchannel to n-channel
variation of the output drivers.
this time, depending on tDQSS
.
12. tDQSQ
Consists of data pin skew and output pattern
effects, and p-channel to n-channel variation of the
output drivers for any given cycle.
4. A maximum of eight AUTO REFRESH commands
can be posted to any given DDR SDRAM device.
5. For command/address input slew rate: 1.0 V/ns
13. tDAL = (tWR/tCK) + (tRP/tCK
)
6. For command/address input slew rate: 0.5 V/ns
and 1.0 V/ns
For each of the terms above, if not already an
integer, round to the next highest integer. Example:
For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15
ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5
clocks
7. For CK & CK# slew rate 1.0 V/ns
8. These parameters guarantee device timing, but
they are not necessarily tested on each device.
They may be guaranteed by device design or tester
correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac)
.
July 2005
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
