WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = +1.8V 0.1V
Symbol Proposed Conditions
Operating one bank active-precharge current;
ICC0* tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
806
665
534
403
Units
2,336 2,246 2,156
mA
TBD
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
=
ICC1*
2,516 2,426 2,336
mA
TBD
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as ICC4W
Precharge power-down current;
ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
932
932
932
mA
mA
mA
TBD
TBD
TBD
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
1,940 1,760 1,760
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
2,120 1,940 1,940
1,580 1,400 1,400
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
mA
mA
TBD
TBD
ICC3P**
Slow PDN Exit MRS(12) = 1
932
932
932
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC3N**
2,300 2,120 2,120
3,056 2,876 2,516
mA
mA
TBD
TBD
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4W*
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
=
ICC4R*
3,056 2,876 2,516
8,420 8,240 8,060
mA
mA
mA
TBD
TBD
TBD
Burst auto refresh current;
ICC5B** tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
ICC6**
Normal
360
360
360
inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
ICC7* tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
6,116 5,756 5,396
mA
TBD
Note:
CC specs are based on SAMSUNG components. Other DRAM manufacturers parameters may be different.
* Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.
I
April 2006
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
