WT62P1
Data Sheet Rev. 1.01
DDC Interface
The DDC interface is a slave mode I2C interface with DDC1 function. It is compatible with VESA
DDC1/2B standard. This interface not only can be used for DDC communication, but also can be applied
for factory alignment purpose.
When ENDDC bit is set, the outputs of SDA1 and SCL1 pins are open-drain type. The DDC function
depends on the DDC2 bit value. If DDC2 bit is “ 0” , it is in DDC1 state. If DDC2 bit is “ 1” , it is in DDC2
state
In DDC1 state, the data is shifted out to SDA1 pin on the rising edge of VSYNC clock. Data format is an
8-bit byte followed by a null bit (always “ 1” ). Most significant bit (MSB) is transmitted first. Every time
when the ninth bit has been transmitted, the shift register will load a data byte from data buffer (DDC_TX
register). After loading data to the shift register, the data buffer becomes empty and generates an
interrupt. Program can check DDCRDY bit to load new data byte.
If a high to low transition occurs on SCL1 in DDC1 state, the SCLH2L bit will be set and generate an
interrupt. Program can set DDC2 bit to enter DDC2 state. If no valid DDC2 command is received within a
certain time (for example, 128 Vsync clocks or 2sec), program should clear DDC2 bit and back to DDC1
state to avoid noise interference.
The data format of DDC2 is
S
Address R/W A
D7,D6,...., D0
A
D7,D6,...., D0
A
P
S : Start condition. A falling edge on SDA1 pin when SCL1 pin is high level.
P : Stop condition. A rising edge on SDA1 pin when SCL1 pin is high level.
A : Acknowledge bit. ꢀ0ꢁ means acknowledge and ꢀ1ꢁ means non-acknowledge.
Address : 7-bit device address.
R/W : Read/Write control bit, "1" is read and "0" is write.
D7,D6,...., D0 : data byte.
In DDC2 state, after START and valid address is received, it send out ACK(“ 0” ) if the TXNAK1 bit is “ 0” .
Otherwise the SDA1 pin outputs NACK(” 1” ). An interrupt will be generated after sending ACK bit and
SCL1 pin is pulled low to stop the clock for handshaking. In the interrupt routine, write DDC_AR0 register
will stop pulling low the SCL1 pin and clear the interrupt. The received address byte can be read in
DDC_RX register and also can use MATCH bit to identify what address is received. The Write or Read
operation can be checked by reading the DDCRW bit.
Write operation
After received the first byte (address byte), interrupt routine finds it is the first byte (FIRST=1) and write
operation (DDCRW=0), program should clear TX bit to “ 0” (for receiving data) and write DDC_AR0
register (to release the SCL1 pin). Then the host sends out a data byte and SDA1 pin outputs ACK if
TXNACK bit is “ 0” . An interrupt is generated after the ACK bit to inform CPU to read DDC_RX register.
When host finished transferring data, it will send STOP condition. When STOP condition is detected, the
STOP bit will be set and generates an interrupt. The interrupt routine can use the STOP bit to know the
data transfer is finished and start executing the received command.
Read operation
After received the first byte (address byte), interrupt routine finds it is the first byte (FIRST=1) and read
operation (DDCRW=1), program should set TX bit to “ 1” , write data to DDC_TX register and write
DDC_AR0 register (to release the SCL1 pin). The host will output ACK after received a data byte. When
host wants to finish reading, it outputs NACK to stop communication. Program can read the RXACK1 bit
to check the acknowledge bit that host sends.
Weltrend Semiconductor, Inc.
Page 18
