WV3HG32M72EEU-D4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
Active
Rank
Parameter
State Condition
806
665
553
403
Units
Operating one device
bank active-precharge
current;
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
ICC0
TBD
1,245
1,200
1,155
mA
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC),
tRAS = tRAS MIN (ICC), tRCD = tRCD (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
Operating one device
bank active-read-
precharge current;
ICC1
TBD
1,335
1,290
1,200
mA
pattern is same as ICC4W
.
Precharge power-down
current;
All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
ICC2P
TBD
TBD
372
570
375
525
372
525
mA
mA
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
ICC2Q control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge quiet
standby current;
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
ICC2N control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Precharge standby
current;
TBD
615
570
570
mA
Fast PDN Exit
TBD
TBD
615
435
570
435
570
435
mA
mA
All device banks open; tCK = tCK (ICC); CKE is LOW;
ICC3P Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
MR[12] = 0
Active power-down
current;
Slow PDN Exit
MR[12] = 1
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC);
ICC3N CKE is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Active standby current;
TBD
TBD
975
930
885
mA
mA
All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC),
Operating burst write
current;
AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is
ICC4W
2,190
1,875
1,515
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
Operating burst read
current;
= CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC);
ICC4R
TBD
1,965
1,740
1,470
mA
CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE
Burst refresh current;
Self refresh current;
ICC5
is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
TBD
1,830
45
1,785
45
1,740
45
mA
mA
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
ICC6
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC),
AL = tRCD (ICC)-1 x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING; See ICC7 Conditions for detail.
Operating device bank
interleave read current;
ICC7
TBD
2,685
2,595
2,595
mA
Note:
• ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
January 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
