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iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

64Mx72 DDR2 SDRAM

iNTEGRATED Plastic Encapsulated Microcircuit

FEATURES

BENEFITS



DDR2 Data rate = 667, 533, 400



Space conscious PBGA deﬁned for easy

Available in Industrial, Enhanced and Military Temp

Packages:

• 255 Plastic Ball Grid Array (PBGA), 25 x 32mm,

1.27mm pitch

SMT manufacturability (1.27mm or

1.0mm pitch)

Reduced part count

Signiﬁcant I/O reduction vs individual

CSP approach



• 208 PBGA, 16 x 22mm, 1.0mm pitch (page 27-28)

Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4n-bit prefetch architecture

DLL for alignment of DQ and DQS transitions with

clock signal



Reduced trace lengths for lower parasitic

capacitance



Suitable for hi-reliability applications

Upgradable to 128M x 72 density



Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)

Configuration Addressing



Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes (I/T Version)

On Die Termination (ODT)

Adjustable data – output drive strength

1.8V ±0.1V power supply and I/O (VCC/VCCQ)

Programmable CAS latency: 3, 4, 5, 6 or 7

Posted CAS additive latency: 0, 1, 2, 3, 4 or 5

Write latency = Read latency - 1* tCK

Organized as 64M x 72 w/ support for x80

Weight: AS4DDR264M72PBG ~ 3.5 grams typical

Parameter

64 Meg x 72

8 Meg x 16 x 8 Banks

8K

Configuration

Refresh Count

Row Address

Bank Address

Column Address

A0‐A12 (8k)

BA0‐BA2 (8)

A0‐A9 (1K)

NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only

FUNCTIONAL BLOCK DIAGRAM

Ax, BA0-1

ODT

VRef

VCC

VCCQ

VSS

VSSQ

VCCL

VSSDL

A

B

C

D

2

DQ64-79

CS0\

CS1\

CS2\

CS3\

2

3

2

3

CS4\

2

UDMx, LDMx

UDSQx,UDSQx\

LDSQx, LDSQx\

RASx\,CASx\,WEx\

CKx,CKx\,CKEx

3

C

B

D

DQ16-31

A

DQ0-15

DQ32-47

DQ48-63

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

1

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

4.8Gb SDRAM-DDRII PINOUT FOR 255 BGA TOP VIEW (SEE PAGE 27 FOR 208 BGA)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

a

b

c

d

e

f

DQ0

DQ14

DQ15

VSS

A9

A10

A11

A8

VCCQ VCCQ DQ16

DQ17

DQ31

VSS

a

b

c

d

e

f

DQ1

DQ3

DQ2

DQ4

DQ12

DQ10

DQ8

DQ13

DQ11

DQ9

VSS

VCC

VSS

VCC

A0

A2

A7

A5

A6

A4

A1

A3

VCC

VSS

VCC

VSS

DQ18

DQ20

DQ22

LDM1

WE1\

CS1\

VSS

DQ19

DQ21

DQ23

VSS

DQ29

DQ27

DQ26

NC

DQ30

DQ28

DQ25

DQ24

CLK1

CKE1

VCC

DQ6

DQ5

VCCQ VCCQ A12/NC DNU

BA2

BA1

NC

DNU

DQ7

LDM0

WE0\

RAS0\

VSS

VCC

DQ55

DQ53

DQ51

UDM0 UDQS3 LDQS0 UDQS0

BA0

LDQS1 UDQS1 VREF

UDQS1\ LDQS1\ RAS1\

CAS0\

CS0\

VSS

CLK0 LDQS3 UDQS3\ LDQS0\ UDQS0\

VSS

UDM1

CLK1\

VCCQ

RAS2\

WE2\

LDM2

DQ37

DQ36

DQ34

g

h

j

CKE0

VCCQ

CLK0\ LDQS3\ VSSQ VSSQ VSSQ VSSQ

NC

CAS1\

VCC

VSS

g

h

j

VSS

NC

VSSQ VSSQ VSSQ VSSQ

VSS

VCC

VSS

VCC

k

l

CLK3\

NC

CKE3

CLK3

UDM3

DQ58

DQ59

DQ61

CS3\ LDQS4 UDQS4\ VSSQ VSSQ VSSQ VSSQ

CLK2\

CKE2

VSS

CS2\

k

l

CAS3\ RAS3\

ODT LDQS4\

NC

LDQS2\ UDQS2\ LDQS2 CLK2

VSS

CAS2\

DQ39

DQ38

DQ35

DQ33

VCC

m

n

p

r

DQ56

DQ57

DQ60

DQ62

WE3\

LDM3

CKE4

UDM4

DQ73

DQ75

DQ77

CLK4

DQ72

DQ74

DQ76

CAS4\

DQ71

DQ69

DQ67

WE4\

DQ70

DQ68

DQ66

RAS4\

CS4\

UDM2

VSS

m

n

p

r

DQ54 UDQS4 CLK4\

LDM4 UDQS2 DQ41

DQ40

DQ42

DQ44

DQ52

DQ50

VSS

VCC

VSS

VCC

VSS

VCC

VSS

DQ43

DQ45

t

VSS

1

DQ63

DQ49

DQ48 VCCQ VCCQ DQ79

DQ78

DQ65

DQ64

VSS

11

VSS

12

DQ47

DQ46

DQ32

t

2

3

4

5

6

7

8

9

10

13

14

15

Ground

Array Power

CNTRL

D/Q Power

Address

Data IO

NC

Level REF.

ADDRESS-DNU

UNPOPULATED

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

2

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

BGA Locations

Symbol

Type

Description

L6

ODT

CNTL Input On‐Die‐Termination: Registered High enables on data bus termination

F4, F16, G5, G15, K1

K12, L2, L13, N6, M8

G4, G16, K13, K2, M6

G1, G13, K16, K4, M12

F12, G2, K15, L5, M11

F1, G12, L16, L4, M9

F2, F13, L15, M4, M10

E4, F15, M13, M2, M7

E2, E13, M15, M5, N11

E5, E7, E11, N12, N5

F6, F8, F10, L11, L7

E6, E10, F5, L12, K5

F7, F11, G6, L10, K6

A7, A8, A9, A10, B7,

B8, B9, B10, C7, C8,

C9, C10, D7

CLKx, CLKx\

CNTL Input Differential input clocks, one set for each x16bits

CKEx

CSx\

CNTL Input Clock enable which activates all on silicon clocking circuitry

CNTL Input Chip Selects, one for each 16 bits of the data bus width

CNTL Input Command input which along with CAS\, WE\ and CS\ define operations

CNTL Input Command input which along with RAS\, WE\ and CS\ define operations

CNTL Input Command input which along with RAS\, CAS\ and CS\ define operations

CNTL Input One Data Mask cntl. for each upper 8 bits of a x16 word

CNTL Input One Data Mask cntl. For each lower 8 bits of a x16 word

CNTL Input Data Strobe input for upper byte of each x16 word

CNTL Input Differential input of UDQSx, only used when Differential DQS mode is enabled

CNTL Input Data Strobe input for lower byte of each x16 word

CNTL Input Differential input of LDQSx, only used when Differential DQS mode is enabled

RASx\

CASx\

Wex\

UDMx

LDMx

UDQSx

UDQSx\

LDQSx

LDQSx\

Ax

Input

Array Address inputs providing ROW addresses for Active commands, and

the column address and auto precharge bit (A10) for READ/WRITE commands

D8, D10

E8, E9, D9

DNU

BA0, BA1, BA2

DQx

Future Input See Note 1 on Pg. 2

Input Bank Address inputs

Input/Output Data bidirectional input/Output pins

A2, A3, A4, A13, A14,

A15, B1, B2, B3, B4,

B13, B14, B15, B16,

C1, C2, C3, C4, C13,

C14, C15, C16, D1, D2,

D3, D4, D13, D14, D15,

D16, E1, E16, M1, M16,

N1, N2, N3, N4, N7, N8, N9

N10, N13, N14, N15, N16,

P1, P2, P3, P4, P7, P8, P9

P10, P14, P15, P16,

R1, R2, R3, R4, R7, R8, R9,

R10, R13,R14,R15, R16, T2,

T3,T4, T7, T8, T9, T10, T13,

T14, T15

E12

Vref

VCC

Supply

SSTL_18 Voltage Reference

Core Power Supply

B11, B12, C5, C6,E3,

F3, G3, H3, H12, H16,

J3, J12, J16, K3, L3,

M3, P11, P12, R5, R6,

T16

A11, A12, D5, D6, H4,

H15, J4, J15, T5, T6

A5, A6, A16, B5, B6,

C11, C12, D11, D12,

E14, F14, G14, H1, H2,

H5, H13, H14, J1, J2,

J5, J13, J14, K14, L14,

M14, P5,P6, R11, R12,

T1, T11, T12

VCCQ

VSS

Supply

I/O Power

Core Ground return

G7, G8, G9, G10, H7,

H8, H9, H10, J7, J8, J9,

J10, K7, K8, K9, K10

E15, F9, G11, H6, H11,

J6, J11, K11,

VSSQ

NC

Supply

I/O Ground return

No connection

L1, L8, L9

A1

UNPOPULATED

Unpopulated ball matrix location (location registration aid)

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

3

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

DESCRIPTION

The 4.8Gb DDR2 SDRAM, a high-speed CMOS, dynamic

random-access memory containing 4,831,838,208 bits.

Each of the ﬁve chips in the MCP are internally conﬁgured

as 8-bank DRAM. The block diagram of the device is

shown in Figure 2. Ball assignments and are shown in

Figure 3.

An auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst access.

As with standard DDR SDRAMs, the pipelined, multibank

architecture of DDR2 SDRAMs allows for concurrent

operation, thereby providing high, effective bandwidth by

hiding row precharge and activation time.

The 4.8Gb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer

two data words per clock cycle at the I/O balls. A

single read or write access for the x72 DDR2 SDRAM

effectively consists of a single 4n-bit-wide, one-clock-

cycle data transfer at the internal DRAM core and four

corresponding n-bit-wide, one-half-clock-cycle data

transfers at the I/O balls.

A self refresh mode is provided, along with a power-

saving power-down mode.

All inputs are compatible with the JEDEC standard for

SSTL_18. All full drive-strength outputs are SSTL_18-

compatible.

GENERAL NOTES

• The functionality and the timing speciﬁcations

discussed in this data sheet are for the DLLenabled

mode of operation.

A bidirectional data strobe (DQS, DQS#) is transmitted

externally, along with data, for use in data capture at the

receiver. DQS is a strobe transmitted by the DDR2

SDRAM during READs and by the memory controller

during WRITEs. DQS is edge-aligned with data for

READs and center-aligned with data for WRITEs. There

are strobes, one for the lower byte (LDQS, LDQS#) and

one for the upper byte (UDQS, UDQS#).

• Throughout the data sheet, the various ﬁgures and

text refer to DQs as ¡°DQ.¡± The DQ term is to be

interpreted as any and all DQ collectively, unless

speciﬁcally stated otherwise. Additionally, each chip

is divided into 2 bytes, the lower byte and upper

byte. For the lower byte (DQ0¨CDQ7), DM refers to

LDM and DQS refers to LDQS. For the upper byte

(DQ8¨CDQ15), DM refers to UDM and DQS refers to

UDQS.

• Complete functionality is described throughout

the document and any page or diagram may have

been simpliﬁed to convey a topic and may not be

inclusive of all requirements.

The MCP DDR2 SDRAM operates from a differential

clock (CK and CK#); the crossing of CK going HIGH

and CK# going LOW will be referred to as the positive

edge of CK. Commands (address and control signals)

are registered at every positive edge of CK. Input data

is registered on both edges of DQS, and output data

is referenced to both edges of DQS, as well as to both

edges of CK.

• Any speciﬁc requirement takes precedence over a

general statement.

Read and write accesses to the DDR2 SDRAM are

burst oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed.

The address bits registered coincident with the READ

or WRITE command are used to select the bank and the

starting column location for the burst access.

INITIALIZATION

DDR2 SDRAMs must be powered up and initialized

in a predeﬁned manner. Operational procedures other

than those speciﬁed may result in undeﬁned operation.

The following sequence is required for power up and

initialization and is shown in Figure 4 on page 5.

The DDR2 SDRAM provides for programmable read

or write burst lengths of four or eight locations. DDR2

SDRAM supports interrupting a burst read of eight with

another read, or a burst write of eight with another

write.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

4

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

FIGURE 4 - POWER-UP AND INITIALIZATION

Notes appear on page 7

VDD

VDDL

VDDQ

t

1

VTD

_TT1

V

VREF

Tk0

Tl0

Tm0

Tg0

Th0

Ti0

Tj0

Te0

Tf0

Tc0

Td0

Tb0

T0

Ta0

t

CK

CK#

CK

t

CL

SSTL_18

LVCMOS

2

LOW LEVEL

CKE

ODT

3

LOW LEVEL

16

Valid

7

5

6

8

9

10

REF

11

12

13

LM

4

Command

REF

LM

PRE

LM

PRE

LM

NOP

15

DM

3

Address

Code

A10 = 1

Code

A10 = 1

Valid

15

High-Z

DQS

15

DQ

RTT

t

MRD

t

T = 400ns

16

T = 200µs (MIN)

Power-up:

RPA

MRD

RPA

RFC

MRD

(MIN)

See note 17

V

DD and stable

EMR(2)

EMR(3)

EMR

MR without

EMR with

OCD exit

clock (CK, CK#)

DLL RESET

OCD default

Normal

operation

200 cycles of CK are required before a READ command can be issued.

MR with

DLL RESET

Indicates a break in

time scale

Don’t care

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

5

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

NOTES:

6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3)

command, provide HIGH to BA0 and BA1; remaining EMR(3) bits

must be “0.” See “Extended Mode Register 3 (EMR 3)” on page 13

for all EMR(3) requirements.

7. Issue a LOAD MODE command to the EMR to enable DLL. To issue

a DLL ENABLE command, provide LOW to BA1 and A0; provide

HIGH to BA0; bits E7, E8, and E9 can be set to “0” or “1;” Austin

recommends setting them to “0;” remaining EMR bits must be “0.

”See “Extended Mode Register (EMR)” on page 10 for all EMR

requirements.

1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs

remain disabled. To guarantee RTT (ODT resistance) is off,

VREF must be valid and a low level must be applied to the ODT ball (all

other inputs may be undeﬁned, I/Os and outputs must be less

than VCCQ during voltage ramp time to avoid DDR2 SDRAM

device latch-up). VTT is not applied directly to the device; however,

tVTD should be ³0 to avoid device latch-up. At least one of the

following two sets of conditions (A or B) must be met to obtain a

stable supply state (stable supply deﬁned as VCC, VCCQ,VREF,

and VTT are between their minimum and maximum values as

stated in DC Operating Conditionstable):

8. Issue a LOAD MODE command to the MR for DLL RESET. 200

A. (single power source) The VCC voltage ramp from 300mV to

VCC(MIN) must take no longer than 200ms; during the VCC

cycles of clock input is required to lock the DLL. To issue a DLL

RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;

CKE must be HIGH the entire time the DLL is resetting; remaining

MR bits must be “0.” See “Mode Register (MR)” on page 7 for all

MR requirements.

voltage ramp, |VCC - VCCQ| < 0.3V. Once supply voltage

ramping is complete (when VCCQ crosses VCC (MIN), DC

Operating Conditions table speciﬁcations apply.

• VCC, VCCQ are driven from a single power converter output

• VTT is limited to 0.95V MAX

• VREF tracks VCCQ/2; VREF must be within ±3V with respect

to VCCQ/2 during supply ramp time.

9. Issue PRECHARGE ALL command.

10. Issue two or more REFRESH commands.

11. Issue a LOAD MODE command to the MR with LOW to A8 to

initialize device operation (that is, to program operating parameters

without resetting the DLL). To access the MR, set BA0 and BA1

LOW; remaining MR bits must be set to desired settings. See

“Mode Register (MR)” on page 7 for all MR requirements.

12. Issue a LOAD MODE command to the EMR to enable OCD

default by setting bits E7, E8, and E9 to “1,” and then setting all

other desired parameters. To access the EMR, set BA0 LOW

and BA1 HIGH (see “Extended Mode Register (EMR)” on page 10

for all EMR requirements).

• VCCQ > VREF at all times

B. (multiple power sources) VCC e” VCCQ must be maintained

during supply voltage ramping, for both AC and DC levels, until

supply voltage ramping completes (VCCQ crosses VCC [MIN]).

Once supply voltage ramping is complete, DC Operating

Conditions table speciﬁcations apply.

• Apply VCC before or at the same time as VCCQ; VCC

voltage ramp time must be < 200ms from when VCC ramps from

300mV to VCC (MIN)

• Apply VCCQ before or at the same time as VTT; the VCCQ

voltage ramp time from when VCC (MIN) is achieved to when

VCCQ (MIN) is achieved must be < 500ms; while VCC is

ramping, current can be supplied from VCC through the device

to VCCQ

13. Issue a LOAD MODE command to the EMR to enable OCD exit by

setting bits E7, E8, and E9 to “0,” and then setting all other desired

parameters. To access the extended mode registers, EMR, set

BA0 LOW and BA1 HIGH for all EMR requirements.

14. The DDR2 SDRAM is now initialized and ready for normal

operation 200 clock cycles after the DLL RESET at Tf0.

15. DM represents UDM, LDM collectively for each die x16

conﬁguration. DQS represents UDQS, USQS, LDQS, LDQS for

each die x16 conﬁguration. DQ represents DQ0-DQ15 for each

• VREF must track VCCQ/2, VREF must be within ±0.3V with

respect to VCCQ/2 during supply ramp time; VCCQ > VREF

must be met at all times

• Apply VTT; The VTT voltage ramp time from when VCCQ

(MIN) is achieved to when VTT (MIN) is achieved must be no

greater than 500ms

die x16 conﬁguration.

2. CKE requires LVCMOS input levels prior to state T0 to ensure

DQs are High-Z during device power-up prior to VREF being

stable. After state T0, CKE is required to have SSTL_18 input

levels. Once CKE transitions to a high level, it must stay HIGH for

the duration of the initialization sequence.

16. Wait a minimum of 400ns then issue a PRECHARGE ALL

command.

3. A10 = PRECHARGE ALL, CODE = desired values for mode

registers (bank addresses are required to be decoded).

4. For a minimum of 200µs after stable power and clock (CK, CK#),

apply NOP or DESELECT commands, then take CKE HIGH.

5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2)

command, provide LOW to BA0, and provide HIGH to BA1; set

register E7 to “0” or “1” to select appropriate self refresh rate;

remaining EMR(2) bits must be “0” (see “Extended Mode Register

2 (EMR2)” on page 84 for all EMR(2) requirements).

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

6

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

MODE REGISTER (MR)

FIGURE 5 – MODE REGISTER (MR) DEFINITION

The mode register is used to deﬁne the speciﬁc mode of

operation of the DDR2 SDRAM. This deﬁnition includes the

selection of a burst length, burst type, CL, operating mode,

DLL RESET, write recovery, and power-down mode, as

shown in Figure 5. Contents of the mode register can be

altered by re-executing the LOAD MODE (LM) command. If

the user chooses to modify only a subset of the MR variables,

all variables (M0–M14) must be programmed when the

command is issued.

1

2

1

2

BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

16 15 14

n

12 11 10

PD WR

9

8

7

6

5

4

3

2

1

0

Mode Register (Mx)

1

0

MR

0

DLL TM CAS# Latency BT Burst Length

M2 M1 M0

Burst Length

Reserved

4

M12 PD Mode

Mode

Normal

Test

M7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fast exit

(normal)

1

Slow exit

(low power)

The mode register is programmed via the LM command

(bits BA2–BA0 = 0, 0,0) and other bits (M13–M0) will retain

the stored information until it is programmed again or the

device loses power (except for bit M8, which is selfclearing).

Reprogramming the mode register will not alter the contents

of the memory array, provided it is performed correctly.

8

DLL Reset

No

M8

0

Reserved

1

Yes

Write Recovery

M11 M10 M9

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

Burst Type

Sequential

Interleaved

M3

0

The LM command can only be issued (or reissued) when all

banks are in the precharged state (idle state) and no bursts

are in progress. The controller must wait the speciﬁed time

tMRD before initiating any subsequent operations such as

an ACTIVE command. Violating either of these requirements

will result in unspeciﬁed operation.

1

CAS Latency (CL)

M6 M5 M4

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

M15 M16

Mode Register Definition

Mode register (MR)

3

4

5

6

7

BURST LENGTH

0

1

0

1

0

1

Burst length is deﬁned by bits M0–M3, as shown in Figure

5. Read and write accesses to the DDR2 SDRAM are burst-

oriented, with the burst length being programmable to either

four or eight. The burst length determines the maximum

number of column locations that can be accessed for a given

READ or WRITE command.

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

Notes:

1.A13 Not used on this part, and must be programmed to ‘0’ on

this part.

2.BA2 must be programmed to “0” and is reserved for future use.

When a READ or WRITE command is issued, a block of

columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning

that the burst will wrap within the block if a boundary is reached.

The block is uniquely selected by A2–Ai when BL = 4 and by

A3–Ai when BL = 8 (where Ai is the most signiﬁcant column

address bit for a given conﬁguration). The remaining (least

signiﬁcant) address bit(s) is (are) used to select the starting

location within the block. The programmed burst length applies

to both READ and WRITE bursts.

BURST TYPE

Accesses within a given burst may be programmed to be

either sequential or interleaved. The burst type is selected

via bit M3, as shown in Figure 5. The ordering of accesses

within a burst is determined by the burst length, the burst

type, and the starting column address, as shown in Table

2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst

mode only. For 8-bit burst mode, full interleave address

ordering is supported; however, sequential address ordering

is nibble-based.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

7

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

TABLE 2 - BURST DEFINITION

DLL RESET

Order of Accesses Within a Burst

Burst

Length

Starting Column

Address

DLL RESET is deﬁned by bit M8, as shown in Figure 5.

Programming bit M8 to “1” will activate the DLL RESET

function. Bit M8 is self-clearing, meaning it returns back

to a value of “0” after the DLL RESET function has been

issued.

Type = Sequential

Type = Interleaved

A1 A0

0

1

0

1

0

1

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

4

Anytime the DLL RESET function is used, 200 clock cycles

must occur before a READ command can be issued to allow

time for the internal clock to be synchronized with the external

clock. Failing to wait for synchronization to occur may result in

A2 A1 A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

t

a violation of the AC or DQSCK parameters.

8

WRITE RECOVERY

Write recovery (WR) time is deﬁned by bits M9-M11, as shown

in Figure 5. The WR register is used by the DDR2 SDRAM

during WRITE with auto precharge operation. During WRITE

with auto precharge operation, the DDR2 SDRAM delays the

internal auto precharge operation by WR clocks (programmed

in bits M9-M11) from the last data burst.

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block;

A0 selects the starting column within the block.

2. For a burst length of four, A2-Ai select four-data-element block;

A0-1 select the starting column within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block;

A0-2 select the starting column within the block.

4. Whenever a boundary of the block is reached within a given

sequence above, the following access wraps within the block.

WR values of 2, 3, 4, 5, 6 or 7 clocks may be used for

programming bits M9-M11. The user is required to program

the value of WR, which is calculated by dividing ^tWR (in ns)

by tCK (in ns) and rounding up a non integer value to the next

integer; WR [cycles] = WR [ns] / CK [ns]. Reserved states

should not be used as unknown operation or incompatibility

with future versions may result.

t

OPERATING MODE

The normal operating mode is selected by issuing a

command with bit M7 set to “0” and all other bits set to

the desired values, as shown in Figure 5. When bit M7 is

“1,” no other bits of the mode register are programmed.

Programming bit M7 to “1” places the DDR2 SDRAM into a

test mode that is only used by the manufacturer and should

not be used. No operation or functionality is guaranteed

if M7 bit is “1.”

POWER-DOWN MODE

Active power-down (PD) mode is defined by bit M12,

as shown in Figure 5. PD mode allows the user to

determine the active power-down mode, which determines

performance versus power savings. PD mode bit M12 does

not apply to precharge PD mode.

When bit M12 = 0, standard active PD mode or “fast-exit”

active PD mode is enabled. The XARD parameter is used

t

for fast-exit active PD exit timing. The DLL is expected to be

enabled and running during this mode.

When bit M12 = 1, a lower-power active PD mode or “slowexit”

t

active PD mode is enabled. The XARD parameter is used

for slow-exit active PD exit timing. The DLL can be enabled,

but “frozen” during active PD mode since the exit-to-READ

command timing is relaxed. The power difference expected

between PD normal and PD low-power mode is deﬁned in

the I^CCtable.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

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iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

CAS LATENCY (CL)

The CAS latency (CL) is deﬁned by bits M4-M6, as shown

in Figure 5. CL is the delay, in clock cycles, between the

registration of a READ command and the availability of the ﬁrst

bit of output data. The CL can be set to 3, 4, 5, 6 or 7 clocks,

depending on the speed grade option being used.

DDR2 SDRAM also supports a feature called posted CAS

additive latency (AL). This feature allows the READ command

to be issued prior to tRCD (MIN) by delaying the

internal command to the DDR2 SDRAM by AL clocks.

Examples of CL = 3 and CL = 4 are shown in Figure 6; both

assume AL = 0. If a READ command is registered at clock

edge n, and the CL is m clocks, the data will be available

nominally coincident with clock edge n+m (this assumes

AL = 0).

DDR2 SDRAM does not support any half-clock latencies.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

FIGURE 6 - CAS LATENCY (CL)

T0

T1

T2

T3

T4

T5

T6

CK#

CK

READ

NOP

Command

DQS, DQS#

DO

DQ

n

n + 1

n + 2

n + 3

CL = 3 (AL = 0)

T0

T1

T2

T3

T4

T5

T6

CK#

CK

READ

NOP

Command

DQS, DQS#

DO

DQ

n

n + 1

n + 2

n + 3

CL = 4 (AL = 0)

Transitioning data

Don’t care

Notes: 1. BL = 4.

2. Posted CAS# additive latency (AL) = 0.

t

3. Shown with nominal AC, DQSCK, and DQSQ.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

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4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

EXTENDED MODE REGISTER (EMR)

until it is programmed again or the device loses power.

Reprogramming the EMR will not alter the contents of the memory

array, provided it is performed correctly.

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are

DLL enable/disable, output drive strength, on die termination

(ODT) (RTT), postedAL, off-chip driver impedance calibration

(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,

andoutputdisable/enable.Thesefunctionsarecontrolledviathe

bits shown in Figure 7. The EMR is programmed via the LOAD

MODE (LM) command and will retain the stored information

The EMR must be loaded when all banks are idle and no bursts

are in progress, and the controller must wait the speciﬁed time

tMRD before initiating any subsequent operation. Violating either

of these requirements could esult in unspeciﬁed operation.

FIGURE 7 – EXTENDED MODE REGISTER DEFINITION

1

2

3

BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode

16 15 14

n

12 11 10

Out

9

8

7

6

5

4

3

2

1

0

register (Ex)

2

0

MRS

RTT

Posted CAS#

0

OCD Program

R

^TTODS DLL

RDQS DQS#

Outputs

Enabled

Disabled

E0

0

DLL Enable

E12

0

E6 E2

R

TT (Nominal)

Enable (normal)

Disable (test/debug)

1

0

1

0

1

0

1

R^TTdisabled

75Ω

150Ω

50Ω

E11 RDQS Enable

E1

0

Output Drive Strength

0

1

No

Full

(100%)

(40-60%)

Reduced

Yes

1

4

E10 DQS# Enable

Posted CAS# Additive Latency (AL)

E5 E4 E3

0

1

Enable

Disable

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

E9 E8 E7 OCD Operation

3

0

1

0

1

0

1

0

1

0

1

OCD exit

Reserved

4

5

6

Reserved

Enable OCD defaults

Mode Register Set

E15 E14

0

1

0

1

Mode register (MR)

0

1

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

Notes:

1.During initialization, all three bits must be set to “1” for OCD default state, then must be set to “0” before

initialization is ﬁnished, as detailed in the initialization procedure.

2.E13 (A13) must be programmed to “0” and is reserved for future use.

3.E16 must be programmed to “0” and is reserved for future use.

4.Not all AL options are supported in any individual speed grade.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

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4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

OUTPUT ENABLE/DISABLE

DLL ENABLE/DISABLE

The OUTPUT ENABLE function is deﬁned by bit E12, as shown

in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS,

DQS#, RDQS, RDQS#) function normally. When disabled (E12

= 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS,

RDQS#) are disabled, thus removing output buffer current.

The output disable feature is intended to be used during I^CC

characterization of read current.

The DLL may be enabled or disabled by programming bit

E0 during the LM command, as shown in Figure 7. The DLL

must be enabled for normal operation. DLL enable is required

during power-up initialization and upon returning to normal

operation after having disabled the DLL for the purpose of

debugging or evaluation. Enabling the DLL should always be

followed by resetting the DLL using an LM command.

The DLL is automatically disabled when entering SELF

REFRESH operation and is automatically re-enabled and reset

upon exit of SELF REFRESH operation. Any time the DLL is

enabled (and subsequently reset), 200 clock cycles must occur

before a READ command can be issued, to allow time for the

internal clock to synchronize with the external clock. Failing to

wait for synchronization to occur may result in a violation of

ON-DIE TERMINATION (ODT)

ODT effective resistance, RTT (EFF), is deﬁned by bits E2

and E6 of the EMR, as shown in Figure 7. The ODT feature

is designed to improve signal integrity of the memory channel

by allowing the DDR2 SDRAM controller to independently

turn on/off ODT for any or all devices. R^TTeffective resistance

values of 50Ω, 75Ω, and 150Ω are selectable and apply

to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#,

LDQS/LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2)

determine what ODT resistance is enabled by turning on/off

“sw1,” “sw2,” or “sw3.” The ODT effective resistance value is

elected by enabling switch “sw1,” which enables all R1 values

that are 150Ω each, enabling an effective resistance of 75Ω

(R^TT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values

that are 300Ω each, enable an effective ODT resistance of

150Ω (R^TT2(EFF) = R2/2). Switch “sw3” enables R1 values

of 100Ω enabling effective resistance of 50Ω Reserved states

should not be used, as unknown operation or incompatibility

with future versions may result.

t

the AC or DQSCK parameters.

OUTPUT DRIVE STRENGTH

The output drive strength is deﬁned by bit E1, as shown

in Figure 7. The normal drive strength for all outputs are

speciﬁed to be SSTL_18. Programming bit E1 = 0 selects

normal (full strength) drive strength for all outputs. Selecting

a reduced drive strength option (E1 = 1) will reduce all outputs

to approximately 45-60 percent of the SSTL_18 drive strength.

This option is intended for the support of lighter load and/or

point-to-point environments.

DQS# ENABLE/DISABLE

The ODT control ball is used to determine when R^TT(EFF)

is turned on and off, assuming ODT has been enabled via

bits E2 and E6 of the EMR. The ODT feature and ODT input

ball are only used during active, active power-down (both

fast-exit and slow-exit modes), and precharge powerdown

modes of operation. ODT must be turned off prior to entering

self refresh. During power-up and initialization of the DDR2

SDRAM, ODT should be disabled until issuing the EMR

command to enable the ODT feature, at which point the ODT

ball will determine the RTT(EFF) value. Any time the EMR

enables the ODT function, ODT may not be driven HIGH until

eight clocks after the EMR has been enabled. See “ODTTiming”

section for ODT timing diagrams.

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is

the complement of the differential data strobe pair DQS/DQS#.

When disabled (E10 = 1), DQS is used in a single ended mode

and the DQS# ball is disabled. When disabled, DQS# should

be left ﬂoating. This function is also used to enable/disable

RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled

(E10 = 0), then both DQS# and RDQS# will be enabled.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

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4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

POSTED CAS ADDITIVE LATENCY (AL)

Posted CAS additive latency (AL) is supported to make the

command and data bus efﬁcient for sustainable bandwidths in

DDR2 SDRAM. Bits E3–E5 deﬁne the value of AL, as shown

in Figure 7. Bits E3–E5 allow the user to program the DDR2

SDRAM with an inverse AL of 0, 1, 2, 3, 4, 5 or 6 clocks.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE

command to be issued prior to ^tRCD (MIN) with the requirement

that AL = ^tRCD (MIN). A typical application using this feature

would set AL = tRCD (MIN) - 1x _CK. The READ or WRITE

t

command is held for the time of theALbefore it is issued internally

to the DDR2 SDRAM device. RL is controlled by the sum of AL

and CL; RL = AL+CL. Write latency (WL) is equal to RL minus

one clock; WL = AL + CL - 1 x ^t

.

CK

FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION

1

2

1

BA2

BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address bus

Extended mode

register (Ex)

16 15 14

n

12 11 10

9

8

7

6

5

4

3

0

2

0

1

0

SRT 0

MRS

0

E7

0

SRT Enable

E15 E14

Mode Register Set

1X refresh rate (0°C to 85°C)

2X refresh rate (>85°C)

0

1

0

1

0

1

Mode register (MR)

1

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

Notes:

1.E16 bit (BA2) must be programmed to “0” and is reserved for future use.

2.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “0.”

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

12

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION

₂1

BA2

₁2

BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode

16 15 14

MRS

n

12 11 10

9

8

7

6

5

4

3

2

1

0

register (Ex)

0

E15 E14

Mode Register Set

0

1

0

1

0

1

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

Notes:

1.Mode bits (En) with corresponding address balls (An) greater than A12 are reserved for future use and must be programmed to “0.”

2.E16 (BA2) must be programmed to “0” on this device and is reserved for future use.

EXTENDED MODE REGISTER 2

The extended mode register 2 (EMR2) controls functions

beyond those controlled by the mode register. Currently all

bits in EMR2 are reserved, as shown in Figure 8. The EMR2

EMR3 must be loaded when all banks are idle and no bursts

are in progress, and the controller must wait the speciﬁ ed time

tMRD before initiating any subsequent operation. Violating

is programmed via the LM command and will retain the stored

either of these requirements could result in unspecified

information until it is programmed again or the device loses

operation.

power. Reprogramming the EMR will not alter the contents of

the memory array, provided it is performed correctly.

COMMAND TRUTH TABLES

The following tables provide a quick reference of DDR2 SDRAM

EMR2 must be loaded when all banks are idle and no bursts are

in progress, and the controller must wait the speciﬁed time ^tMRD

before initiating any subsequent operation. Violating either of

available commands, including CKE power-down modes, and

bank-to-bank commands.

these requirements could result in unspeciﬁed operation.

EXTENDED MODE REGISTER 3

The extended mode register 3 (EMR3) controls functions

beyond those controlled by the mode register. Currently, all

bits in EMR3 are reserved, as shown in Figure 9. The EMR3

is programmed via the LM command and will retain the stored

information until it is programmed again or the device loses

power. Reprogramming the EMR will not alter the contents of

the memory array, provided it is performed correctly.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

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4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

TABLE 3 - TRUTH TABLE - DDR2 COMMANDS

CKE

BA2 thru

Function

CS#

RAS#

CAS#

WE#

A10

A9-A0

Notes

Previous Current

A12

A11

Cycle

BA0

OP CODE

LOAD MODE

H

L

H

L

X

H

L

H

X

H

L

BA

2

REFRESH

X

SELF-REFRESH Entry

L

X

H

SELF-REFRESH exit

L

H

X

7

2

Single Bank Precharge

All banks PRECHARGE

Bank Activate

H

X

L

X

L

H

ROW ADDRESS

L

BA

Column

Address

Column

Address

Column

Address

Column

Address

Column

Address

Column

Address

Column

Address

Column

Address

WRITE

H

L

H

L

BA

L

H

L

2,3

WRITE with auto precharge

READ

H

READ with auto precharge

L

NO OPERATION

H

X

L

H

L

H

X

H

X

H

X

H

X

H

X

H

X

H

X

Device DESELECT

POWER-DOWN entry

POWER-DOWN exit

H

L

X

4

H

L

H

Note: 1. All DDR2-SDRAM commands are deﬁned by staes of CS#, RAS#, CAS#, WE#, and CKE a the

rising edge of the clock.

2. Bank addresses (BA) BA2-BA0 determine which bank is to be operated upon. BA during a LM

command selects which mode register is programmed.

3. Burst reads or writes at BL=4 cannot be terminated or interrupted.

4. The power down mode does not perform any REFRESH operations. The duration of power down

is therefore limited by the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not effect the states described in this table. The ODT function is not available

during self refresh. See “On Die Termination (ODT)” for details.

6. “X” means “H or L” (but a deﬁned logic level)

7. Self refresh exit is asynchronous.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

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DESELECT

The DESELECT function (CS# HIGH) prevents new commands

from being executed by the DDR2 SDRAM. The DDR2 SDRAM

is effectively deselected. Operations already in progress are

not affected.

A subsequent ACTIVE command to a different row in the

same bank can only be issued after the previous active row

has been closed (precharged). The minimum time interval

between successive ACTIVE commands to the same bank is

deﬁned by ^tRC

NO OPERATION (NOP)

A subsequent ACTIVE command to another bank can be

issued while the ﬁrst bank is being accessed, which results in

a reduction of total row-access overhead. The minimum time

interval between successive ACTIVE commands to different

banks is deﬁned by ^tRRD.

The NO OPERATION (NOP) command is used to instruct the

selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,

CAS#, and WE are HIGH). This prevents unwanted commands

from being registered during idle or wait states. Operations

already in progress are not affected.

LOAD MODE (LM)

The mode registers are loaded via inputs BA2–BA0, and

A12–A0. BA2–BA0 determine which mode register will be

programmed. See “Mode Register (MR)”. The LM command

can only be issued when all banks are idle, and a subsequent

execute able command cannot be issued until ^tMRD is met.

FIGURE 10 - ACTIVE COMMAND

CK#

CK

BANK/ROW ACTIVATION

ACTIVE COMMAND

The ACTIVE command is used to open (or activate) a row in

a particular bank for a subsequent access. The value on the

BA2–BA0 inputs selects the bank, and the address provided

on inputs A12–A0 selects the row. This row remains active (or

open) for accesses until a PRECHARGE command is issued

to that bank.APRECHARGE command must be issued before

opening a different row in the same bank.

CKE

CS#

RAS#

CAS#

WE#

ACTIVE OPERATION

Before any READ or WRITE commands can be issued to a

bank within the DDR2 SDRAM, a row in that bank must be

opened (activated), even when additive latency is used. This

is accomplished via theACTIVE command, which selects both

the bank and the row to be activated.

Row

ADDRESS

After a row is opened with an ACTIVE command, a READ or

WRITE command may be issued to that row, subject to the

tRCD speciﬁcation. tRCD (MIN) should be divided by the clock

period and rounded up to the next whole number to determine

the earliest clock edge after the ACTIVE command on which

a READ or WRITE command can be entered. The same

procedure is used to convert other speciﬁcation limits from time

units to clock cycles. For example, a tRCD (MIN) speciﬁcation

of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3

clocks, rounded up to 6.

BANK ADDRESS

Bank

DON’T CARE

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AS4DDR264M72PBG & MYXDDR264M72

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AS4DDR264M72PBG & MYXDDR264M72

READ COMMAND

The READ command is used to initiate a burst read access

to an active row. The value on the BA2–BA0 inputs selects

the bank, and the address provided on inputs A0–i (where

i = A9) selects the starting column location. The value on

input A10 determines whether or not auto precharge is used.

If auto precharge is selected, the row being accessed will be

precharged at the end of the READ burst; if auto precharge

is not selected, the row will remain open for subsequent

accesses.

FIGURE 11 - READ COMMAND

READ OPERATION

READ bursts are initiated with a READ command. The starting

column and bank addresses are provided with the READ

command and auto precharge is either enabled or disabled for

that burst access. If auto precharge is enabled, the row being

accessed is automatically precharged at the completion of the

burst. If auto precharge is disabled, the row will be left open

after the completion of the burst.

CK#

CK

CKE

CS#

During READ bursts, the valid data-out element from the

starting column address will be available READ latency (RL)

clocks later. RL is deﬁned as the sum of AL and CL; RL = AL

+ CL. The value for AL and CL are programmable via the MR

and EMR commands, respectively. Each subsequent data-out

element will be valid nominally at the next positive or negative

clock edge (i.e., at the next crossing of CK and CK#).

RAS#

CAS#

WE#

DQS/DQS# is driven by the DDR2 SDRAM along with output

data. The initial LOW state on DQS and HIGH state on DQS#

is known as the read preamble (^tRPRE). The LOW state on

DQS and HIGH state on DQS# coincident with the last data-out

element is known as the read postamble (^tRPST).

ADDRESS

Col

ENABLE

A10

AUTO PRECHARGE

DISABLE

Upon completion of a burst, assuming no other commands

have been initiated, the DQ will go High-Z.

BANK ADDRESS

Bank

DON’T CARE

Data from any READ burst may be concatenated with data from

a subsequent READ command to provide a continuous ﬂow

of data. The ﬁrst data element from the new burst follows the

last element of a completed burst. The new READ command

should be issued x cycles after the ﬁrst READ command, where

x equals BL / 2 cycles.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

16

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

WRITE COMMAND

The WRITE command is used to initiate a burst write access

to an active row. The value on the BA2–BA0 inputs selects the

bank, and the address provided on inputs A0–9 selects the

starting column location. The value on input A10 determines

whether or not auto precharge is used. If auto precharge is

selected, the row being accessed will be precharged at the

end of the WRITE burst; if auto precharge is not selected, the

row will remain open for subsequent accesses.

The time between the WRITE command and the ﬁ rst rising

DQS edge is WL ± ^t_DQSS. Subsequent DQS positive rising

edges are timed, relative to the associated clock edge, as ±

tDQSS. tDQSS is speciﬁed with a relatively wide range (25

percent of one clock cycle). All of the WRITE diagrams show

the nominal case, and where the two extreme cases (^tDQSS

[MIN] and ^tDQSS [MAX]) might not be intuitive, they have also

been included. Upon completion of a burst, assuming no other

commands have been initiated, the DQ will remain High-Z and

any additional input data will be ignored.

Input data appearing on the DQ is written to the memory array

subject to the DM input logic level appearing coincident with the

data. If a given DM signal is registered LOW, the corresponding

data will be written to memory; if the DM signal is registered

HIGH, the corresponding data inputs will be ignored, and a

WRITE will not be executed to that byte/column location.

Data for any WRITE burst may be concatenated with a

subsequent WRITE command to provide continuous ﬂow of

input data. The ﬁ rst data element from the new burst is applied

after the last element of a completed burst. The new WRITE

command should be issued x cycles after the ﬁrst WRITE

command, where x equals BL/2.

WRITE OPERATION

WRITE bursts are initiated with a WRITE command, as shown

in Figure 12. DDR2 SDRAM uses WL equal to RL minus one

clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting

column and bank addresses are provided with the WRITE

command, and auto precharge is either enabled or disabled

for that access. If auto precharge is enabled, the row being

accessed is precharged at the completion of the burst. For the

generic WRITE commands used in the following illustrations,

auto precharge is disabled.

DDR2 SDRAM supports concurrent auto precharge options,

as shown in Table 4.

DDR2 SDRAM does not allow interrupting or truncating any

WRITE burst using BL = 4 operation. Once the BL = 4 WRITE

command is registered, it must be allowed to complete the

entire WRITE burst cycle. However, a WRITE (with auto

precharge disabled) using BL= 8 operation might be interrupted

and truncated ONLY by another WRITE burst as long as the

interruption occurs on a 4-bit boundary, due to the 4n prefetch

architecture of DDR2 SDRAM. WRITE burst BL = 8 operations

may not to be interrupted or truncated with any command

except another WRITE command.

During WRITE bursts, the ﬁrst valid data-in element will be

registered on the ﬁrst rising edge of DQS following the WRITE

command, and subsequent data elements will be registered on

successive edges of DQS. The LOW state on DQS between

the WRITE command and the ﬁrst rising edge is known as the

write preamble; the LOW state on DQS following the last data-in

element is known as the write postamble.

Data for any WRITE burst may be followed by a subsequent

READ command. The number of clock cycles required to meet

tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any

WRITE burst may be followed by a subsequent PRECHARGE

command. ^tWT starts at the end of the data burst, regardless

of the data mask condition.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

17

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

FIGURE 12 - WRITE COMMAND

CK#

CK

CKE

CS#

HIGH

RAS#

CAS#

WE#

ADDRESS

A10

CA

EN AP

DIS AP

BANK ADDRESS

BA

DON’T CARE

Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and

DIS AP = disable auto precharge.

TABLE 4 - WRITE USING CONCURRENT AUTO PRECHARGE

Minimum Delay (With Concurrent

From Command (Bank n )

To Command (Bank m )

Units

Auto Precharge)

(CL-1) + (BL/2) + ^tWTR

^tCK

READ OR READ w/ AP

WRITE OR WRITE w/ AP

PRECHARGE or ACTIVE

WRITE with Auto Precharge

(BL/2)

1

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

18

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

PRECHARGE COMMAND

FIGURE 13 – PRECHARGE COMMAND

The PRECHARGE command, illustrated in Figure 13, is used

to deactivate the open row in a particular bank or the open

row in all banks. The bank(s) will be available for a subsequent

row activation a speciﬁed time (tRP) after the PRECHARGE

command is issued, except in the case of concurrent auto

precharge, where a READ or WRITE command to a different

bank is allowed as long as it does not interrupt the data

transfer in the current bank and does not violate any other

timing parameters. Once a bank has been precharged, it is

in the idle state and must be activated prior to any READ or

WRITE commands being issued to that bank. APRECHARGE

command is allowed if there is no open row in that bank (idle

state) or if the previously open row is already in the process of

precharging. However, the precharge period will be determined

by the last PRECHARGE command issued to the bank.

CK#

CK

CKE

HIGH

CS#

RAS#

CAS#

WE#

PRECHARGE OPERATION

Input A10 determines whether one or all banks are to be

precharged, and in the case where only one bank is to be

precharged, inputs BA2–BA0 select the bank. Otherwise

BA2–BA0 are treated as “Don’t Care.” When all banks are to

be precharged, inputs BA2–BA0 are treated as “Don’t Care.”

ADDRESS

ALL BANKS

A10

ONE BANK

Once a bank has been precharged, it is in the idle state and

must be activated prior to any READ or WRITE commands

being issued to that bank. ^tRPA timing applies when the

PRECHARGE (ALL) command is issued, regardless of the

number of banks already open or closed. If a single-bank

PRECHARGE command is issued, ^tRP timing applies.

-

BA2, BA0

BA

DON’T CARE

Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").

issued). The differential clock should remain stable and meet tCKE

speciﬁcations at least 1 x ^tCK after entering self refresh mode. All

command and address input signals except CKE are “Don’t Care”

during self refresh.

SELF REFRESH COMMAND

The SELF REFRESH command can be used to retain data in

the DDR2 SDRAM, even if the rest of the system is powered

down. When in the self refresh mode, the DDR2 SDRAM

retains data without external clocking. All power supply inputs

(including V^REF) must be maintained at valid levels upon entry/

exit and during SELF REFRESH operation.

The procedure for exiting self refresh requires a sequence of

commands. First, the differential clock must be stable and meet

tCK speciﬁcations at least 1 x tCK prior to CKE going back HIGH.

Once CKE is HIGH (tCLE(MIN) has been satisﬁed with four clock

registrations), the DDR2 SDRAM must have NOP or DESELECT

commands issued for tXSNR because time is required for the

completion of any internal refresh in progress. A simple algorithm

for meeting both refresh and DLL requirements is to apply NOP

or DESELECT commands for 200 clock cycles before applying

any other command.

The SELF REFRESH command is initiated like a

REFRESH command except CKE is LOW. The DLL is

automatically disabled upon entering self refresh and is

automatically enabled upon exiting self refresh (200 clock

cycles must then occur before a READ command can be

Note: Self refresh not available at military temperature.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

19

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

RESET FUNCTION

(CKE LOW Anytime)

DDR2 SDRAM applications may go into a reset state anytime

during normal operation. If an application enters a reset

condition, CKE is used to ensure the DDR2 SDRAM device

resumes normal operation after reinitializing. All data will be

lost during a reset condition; however, the DDR2 SDRAM

device will continue to operate properly if the following

conditions outlined in this section are satisﬁed.

If CKE asynchronously drops LOW during any valid operation

(including a READ or WRITE burst), the memory controller

must satisfy the timing parameter tDELAY before turning off

the clocks. Stable clocks must exist at the CK, CK# inputs

of the DRAM before CKE is raised HIGH, at which time the

normal initialization sequence must occur. The DDR2 SDRAM

device is now ready for normal operation after the initialization

sequence.

The reset condition deﬁned here assumes all supply voltages

(V_DD, V_DDQand V_REF) are stable and meet all DC speciﬁcations

prior to, during, and after the RESET operation. All other

input pins of the DDR2 SDRAM device are a “Don’t Care”

during RESET with the exception of CKE.

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

20

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

DC OPERATING CONDITIONS

All Voltages referenced to Vss

Parameter

Supply Voltage

Symbol

MIN

TYP

1.8

MAX

1.9

Units

Notes

V_CC

1.7

V

1

4

2

3

V_CCQ

V_REF

V_TT

I/O Supply Voltage

1.7

1.8

1.9

I/O Reference Voltage

I/O Termination Voltage

0.49 x V_CCQ

V_REF- 0.04

0.50 x V_CCQ

V_REF

0.51 x V_CCQ

V_REF+ 0.04

Notes:

1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC.

2. V^REFis expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 1 percent of the DC value. Peak-to-

peak AC noise on V^REFmay not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.

4. V^CCQtracks with VCC track with VCC.

ABSOLUTE MAXIMUM RATINGS

Symbol

V_CC

Parameter

Voltage on V_CCpin relative to V_SS

Voltage on VCCQ pin relative to V

Min

-1.0

Max

2.3

Unit

V

V_CCQ

-0.5

2.3

V

SS

V_IN, V_OUT

T_STG

Voltage on any pin relative to V

-0.5

2.3

V

SS

^oC

Storage Temperature

-55.0

125.0

T_CASE

Device Operating Temperature

ADDR, BAx

-10.0

10.0

uA

RAS\, CAS\, WE\, CS\,

CKE, DM, DQS, DQS\,

RDQS

-5

5

Input Leakage current; Any input 0V<V <V_CC;

.5XVCCQ; Other balls not under test = 0V

V_REF=

IN

I_I

CK, CK\

DM

-5

5

uA

OV ≤ VOUT ≤ VDDQ, DQ & ODT Disabled

I_OZ

I_VREF

-5

5

uA

V_REFLeakage Current

-10

10

INPUT / OUTPUT CAPACITANCE

T_A= 25^oC, f = 1 MHz, V_CC= V_CCQ= 1.8V

Parameter

Symbol

C_ADDR

Max

28

10

8

Unit

pF

Input capacitance (A0-A12, BA2-BA0)

Input capacitance (CS#, RAS#, CAS#, WE#, CKE, ODT)

Input capacitance CK, CK#

C_IN1

C_IN2

C_IN3

C_OUT

pF

Input capacitance DM, DQS, DQS#

Input capacitance DQ0-71

10

12

pF

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

21

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

INPUT DC LOGIC LEVEL

All voltages referenced to Vss

Parameter

Symbol

V_IH(DC)

Min

V_REF+ 0.125

Max

V_CCQ

Unit

1

Input High (Logic 1) Voltage

V

V_IL(DC)

V_REF- 0.125

Input Low (Logic 0) Voltage

-0.300

V

Note 1: VCCQ + 300mV allowed provided 1.9V is not exceeded

INPUT AC LOGIC LEVEL

All voltages referenced to Vss

Parameter

Symbol

Min

V_REF+ 0.250

Max

Unit

1

V

_IH(AC)

V_CCQ

AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533

V

1

V

V_REF+ 0.200

-0.3

V_CCQ

AC Input High (Logic 1) Voltage DDR2-667

ACInput Low (Logic 0) Voltage DDR2-400 & DDR2-533

AC Input Low (Logic 0) Voltage DDR2-667

V

V_IL(AC)

V_REF- 0.250

V_REF- 0.200

-0.3

Note 1: VCCQ + 300mV allowed provided 1.9V is not exceeded

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

22

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

DDRII ICC SPECIFICATIONS AND CONDITIONS

667 MHZ

-3

533 MHZ

-38

400 MHZ

-5

Parameter

Symbol

Units

Operating Current: One bank active-precharge

tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is

HIGH, CS\ is HIGH between valid commands; Address bus

switching, Data bus switching

ICC0

600

750

35

550

650

35

500

600

35

mA

Operating Current: One bank active-READ-precharge

current

IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRC-

tRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is

HIGH, CS\ is HIGH between valid commands; Address bus is

switching; Data bus is switching

ICC1

ICC2P

ICC2Q

ICC2N

ICC3P

mA

Precharge POWER-DOWN current

All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and

address bus inputs are stable; Data bus inputs are floating

Precharge quiet STANDBY current

All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH;

Other control and address bus inputs are stable; Data bus

inputs are floating

275

300

225

250

175

200

Precharge STANDBY current

All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH;

Other control and address bus inputs are switching; Data bus

inputs are switching

Active POWER-DOWN current

MRS[12]=0

150

50

125

50

115

50

All banks open; tCK=tCK(ICC); CKE is LOW;

Other control and address inputs are stable; Data

MRS[12]=1

bus inputs are floating

Active STANDBY current

All banks open; tCK=tCK(ICC), tRAS MAX(ICC),

tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are

switching; Data bus inputs are switching

ICC3N

ICC4W

300

850

250

700

200

600

mA

Operating Burst WRITE current

All banks open, continuous burst writes; BL=4, CL=CL(ICC),

tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid

commands; Address bus inputs are switching; Data bus

Operating Burst READ current

All banks open, continuous burst READS, Iout=0mA; BL=4,

CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC),

tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid

commands; Address and Data bus inputs switching

ICC4R

850

700

600

mA

Burst REFRESH current

tCK=tCK(ICC); refresh command at every iRFC(ICC) interval;

CKE is HIGH, CS\ is HIGH Between valid commands;

Address bus inputs are switching; Data bus inputs are

switching

ICC5

ICC6

1100

35

1000

35

900

35

mA

Self REFRESH current

CK and CK\ at 0V; CKE </=0.2V; Other contro, address and

data inputs are floating

Operating bank Interleave READ current:

All bank interleaving READS, IOUT = 0mA; BL=4,

CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC),

tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\ is HIGH

between valid commands; Address bus inputs are stable

during deselects; Data bus inputs are switching

ICC7

1500

1400

1300

mA

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

23

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

AC OPERATING SPECIFICATIONS

-3

-38

-5

333MHz/667Mbps 266MHz/533Mbps 200MHz/400Mbps

Parameter

Symbol

tCK_AVG

tCH_AVG

tCL_AVG

MIN

3

MAX

8

MIN

MAX

MIN

MAX

Units

ns

Clock Cycle Time

Clock High Time

CL=5

CL=4

CL=3

3.75

5

8

3.75

5

8

5

8

ns

8

ns

0.48

0.52

0.48

0.52

0.48

0.52

tCK

Clock Low Time

0.48

tCH,tCL

-125

0.48

tCH,tCL

-125

0.48

tCH,tCL

-125

tCK

ps

Half Clock Period

Clock Jitter - Period

Min of

tHP

tJIT_PER

125

150

ps

tJIT _DUTY

tJIT_CC

Clock Jitter - Half Period

-125

-150

ps

Clock Jitter - Cycle to Cycle

250

tERR_2PER

tERR_4PER

tERR_10PER

tERR_50PER

Cumulative Jitter error, 2 Cycles

Cumulative Jitter error, 4 Cycles

Cumulative Jitter error, 6-10 Cycles

Cumulative Jitter error, 11-50 Cycles

-175

-250

-350

-450

175

250

350

450

-175

-250

-350

-450

175

250

350

450

-175

-250

-350

-450

175

250

350

450

DQ hold skew factor

tQHS

tAC

tHZ

-

340

450

-

400

500

-

450

600

ps

DQ output access time from CK/CK\

Data-out High-Z window from CK/CK\

DQS Low-Z window from CL/CK\

-450

-500

-600

tAC(MAX)

tLZ₁

tAC(MIN)

tAC(MAX)

tAC(MIN)

tAC(MAX)

tAC(MIN)

tAC(MAX)

tLZ₂

DQ Low-Z window from CK/CK\

2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX) 2*tAC(MIN) tAC(MAX)

ps

tDS_JEDEC

tDH_JEDEC

DQ and DM input setup time relative to DQS

DQ and DM input hold time relative to DQS

100

175

0.35

100

225

0.35

150

275

0.35

DQ and DM input pulse width (for each input)

Data Hold skew factor

DQ-DQS Hold, DQS to first DQ to go non valid, per access

Data valid output window (DVW)

DQS input-high pulse width

DQS input-low pulse width

DQS output access time from CK/CK\

DQS falling edge to CK rising - setup time

DQS falling edge from CK rising-hold time

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQS READ preamble

DQS READ postamble

WRITE preamble setup time

DQS WRITE preamble

DQS WRITE postamble

Positive DQS latching edge to associated Clock edge

WRITE command to first DQS latching transition

tDIPW

tQHS

tQH

tCK

ps

340

400

450

tHP-tQHS

tQH-tDQSQ

0.35

-400

tHP-tQHS

tQH-tDQSQ

0.35

-400

tHP-tQHS

tQH-tDQSQ

0.35

-450

tDVW

ps

tDQSH

tDQSL

tDQSCK

tDSS

tCK

ps

tCK

ps

tCK

ps

tCK

0.2

tDSH

0.2

tDQSQ

tRPRE

tRPST

tWPRES

tWPRE

tWPST

tDQSS

240

1.1

0.6

300

1.1

0.6

350

1.1

0.6

0.9

0.4

0.9

0.4

0.9

0.4

0

0.35

0.4

0.35

0.4

0.35

0.4

0.6

-0.25

0.25

-0.25

0.25

-0.25

0.25

WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

24

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

AC OPERATING SPECIFICATIONS (CONTINUED)

-3

-38

-5

333MHz/667Mbps 266MHz/567Mbps 200MHz/400Mbps

Parameter

Symbol

tIPW

tIS_JEDEC

tIH_JEDEC

tCCD

tRC

tRRD

tRCD

tFAW

tRAS

MIN

0.6

200

275

2

55

10

15

50

MAX

MIN

0.6

250

375

2

55

10

15

50

MAX

MIN

0.6

350

475

2

55

10

15

50

MAX Units

Address and Control input puslse width for each input

Address and Control input setup time

Address and Control input hold time

CAS\ to CAS\ command delay

ACTIVE to ACTIVE command (same bank)

ACTIVE bank a to ACTIVE bank b Command

ACTIVE to READ or WRITE delay

tCK

ps

tCK

ns

4‐Bank activate period

ACTIVE to PRECHARGE

40

70000¹

40

70000¹

40

70000¹ns

Internal READ to PRECHARGE command delay

WRITE recovery time

tRTP

tWR

7.5

15

7.5

15

7.5

15

ns

Auto PRECHARGE WRITE recovery+PRECHARGE time

Internal WRITE to READ command delay

PRECHARGE command period

tDAL

tWTR

tRP

tWR + tRP

ns

7.5

15

7.5

15

10

15

PRECHARGE ALL command period

LOAD MODE, command Cycle time

CKE LOW to CK, CK\ uncertainty

tRPA

tMRD

tDELAY

tRP+tCL

ns

tCK

ns

2

tIS + tCL + tIH

REFRESH to ACTIVE or REFRESH to REFRESH

command Interval

70000 ¹

tRFC

127

ns

tREFI_IT

tREFI_ET

tREFI_XT

Average periodic REFRESH interval [Industrial temp]

Average periodic REFRESH interval [Enhanced temp]

Average periodic REFRESH interval [Military temp]

Exit SELF REFRESH to non READ command

7.8

5.9

3.9

7.8

5.9

3.9

7.8

5.9

3.9

us

tRFC(min)

+10

tRFC(min)

+10

tRFC(min)

+10

tXSNR

tXSRD

tISXR

ns

tCK

ps

Exit SELF REFRESH to READ command

Exit SELF REFRESH timing reference

200

tIS

200

tIS

200

tIS

ODT turn‐on delay

ODT turn‐off delay

tAOND

tAOPD

tAOF

2

tCK

ps

tAC(max)+

700

tAC(max)+

1000

tAC(max)+

1000

tAC(min)

2.5

tAC(max)+

600

2.5

tAC(max)+

600

2.5

tAC(max)+

600

tCK

ps

tAC(min)

2 x tCK +

tAC(max)+

1000

2 x tCK +

tAC(max)+

1000

2 x tCK +

tAC(max)+

1000

tAC(min) +

2000

tAC(min) +

2000

tAC(min) +

2000

ODT turn‐on (power‐down mode)

ODT turn‐off (power‐down mode)

tAONPD

tAOFPD

ps

2.5 x tCK +

tAC(max)+

1000

2.5 x tCK +

tAC(max)+

1000

2.5 x tCK +

tAC(max)+

1000

tAC(min) +

2000

tAC(min) +

2000

tAC(min) +

2000

ODT to power‐down entry latency

ODT power‐down exit latency

ODT enable from MRS command

Exit active POWER‐DOWN to READ command, MR[12]=0

Exit active POWER‐DOWN to READ command, MR[12]=1

Exit PRECHARGE POWER‐DOWN to any non READ

CKE Min. HIGH/LOW time

tANPD

tAXPD

tMOD

tXARD

tSARDS

tXP

3

8

12

2

3

8

12

2

3

8

12

2

tCK

ns

tCK

7 - AL

6 - AL

2

3

2

3

2

3

tCLE

Note 1: Max value reduced to 10,000ns at 125^oC

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

25

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

MECHANICAL DIAGRAM, 255 PBGA

1

2

3

4

6

7

8

9

10 11 12 13 14 15 16

T

R

P

N

M

L

K

J

19.05

NOM

24.90

25.10

H

G

F

E

D

1.27

NOM

C

B

A

(Bottom View)

255 x 0.762 NOM

1.27 NOM

31.90

32.10

0.61 NOM

2.03 MAX

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

26

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

Advanced information. Subject to change without notice.

PIN CONFIGURATION (TOP VIEW), 208 PBGA

1

2

3

4

5

6

7

8

9

10

11

VCC

VSS

NC

VSS

NC

VCC

NC

VCC

NC

VSS

NC

VCC

NC

VCC

NC

VSS

NC

VCC

VSS

VCC

VSS

A

B

C

D

E

VCC

VSS

NC

DQ34

DQ53

LDQS2

DQ58

DQ56

DQ47

A3

CK3

CK3#

CK2#

DQ48

DQ35

DQ52

LDM3

DQ38

UDM3

VCC

DQ51

DQ36

LDM2

DQ54

DQ44

A6

NC

DQ50

DQ39

DQ55

DQ63

UDQS2#

VCC

DQ37

LDQS3

DQ42

DQ40

UDQS2

A12

CK2

DQ33

DQ49

DQ60

DQ41

A10

NC

BA2

DNU

VSS

VCC

VSS

VREF

VSS

VCC

VSS

ODT

DQ32

DQ43

DQ57

DQ46

A9

DQ59

UDM2

DQ62

VCC

LDQS2# LDQS3#

F

DQ61

DQ45

G

H

J

UDQS3 UDQS3#

DNU

BA1

VCC

VSS

A0

A11

VCC

A8

VSS

VCC

A1

K

L

VCC

A2

A4

VCC

BA0

A5

A7

VCC

UDQS1# UDQS1

UDQS0

DQ8

DQ10

LDQS1

DQ5

CK1

DQ15

DQ24

DQ26

LDQS0

DQ21

DQ2

CK4

VCC

UDQS0#

DQ31

DQ23

DQ7

DQ30

UDM0

DQ27

DQ14

DQ25

DQ11

DQ9

DQ12

DQ22

LDM0

DQ4

UDM1

DQ6

M

N

P

R

T

DQ13

DQ29

DQ28

DQ17

DQ1

LDQS1# LDQS0#

LDM1

DQ20

DQ3

DQ0

CK0

VSS

VCC

VSS

DQ16

CK0#

CK1#

VSS

LDQS4# UDQS4 UDQS4#

DQ18

RAS#

CS#

LDQS4

CAS#

DQ66

VSS

DQ71

DQ64

DQ69

VCC

CKE

DQ70

LDM4

VCC

WE#

DQ65

DQ67

VSS

DQ19

DQ68

VSS

U

V

W

CK4#

VSS

VCC

VSS

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

27

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

Advanced information. Subject to change without notice.

MECHANICAL DIAGRAM (BOTTOM VIEW), 208 PBGA

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

28

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

ORDERING INFORMATION

Core

Freqency

Part Number

Data Rate

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

Device Grade

Industrial

Availability

Production

Package

AS4DDR264M72PBG-3/IT

AS4DDR264M72PBG-38/IT

AS4DDR264M72PBG-5/IT

AS4DDR264M72PBG-3/ET

AS4DDR264M72PBG-38/ET

AS4DDR264M72PBG-5/ET

AS4DDR264M72PBG-3/XT

AS4DDR264M72PBG-38/XT

AS4DDR264M72PBG-5/XT

MYX4DDR264M72PBG-3IT

MYX4DDR264M72PBG-38IT

MYX4DDR264M72PBG-5IT

MYX4DDR264M72PBG-3ET

MYX4DDR264M72PBG-38ET

MYX4DDR264M72PBG-5ET

MYX4DDR264M72PBG-3XT

MYX4DDR264M72PBG-38XT

MYX4DDR264M72PBG-5XT

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

255

Enhanced

Military

Production

255

Industrial

Enhanced

Military

Development

208

IT = Industrial = Full production, Industrial class integrated component, fully operable across -40°C to +85°C

ET = Enhanced = Full production, Enhanced class integrated component, fully operable across -40°C to +105°C

XT = Military= Full production, Mil-Temperature class integrated component, fully operable across -55°C to +125°C

* Contact Micross Sales Rep for IBIS Models

* Contact Micross Sales Rep for Thermal Models

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

29

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

ORDERING INFORMATION (CONTINUED)

Core

Freqency

Part Number

Data Rate

Device Grade

Availability

Production

Package

AS4DDR264M72PBGR-3/IT

AS4DDR264M72PBGR-38/IT

AS4DDR264M72PBGR-5/IT

AS4DDR264M72PBGR-3/ET

AS4DDR264M72PBGR-38/ET

AS4DDR264M72PBGR-5/ET

AS4DDR264M72PBGR-3/XT

AS4DDR264M72PBGR-38/XT

AS4DDR264M72PBGR-5/XT

MYX4DDR264M72PBGR-3IT

MYX4DDR264M72PBGR-38IT

MYX4DDR264M72PBGR-5IT

MYX4DDR264M72PBGR-3ET

MYX4DDR264M72PBGR-38ET

MYX4DDR264M72PBGR-5ET

MYX4DDR264M72PBGR-3XT

MYX4DDR264M72PBGR-38XT

MYX4DDR264M72PBGR-5XT

333MHz

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

667Mbps

533Mbps

400Mbps

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

333MHz

266MHz

200MHZ

Industrial - RoHS

255

Enhanced - RoHS

Military - RoHS

Production

255

Industrial - RoHS

Enhanced - RoHS

Military - RoHS

Development

208

IT = Industrial = Full production, Industrial class integrated component, fully operable across -40°C to +85°C

ET = Enhanced = Full production, Enhanced class integrated component, fully operable across -40°C to +105°C

XT = Military= Full production, Mil-Temperature class integrated component, fully operable across -55°C to +125°C

* Contact Micross Sales Rep for IBIS Models

* Contact Micross Sales Rep for Thermal Models

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

30

iPEM

4.8 Gb SDRAM-DDR2

AS4DDR264M72PBG & MYXDDR264M72

DOCUMENT TITLE

4.8Gb, 64M x 72, DDR2 SDRAM, 25mm x 32mm - 255 PBGA Multi-Chip Package [iPEM]

REVISION HISTORY

Rev #

History

Release Date

Status

1.0

Initial Release

September 2007

Preliminary

1.5

1.6

1.7

Updated Figure Notes on

pg 7, 10, 12, 13

November 2007

Preliminary

Added Conﬁguration Addressing Table September 2008

on page 1

Change temp reference from Extended June 2009

to Military

1.8

1.9

2.0

2.1

2.4

Updated Pin-out

November 2009

January 2010

February 2011

December 2012

Preliminary

Release

Updated Micross Information

Updated pinout & pin description

Updated status to “release”

Added 208 PBGA packaged option

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4DDR264M72PBG & MYXDDR264M72

Rev. 2.4 12/12

31

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