NCID9401, NCID9411
APPLICATION INFORMATION
Theory of Operation
In the layout with digital isolators, it is required that the
isolated circuits have separate ground and power planes. The
section below the device should be clear with no power,
ground or signal traces. Maintain a gap equal to or greater
than the specified minimum creepage clearance of the
device package.
NCID9401 and NCID9411 are quad−channel digital
isolators. Each channel enables communication between
two isolated circuits. It uses off−chip ceramic capacitors that
serve both as the isolation barrier and as the medium of
transmission for signal switching using On−Off keying
(OOK) technique, illustrated in the single channel
operational block diagram in Figure 17.
Signal Lines / VDD2 Fill
Signal Lines / VDD1 Fill
At the transmitter side, the V input logic state is
IN
GND1
Plane
GND2
Plane
modulated with a high frequency carrier signal. The
resulting signal is amplified and transmitted to the isolation
barrier. The receiver side detects the barrier signal and
demodulates it using an envelope detection technique. The
No Trace
VDD1 Plane
VDD2 Plane
Signal Lines / GND2 Fill
Signal Lines / GND1 Fill
Figure 19. 4−Layer PCB for Digital Isolator
output signal determines the V output logic state when the
O
output enable control EN is at high. When EN is at low,
It is highly advised to connect at least a pair of low ESR
supply bypass capacitors, placed within 2mm from the
power supply pins 1 and 16 and ground pins 2 and 15.
Recommended values are 1 mF and 0.1 mF, respectively.
output V is at high impedance state. V is at default state
O
O
low when the power supply at the transmitter side is turned
off or the input V is disconnected.
IN
Place them between the V pins of the device and the via
DD
ISOLATION
TRANSMITTER
EN
RECEIVER
BARRIER
to the power planes, with the higher frequency, lower value
capacitor closer to the device pins. Directly connect the
device ground pins 2, 8, 9 and 15 by via to their
corresponding ground planes.
TX
Amplifier
OOK
Modulator
RX
Amplifier
Envelope
Detector
V
V
O
IO
IN
OFF−CHIP
CAPACITORS
OSC
Figure 17. Operational Block Diagram of
Single Channel
1 mF 0.1 mF
0.1 mF 1 mF
V
V
DD2
GND2
DD1
GND1
V
IN
ISOLATION
BARRIER
SIGNAL
GND1
GND2
V
O
Figure 20. Placement of Bypass Capacitors
Figure 18. On−Off Keying Modulation Signals
Over Temperature Detection
NCID9401 and NCID9411 have built−in Over
Temperature Detection (OTD) feature that protects the IC
from thermal damage. The output pins will automatically
switch to default state when the ambient temperature
exceeds the maximum junction temperature at threshold of
approximately 160°C. The device will return to normal
operation when the temperature decreases approximately
20°C below the OTD threshold.
Layout Recommendation
Layout of the digital circuits relies on good suppression of
unwanted noise and electromagnetic interference. It is
recommended to use 4−layer FR4 PCB, with ground plane
below the components, power plane below the ground plane,
signal lines and power fill on top, and signal lines and ground
fill at the bottom. The alternating polarities of the layers
creates interplane capacitances that aids the bypass
capacitors required for reliable operation at digital
switching rates.
www.onsemi.com
12
