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9ZXL1930_15

型号：

9ZXL1930_15

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

231 K

下载PDF手册
DATASHEET  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
9ZXL1930  
Description  
Features/Benefits  
The 9ZXL1930 is a low power version of the Intel DB1900Z  
Differential Buffer utilizing Low-Power HCSL (LP-HCSL)  
outputs to reduce power consumption more than 50% from  
the original IDT9ZX21901. It is suitable for PCI-Express  
Gen1/2/3 or QPI/UPI applications, and uses a fixed external  
feedback to maintain low drift for demanding QPI/UPI  
applications.  
• Fixed feedback path; 0ps input-to-output delay  
• 9 Selectable SMBus addresses; Multiple devices can  
share same SMBus segment  
• Separate VDDIO for outputs; allows maximum power  
savings  
• PLL or bypass mode; PLL can dejitter incoming clock  
• Selectable PLL BW; minimizes jitter peaking in  
downstream PLL's  
Recommended Application  
Buffer for Romley, Grantley and Purley Servers  
• Spread spectrum compatible; tracks spreading input  
clock for EMI reduction  
• SMBus Interface; unused outputs can be disabled  
Key Specifications  
• Cycle-to-cycle jitter: < 50ps  
• Output-to-output skew: <85ps  
• Input-to-output delay: Fixed at 0 ps  
• Input-to-output delay variation: <50ps  
• Phase jitter: PCIe Gen3 < 1ps rms  
• Phase jitter: QPI/UPI 9.6GB/s < 0.2ps rms  
• 100MHz & 133.33MHz PLL mode; Legacy QPI/UPI  
support  
• Differential outputs are Low/Low in power down;  
Maximum power savings  
Output Features  
• 19 - LP-HCSL Differential Output Pairs  
Block Diagram  
FBOUT_NC  
DIF18  
Z-PLL  
(SS Compatible)  
DIF_IN  
DIF_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
DIF0  
Logic  
SMB_A1_tri  
SMBDAT  
SMBCLK  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
1
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
DIF_12#  
DIF_12  
VDDIO  
GND  
VDDA  
GNDA  
1
2
3
4
5
6
7
8
9
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
100M_133M#  
HIBW_BYPM_LOBW#  
CKPWRGD_PD#  
GND  
DIF_11#  
DIF_11  
DIF_10#  
DIF_10  
GND  
VDDR  
DIF_IN  
DIF_IN#  
9ZXL1930  
VDD  
SMB_A0_tri 10  
SMBDAT 11  
SMBCLK 12  
SMB_A1_tri 13  
FBOUT_NC# 14  
FBOUT_NC 15  
GND 16  
DIF_9#  
DIF_9  
DIF_8#  
DIF_8  
VDDIO  
GND  
DIF_7#  
DIF_7  
DIF_0 17  
DIF_0# 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
Power Management Table  
Inputs  
Outputs  
Control Bits  
PLL State  
DIF_IN/  
DIF_IN#  
X
SMBus  
EN bit  
DIF_x/  
DIF_x# FB_OUT_NC#  
FBOUT_NC/  
CKPWRGD_PD#  
0
X
0
1
Low/Low  
Low/Low  
Running  
Low/Low  
Running  
Running  
OFF  
ON  
ON  
1
Running  
Power Connections  
PLL Operating Mode Table  
HiBW_BypM_LoBW# Byte0, bit (7:6)  
Pin Number  
Description  
VDD  
VDDIO  
GND  
2
6
Low ( PLL Low BW)  
Mid (Bypass)  
00  
01  
1
7
Analog PLL  
Analog Input  
High (PLL High BW)  
11  
16, 22, 27, 34,  
39, 46, 51, 58,  
63, 70  
NOTE: PLL is off in Bypass mode  
21, 33, 40,  
52, 57, 69  
28, 45, 64  
DIF clocks  
Tri-Level Input Thresholds  
Level  
Low  
Mid  
Voltage  
<0.8V  
1.2<Vin<1.8V  
Vin > 2.2V  
Functionality at Power-up (PLL mode)  
DIF_IN  
(MHz)  
100.00  
133.33  
DIFx  
(MHz)  
DIF_IN  
DIF_IN  
100M_133M#  
High  
1
0
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
2
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Pin Descriptions  
PIN #  
PIN NAME  
PIN TYPE  
PWR  
PWR  
DESCRIPTION  
1
2
VDDA  
GNDA  
3.3V power for the PLL core.  
Ground pin for the PLL core.  
3.3V Input to select operating frequency  
See Functionality Table for Definition  
3
100M_133M#  
IN  
Trilevel input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
4
HIBW_BYPM_LOBW#  
CKPWRGD_PD#  
IN  
Notifies device to sample latched inputs and start up on first high assertion, or exit  
Power Down Mode on subsequent assertions. Low enters Power Down Mode.  
5
IN  
6
7
GND  
PWR  
PWR  
Ground pin.  
3.3V power for differential input clock (receiver). This VDD should be treated as an  
analog power rail and filtered appropriately.  
VDDR  
8
9
DIF_IN  
DIF_IN#  
IN  
IN  
0.7 V Differential TRUE input  
0.7 V Differential Complementary Input  
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1  
to decode 1 of 9 SMBus Addresses.  
10  
SMB_A0_tri  
IN  
11  
12  
SMBDAT  
SMBCLK  
I/O  
IN  
Data pin of SMBUS circuitry, 5V tolerant  
Clock pin of SMBUS circuitry, 5V tolerant  
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0  
to decode 1 of 9 SMBus Addresses.  
13  
SMB_A1_tri  
IN  
Complementary half of differential feedback output. This pin should NOT be connected  
to anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
14  
FBOUT_NC#  
OUT  
True half of differential feedback output. This pin should NOT be connected to anything  
outside the chip. It exists to provide delay path matching to get 0 propagation delay.  
15  
FBOUT_NC  
OUT  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
Ground pin.  
DIF_0  
DIF_0#  
DIF_1  
DIF_1#  
VDDIO  
GND  
DIF_2  
DIF_2#  
DIF_3  
DIF_3#  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
VDD  
Power supply, nominal 3.3V  
DIF_4  
DIF_4#  
DIF_5  
DIF_5#  
VDDIO  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
DIF_6  
DIF_6#  
0.7V differential true clock output  
0.7V differential Complementary clock output  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
3
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Pin Descriptions (cont.)  
PIN #  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
PIN NAME  
DIF_7  
PIN TYPE  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
PWR  
OUT  
OUT  
DESCRIPTION  
0.7V differential true clock output  
DIF_7#  
GND  
VDDIO  
DIF_8  
DIF_8#  
DIF_9  
DIF_9#  
VDD  
0.7V differential Complementary clock output  
Ground pin.  
Power supply for differential outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply, nominal 3.3V  
GND  
Ground pin.  
DIF_10  
DIF_10#  
DIF_11  
DIF_11#  
GND  
VDDIO  
DIF_12  
DIF_12#  
DIF_13  
DIF_13#  
VDDIO  
GND  
DIF_14  
DIF_14#  
DIF_15  
DIF_15#  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
Power supply for differential outputs  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Ground pin.  
VDD  
Power supply, nominal 3.3V  
DIF_16  
DIF_16#  
DIF_17  
DIF_17#  
VDDIO  
GND  
0.7V differential true clock output  
0.7V differential Complementary clock output  
0.7V differential true clock output  
0.7V differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
DIF_18  
DIF_18#  
0.7V differential true clock output  
0.7V differential Complementary clock output  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
4
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZXL1930. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over  
the recommended operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
4.6  
4.6  
3.3V Core Supply Voltage VDDA, R  
3.3V Logic Supply Voltage  
I/O Supply Voltage  
V
V
V
V
1,2  
1,2  
1,2  
1
VDD  
VDDIO  
VIL  
4.6  
Input Low Voltage  
GND-0.5  
Input High Voltage  
Input High Voltage  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5V  
5.5V  
V
1
1
VIHSMB  
V
°C  
°C  
V
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
Ts  
Tj  
ESD prot  
-65  
150  
125  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
Electrical Characteristics–DIF_IN Clock Input Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Input Crossover Voltage -  
DIF_IN  
VCROSS  
Cross Over Voltage  
150  
900  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.4  
-5  
mV  
V/ns  
uA  
1
8
5
1,2  
VIN = VDD , VIN = GND  
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
5
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Electrical Characteristics–Input/Supply/Common Output Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Ambient Operating  
Temperature  
TCOM  
Commmercial range  
0
70  
°C  
V
1
1
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Input High Voltage  
Input Low Voltage  
VIH  
2
VDD + 0.3  
VIL  
IIN  
GND - 0.3  
-5  
0.8  
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
VIN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-200  
200  
uA  
1
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
90  
150  
110  
147  
7
MHz  
MHz  
MHz  
nH  
2
2
Input Frequency  
Pin Inductance  
Capacitance  
100.00  
133.33  
Fipll  
120  
2
Lpin  
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
1.5  
1.5  
5
pF  
1
CINDIF_IN  
2.7  
pF  
1,4  
COUT  
Output pin capacitance  
6
pF  
1
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Clk Stabilization  
TSTAB  
1
ms  
1,2  
Input SS Modulation  
Frequency  
Allowable Frequency  
(Triangular Modulation)  
fMODIN  
30  
4
33  
kHz  
1
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
tLATOE#  
tDRVPD  
12  
clocks  
us  
1
300  
1,3  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
5
5
ns  
ns  
V
1,2  
1,2  
1
Trise  
tR  
Rise time of control inputs  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
0.8  
2.1  
VDDSMB  
0.4  
V
1
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
1
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
V
1
3V to 5V +/- 10%  
2.7  
5.5  
1000  
300  
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
1
fMAXSMB  
Maximum SMBus operating frequency  
100  
kHz  
1,5  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
6
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Electrical Characteristics–DIF Low-Power HCSL Differential Outputs  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
Trf  
CONDITIONS  
MIN  
1
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Scope averaging on  
Slew rate matching, Scope averaging on  
3
7.6  
4
20  
1, 2, 3  
1, 2, 4  
∆
Trf  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
757  
16  
850  
1
1
mV  
-150  
150  
Max Voltage  
Min Voltage  
Vswing  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vswing  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Scope averaging off  
857  
-36  
1150  
1
1
1, 2  
1, 5  
1, 6  
mV  
-300  
300  
300  
mV  
mV  
mV  
Vcross_abs  
Scope averaging off  
Scope averaging off  
469  
14  
550  
140  
∆
-Vcross  
1
Ω
Ω
Ω
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33 for Zo = 50 (100 differential  
trace impedance).  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross  
∆
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Electrical Characteristics–Current Consumption  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Ω
Ω
Ω
IDDVDD  
IDDVDDA/R  
IDDVDDIO  
All outputs @100MHz, CL = 2pF; Zo=85  
All outputs @100MHz, CL = 2pF; Zo=85  
All outputs @100MHz, CL = 2pF; Zo=85  
All differential pairs low/low  
mA  
mA  
mA  
mA  
mA  
mA  
1
23  
12  
35  
20  
175  
6
Operating Supply Current  
1
1
151  
2.9  
4.4  
0.05  
IDDVDDPD  
IDDVDDA/RPD  
IDDVDDIOPD  
1,2  
1,2  
1,2  
Powerdown Current  
All differential pairs low/low  
6
All differential pairs low/low  
1.5  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 With input clock running. Stopping the input clock will result in lower numbers.  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
7
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Electrical Characteristics–Skew and Differential Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tSPO_PLL  
CONDITIONS  
Input-to-Output Skew in PLL mode  
nominal value @ 25°C, 3.3V  
MIN  
-100  
TYP  
-44  
MAX  
100  
UNITS NOTES  
CLK_IN, DIF[x:0]  
ps  
ns  
ps  
1,2,4,5,8  
1,2,3,5,8  
1,2,3,5,8  
Input-to-Output Skew in Bypass mode  
nominal value @ 25°C, 3.3V  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
2.5  
-50  
3.6  
-2  
4.5  
50  
tDSPO_PLL  
Input-to-Output Skew Varation in Bypass mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF{x:0]  
tDSPO_BYP  
-250  
250  
5
ps  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,8  
Random Differential Tracking error beween two  
9ZX devices in Hi BW Mode  
ps  
(rms)  
tDTE  
3
Random Differential Spread Spectrum Tracking  
error beween two 9ZX devices in Hi BW Mode  
tDSSTE  
15  
76  
75  
85  
ps  
Output-to-Output Skew across all outputs  
(Common to Bypass and PLL mode)  
LOBW#_BYPASS_HIBW = 1  
tSKEW_ALL  
ps  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
0
0
1.75  
0.75  
3.33  
1.18  
50.4  
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
2
4
MHz  
MHz  
%
0.7  
45  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
-2  
0
2
%
1,10  
PLL mode  
Additive Jitter in Bypass Mode  
24  
0
50  
50  
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Notes for preceding table:  
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
2
3
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6. t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
8
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Electrical Characteristics–Phase Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tjphPCIeG1  
CONDITIONS  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
MIN  
TYP  
30  
MAX  
86  
UNITS  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
Notes  
1,2,3  
1.0  
1.7  
3
3.1  
1
1,2  
1,2  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
tjphPCIeG3  
0.38  
0.18  
0.13  
1,2,4  
1,5  
Phase Jitter, PLL Mode  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
0.5  
0.3  
tjphQPI_SMI  
1,5  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
0.10  
0
0.2  
10  
1,5  
(rms)  
tjphPCIeG1  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1,2,3  
1,2,6  
0.0  
0.3  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
0.0  
0.0  
0.7  
1,2,6  
1,2,4,6  
1,5,6  
0.3  
AdditivePhase Jitter,  
tjphPCIeG3  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Bypass mode  
0.12  
0.00  
0.00  
0.3  
0.1  
0.1  
tjphQPI_SMI  
1,5,6  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
1,5,6  
(rms)  
1 Applies to all outputs.  
2 See http://www.pcisig.com for complete specs  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 Subject to final ratification by PCI SIG.  
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3  
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
9
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Average  
Min  
Min  
99.75  
133.00  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Notes:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy  
requirements (+/-100ppm). The 9ZXL1930 itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
Test Loads  
Differential Output Terminations  
Ω
Ω
Rs ( )  
DIF Zo ( )  
100  
85  
33  
27  
9ZXL Differential Test Loads  
Differential Zo,  
10 inches  
Rs  
Rs  
2pF  
2pF  
LP-HCSL  
Differential  
Output  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
10  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
General SMBus Serial Interface Information  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
(H)  
written to Byte 8)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Read Operation  
Index Block Write Operation  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
Slave Address  
WR WRite  
IDT (Slave/Receiver)  
T
T
Slave Address  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
Data Byte Count=X  
Beginning Byte N  
O
O
O
ACK  
ACK  
Byte N + X - 1  
O
O
O
ACK  
O
O
O
P
stoP bit  
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
11  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
9ZXL1930 SMBus Addressing  
SMB_A(1:0)_tri  
SMBus Address (Rd/Wrt bit = 0)  
00  
0M  
01  
M0  
MM  
M1  
10  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
1M  
11  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Pin #  
4
4
72/71  
68/67  
66/65  
Name  
Control Function  
Type  
R
R
RW  
RW  
RW  
0
1
Default  
Latch  
Latch  
1
See PLL Operating Mode  
PLL Mode 1  
PLL Mode 0  
DIF_18_En  
DIF_17_En  
DIF_16_En  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Reserved  
Readback Table  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Low/Low  
Low/Low  
Enable  
Enable  
Enable  
1
1
0
Reserved  
0
133MHz  
100MHz  
3
100M_133M#  
Frequency Select Readback  
Latch  
R
SMBusTable: Output Control Register  
Byte 1  
Bit 7  
Pin #  
38/37  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
1
1
1
1
1
1
1
1
35/36  
31/32  
29/30  
25/26  
23/24  
19/20  
17/18  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Bit 7  
Pin #  
62/61  
Name  
Control Function  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_15_En  
DIF_14_En  
DIF_13_En  
DIF_12_En  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
Output Control overrides OE# pin  
1
1
1
1
1
1
1
1
60/59  
56/55  
54/53  
50/49  
48/47  
44/43  
42/41  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
SMBusTable: Reserved Register  
Byte 3 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
12  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
SMBusTable: Reserved Register  
Byte 4  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin #  
-
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
X
X
X
X
0
0
0
1
A rev = 0000  
B rev = 0001  
etc.  
-
-
-
-
-
-
-
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
-
-
-
-
-
-
-
-
VENDOR ID  
SMBusTable: DEVICE ID  
Byte 6 Pin #  
Bit 7  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
1
X
X
X
X
0
-
-
-
-
-
-
-
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1930 is 193 Decimal  
or C1 Hex  
0
1
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
-
-
-
-
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
13  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
DIF Reference Clock  
Common Recommendations for Differential Routing  
L1 length, route as non-coupled 50ohm trace  
L2 length, route as non-coupled 50ohm trace  
L3 length, route as non-coupled 50ohm trace  
Rs (100 ohm differential traces)  
Dimension or Value  
0.5 max  
0.2 max  
0.2 max  
33  
Unit Figure  
inch  
inch  
inch  
ohm  
ohm  
1
1
1
1
1
Rs (85 ohm differential traces)  
27  
Down Device Differential Routing  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
2 min to 16 max  
1.8 min to 14.4 max  
inch  
inch  
1
1
Differential Routing to PCI Express Connector  
L4 length, route as coupled microstrip 100ohm differential trace  
L4 length, route as coupled stripline 100ohm differential trace  
0.25 to 14 max  
0.225 min to 12.6 max  
inch  
inch  
2
2
Figure 1: Down Device Routing  
L2  
L1  
Rs  
Rs  
L4  
L4'  
L2'  
L1'  
LP-HCSL  
PCI Express  
Down Device  
Differential Output  
REF_CLK Input  
Figure 2: PCI Express Connector Routing  
L2  
L1  
Rs  
L4  
L4'  
L2'  
L1'  
Rs  
LP-HCSL  
Differential Output  
PCI Express  
Add-in Board  
REF_CLK Input  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
14  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Cable Connected AC Coupled Application (Figure 3)  
Component  
R5a, R5b  
R6a, R6b  
Cc  
Value  
8.2K 5%  
1K 5%  
Note  
0.1 µF  
Vcm  
0.350 volts  
Figure 3  
3. 3 Volts  
R5a  
R6a  
R5b  
R6b  
Rs  
Rs  
L4  
L4'  
PCIe Device  
REFCLK Input  
LP-HCSL  
Differential  
Output  
Marking Diagram  
ICS  
9ZXL1930BKLF  
LOT  
COO YYWWP  
Notes:  
1. ‘LOT’ is the lot number.  
2. YYWW is the last two digits of the year and week that the part was assembled.  
3. “LF” denotes RoHS compliant package.  
4. ‘COO” deontes country of origin.  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
15  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Package Outline and Package Dimensions (72-pin MLF)  
(Ref)  
ND & NE  
Even  
Seating Plane  
(ND-1)x  
(Ref)  
e
A1  
Index Area  
(Typ)  
If ND & NE  
are Even  
L
A3  
e
2
N
1
2
N
Anvil  
Singulation  
1
2
(NE-1)x  
(Ref)  
e
-- or --  
E2  
E
E2  
2
Sawn  
Singulation  
Top View  
b
A
C
(Ref)  
ND & NE  
Odd  
e
Thermal Base  
D
D2  
2
C
D2  
0.08  
Millimeters  
Symbol  
Min  
Max  
1.0  
A
A1  
A3  
0.8  
0
0.05  
0.25 Reference  
0.18 0.3  
b
e
0.50 BASIC  
D x E BASIC  
D2 MIN./MAX.  
E2 MIN./MAX.  
L MIN./MAX.  
10.00 x 10.00  
5.75  
5.75  
0.3  
6.15  
6.15  
0.5  
N
N
18  
18  
D
E
Ordering Information  
Part / Order Number  
Marking  
see page 15  
Shipping Packaging  
Tray  
Package  
72-pin MLF  
72-pin MLF  
Temperature  
0 to +70C  
0 to +70C  
9ZXL1930BKLF  
9ZXL1930BKLFT  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“B” is the device revision designator (will not correlate with the datasheet revision).  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT  
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
16  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
Revision History  
Rev. Issuer Issue Date Description  
Page #  
1. Updated key specifications table Output to Output skew to 85ps  
2. Updated Electrical Tables with typical specs  
3. Updated Byte 5 for REV ID  
4. Moved to Final  
1.Various typo fixes, changed output references to LP-HCSL.  
2. Added Test Loads figure and table.  
1.Slightly increased MAX power down currents.  
2. Clarified block diagram to indicate that there are multiple outputs.  
3. Changed title of output characterisitics table to "Electrical  
Characteristics - DIF Low-Power HCSL Differential Outputs" to follow new  
standard.  
A
B
RDW  
RDW  
12/8/2011  
3/12/2012  
1,6-9,13  
1,9,10,14  
1,7,14,15  
C
D
RDW  
RDW  
6/25/2214  
4. Reformatted Figures 2 and 3 for consistency/clarity  
1. Updated QPI references to QPI/UPI  
2. Updated DIF_IN table to match PCI SIG specification, no silicon change  
11/20/2015  
1,5  
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
17  
9ZXL1930  
REV D 112015  
9ZXL1930  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE  
SYNTHESIZERS  
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Integrated Device Technology, Inc.  
www.idt.com  
© 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or  
registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
厂商 型号 描述 页数 下载

IDT

 		9ZX21201 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201AKLF 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201AKLFT 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201BKLF 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21201BKLFT 12 ，输出差分Z缓冲的第二代PCIe / 3和QPI[ 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI ] 16 页

IDT

 		9ZX21501B 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21501BKLF 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21501BKLFT 15输出差分Zbuffer的第二代PCIe / 3和QPI[ 15-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21901B 19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

IDT

 		9ZX21901BKLF 19 ，输出差分Zbuffer的第二代PCIe / 3和QPI[ 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI ] 16 页

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