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9ZXL1950BKLFT

型号：

9ZXL1950BKLFT

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

296 K

下载PDF手册
19-output DB1900Z Low-Power Derivative  
w/85ohm Terminations  
9ZXL1950  
DATASHEET  
General Description  
Features/Benefits  
The 9ZXL1950 is a DB1900Z derivative buffer utilizing  
Low-Power HCSL (LP-HCSL) outputs to increase edge rates  
on long traces, reduce board space, and reduce power  
consumption more than 50% from the original 9ZX21901.It is  
pin-compatible to the 9ZXL1930 and fully integrates the  
output terminations. It is suitable for PCI-Express Gen1/2/3 or  
QPI/UPI applications, and uses a fixed external feedback to  
maintain low drift for demanding QPI/UPI applications.  
• LP-HCSL outputs; up to 90% IO power reduction, better  
signal integrity over long traces  
• Direct connect to 85Ω transmission lines; eliminates 76  
2
termination resistors, saves 130mm area  
• Pin compatible to the 9ZXL1930; easy upgrade to reduced  
board space  
• 72-pin VFQFPN package; smallest 19-output Z-buffer  
• Fixed feedback path; ~0ps input-to-output delay  
Recommended Application  
Buffer for Romley, Grantley and Purley Servers  
• 9 Selectable SMBus addresses; multiple devices can share  
same SMBus segment  
• Separate VDDIO for outputs; allows maximum power  
savings  
Output Features  
• PLL or bypass mode; PLL can dejitter incoming clock  
• 100MHz & 133.33MHz PLL mode; legacy QPI support  
19 LP-HCSL output pairs w/integrated terminations (Zo =  
85  
• Selectable PLL BW; minimizes jitter peaking in downstream  
PLL's  
Key Specifications  
• Cycle-to-cycle jitter: <50ps  
• Output-to-output skew: <50ps  
• Spread spectrum compatible; tracks spreading input clock  
for EMI reduction  
• Input-to-output delay variation: <50ps  
• Phase jitter: PCIe Gen3 <1ps rms  
• Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms  
• SMBus Interface; unused outputs can be disabled  
Block Diagram  
FBOUT_NC  
Z-PLL  
(SS Compatible)  
DIF_IN  
DIF_IN#  
DIF(18:0)  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
SMB_A1_tri  
SMBDAT  
Logic  
SMBCLK  
9ZXL1950 REVISION E 11/20/15  
1
©2015 Integrated Device Technology, Inc.  
9ZXL1950 DATASHEET  
Pin Configuration  
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55  
DIF12#  
DIF12  
VDDIO  
GND  
VDDA  
GNDA  
1
2
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
^100M_133M# 3  
^vHIBW_BYPM_LOBW# 4  
CKPWRGD_PD# 5  
GND 6  
DIF11#  
DIF11  
DIF10#  
DIF10  
GND  
VDDR 7  
DIF_IN 8  
9ZXL1950  
(epad should be connected to GND and is  
pin 73)  
DIF_IN# 9  
VDD  
^SADR0_tri 10  
SMBDAT 11  
SMBCLK 12  
DIF9#  
DIF9  
DIF8#  
DIF8  
^SADR1_tri 13  
FBOUT_NC# 14  
FBOUT_NC 15  
GND 16  
VDDIO  
GND  
DIF7#  
DIF7  
DIF0 17  
N/A 1530  
DIF0# 18  
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36  
Note: Pins with ^ prefix have internal 120K pullup  
Pins with v prefix have internal 120K pulldowm  
Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)  
Power Management Table  
Inputs  
Outputs  
Control Bits  
PLL State  
DIF_IN/  
SMBus  
DIFx/  
FBOUT_NC/  
CKPWRGD_PD#  
DIF_IN#  
EN bit  
DIFx# FB_OUT_NC#  
0
X
X
0
Low/Low  
Low/Low  
Low/Low  
Running  
OFF  
ON  
1
Running  
1
Running  
Running  
ON  
Power Connections  
PLL Operating Mode  
Pin Number  
VDDIO  
HiBW_BypM_LoBW# Byte0, bit (7:6)  
Description  
VDD  
1
7
GND  
2
6
Low ( PLL Low BW)  
Mid (Bypass)  
00  
01  
11  
Analog PLL  
Analog Input  
High (PLL High BW)  
16, 22, 27, 34,  
39, 46, 51, 58,  
63, 70, 73  
NOTE: PLL is off in Bypass mode  
21, 33, 40,  
52, 57, 69  
28, 45, 64  
DIF clocks  
Tri-level Input Thresholds  
Level  
Low  
Mid  
Voltage  
<0.8V  
1.2<Vin<1.8V  
Vin > 2.2V  
Functionality at Power-up (PLL mode)  
DIF_IN  
(MHz)  
100.00  
133.33  
DIFx  
(MHz)  
DIF_IN  
DIF_IN  
100M_133M#  
High  
1
0
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
2
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Pin Descriptions  
PIN #  
1
2
PIN NAME  
VDDA  
GNDA  
PIN TYPE  
PWR  
GND  
DESCRIPTION  
Power for the PLL core.  
Ground pin for the PLL core.  
3.3V Input to select operating frequency. This pin has an internal pull-up resistor.  
See Functionality Table for Definition  
3
4
^100M_133M#  
IN  
LATCHE  
D IN  
Trilevel input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
3.3V Input notifies device to sample latched inputs and start up on first high  
assertion, or exit Power Down Mode on subsequent assertions. Low enters  
Power Down Mode.  
^vHIBW_BYPM_LOBW#  
5
CKPWRGD_PD#  
IN  
6
7
GND  
GND  
PWR  
Ground pin.  
3.3V power for differential input clock (receiver). This VDD should be treated as  
an analog power rail and filtered appropriately.  
HCSL True input  
VDDR  
8
9
DIF_IN  
DIF_IN#  
IN  
IN  
HCSL Complementary Input  
SMBus address bit. This is a tri-level input that works in conjunction with the  
SADR1 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up  
resistor.  
10  
^SADR0_tri  
IN  
11  
12  
SMBDAT  
SMBCLK  
I/O  
IN  
Data pin of SMBUS circuitry, 5V tolerant  
Clock pin of SMBUS circuitry, 5V tolerant  
SMBus address bit. This is a tri-level input that works in conjunction with the  
SADR0 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up  
resistor.  
Complementary half of differential feedback output. This pin should NOT be  
connected to anything outside the chip. It exists to provide delay path matching to  
get 0 propagation delay.  
13  
14  
15  
^SADR1_tri  
FBOUT_NC#  
FBOUT_NC  
IN  
OUT  
OUT  
True half of differential feedback output. This pin should NOT be connected to  
anything outside the chip. It exists to provide delay path matching to get 0  
propagation delay.  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
GND  
DIF0  
GND  
OUT  
OUT  
OUT  
OUT  
PWR  
GND  
OUT  
OUT  
OUT  
OUT  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
GND  
OUT  
OUT  
Ground pin.  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Ground pin.  
Power supply, nominal 3.3V  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
Differential true clock output  
Differential Complementary clock output  
DIF0#  
DIF1  
DIF1#  
VDDIO  
GND  
DIF2  
DIF2#  
DIF3  
DIF3#  
GND  
VDD  
DIF4  
DIF4#  
DIF5  
DIF5#  
VDDIO  
GND  
DIF6  
DIF6#  
REVISION E 11/20/15  
3
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
Pin Descriptions (cont.)  
PIN #  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
PIN NAME  
PIN TYPE  
OUT  
OUT  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
GND  
OUT  
OUT  
OUT  
OUT  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
GND  
OUT  
OUT  
OUT  
OUT  
GND  
PWR  
OUT  
OUT  
OUT  
OUT  
PWR  
GND  
OUT  
OUT  
GND  
DESCRIPTION  
DIF7  
DIF7#  
GND  
Differential true clock output  
Differential Complementary clock output  
Ground pin.  
VDDIO  
DIF8  
Power supply for differential outputs  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Power supply, nominal 3.3V  
Ground pin.  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Ground pin.  
Power supply for differential outputs  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Ground pin.  
Power supply, nominal 3.3V  
Differential true clock output  
Differential Complementary clock output  
Differential true clock output  
Differential Complementary clock output  
Power supply for differential outputs  
Ground pin.  
Differential true clock output  
Differential Complementary clock output  
Connect EPAD to ground.  
DIF8#  
DIF9  
DIF9#  
VDD  
GND  
DIF10  
DIF10#  
DIF11  
DIF11#  
GND  
VDDIO  
DIF12  
DIF12#  
DIF13  
DIF13#  
VDDIO  
GND  
DIF14  
DIF14#  
DIF15  
DIF15#  
GND  
VDD  
DIF16  
DIF16#  
DIF17  
DIF17#  
VDDIO  
GND  
DIF18  
DIF18#  
epad  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
4
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Electrical Characteristics–Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
3.3V Core Supply Voltage VDDA, R  
4.6  
4.6  
4.6  
V
V
V
V
1,2  
1,2  
1,2  
1
3.3V Logic Supply Voltage  
I/O Supply Voltage  
VDD  
VDDIO  
VIL  
Input Low Voltage  
GND-0.5  
Input High Voltage  
Input High Voltage  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5V  
5.5V  
V
V
°C  
°C  
V
1
1
VIHSMB  
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
Ts  
Tj  
ESD prot  
-65  
150  
125  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
Electrical Characteristics–DIF_IN Clock Input Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Input Crossover Voltage -  
DIF_IN  
VCROSS  
Cross Over Voltage  
150  
900  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.4  
-5  
mV  
V/ns  
uA  
1
8
5
1,2  
VIN = VDD , VIN = GND  
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics–Current Consumption  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Ω
Ω
Ω
mA  
mA  
mA  
mA  
mA  
mA  
IDDVDD  
IDDVDDA/R  
IDDVDDIO  
All outputs 100MHz, CL = 2pF; Zo = 85  
All outputs 100MHz, CL = 2pF; Zo = 85  
All outputs 100MHz, CL = 2pF; Zo = 85  
All differential pairs low-low  
20  
15  
35  
20  
185  
6
Operating Supply Current  
142  
2.2  
4.5  
0.1  
IDDVDDPD  
IDDVDDA/RPD  
IDDVDDIOPD  
Powerdown Current  
All differential pairs low-low  
9
All differential pairs low-low  
1
REVISION E 11/20/15  
5
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
Electrical Characteristics–Input/Supply/Common Output Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
°C  
Ambient Operating  
Temperature  
TCOM  
Commmercial range  
0
35  
70  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Input High Voltage  
Input Low Voltage  
VIH  
2
V
DD + 0.3  
V
VIL  
IIN  
GND - 0.3  
-5  
0.8  
5
V
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
IN = 0 V; Inputs with internal pull-up resistors  
Input Current  
V
IINP  
-200  
200  
uA  
VIN = VDD; Inputs with internal pull-down resistors  
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
90  
150  
110  
147  
7
MHz  
MHz  
MHz  
nH  
2
2
Input Frequency  
Pin Inductance  
Capacitance  
100.00  
133.33  
Fipll  
120  
2
Lpin  
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
1.5  
1.5  
5
pF  
1
CINDIF_IN  
2.7  
pF  
1,4  
COUT  
Output pin capacitance  
6
pF  
1
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Clk Stabilization  
TSTAB  
0.65  
1
ms  
2
Input SS Modulation  
Frequency  
Allowable Frequency  
(Triangular Modulation)  
fMODIN  
30  
31.5  
25  
33  
kHz  
us  
DIF output enable after  
PD# de-assertion  
Tdrive_PD#  
tDRVPD  
300  
1,3  
Tfall  
tF  
Fall time of control inputs  
5
5
ns  
ns  
V
1,2  
1,2  
Trise  
tR  
Rise time of control inputs  
SMBus Input Low Voltage  
SMBus Input High Voltage  
VILSMB  
VIHSMB  
0.8  
2.1  
VDDSMB  
0.4  
V
SMBus Output Low Voltage VOLSMB  
@ IPULLUP  
@ VOL  
V
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
IPULLUP  
VDDSMB  
tRSMB  
4
mA  
V
3V to 5V +/- 10%  
2.7  
5.5  
1000  
300  
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
tFSMB  
fSMB  
SMBus operating frequency  
100  
kHz  
5
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
6
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
Trf  
CONDITIONS  
MIN  
1.5  
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Scope averaging on  
Slew rate matching.  
2.7  
8.8  
4
20  
1, 2, 3  
1, 2, 4  
∆
Trf  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
787  
33  
850  
mV  
-150  
150  
Max Voltage  
Min Voltage  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vcross_abs  
Single ended signal using absolute value.  
Includes 300mV of over/undershoot. (Scope  
845  
9
471  
14  
1150  
mV  
-300  
250  
Scope averaging off  
Scope averaging off  
550  
140  
mV  
mV  
1, 5  
1, 6  
∆
-Vcross  
1
Ω
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with Zo = 85 differential trace impedance.  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross  
∆
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
99.75  
133.00  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Notes:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+  
accuracy requirements (+/-100ppm). The 9ZXL1950 itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
REVISION E 11/20/15  
7
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
Electrical Characteristics–Skew and Differential Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tSPO_PLL  
CONDITIONS  
MIN  
-150  
TYP  
-117  
MAX  
-50  
UNITS NOTES  
Input-to-Output Skew in PLL mode  
nominal value @ 35°C, 3.3V, 100MHz  
Input-to-Output Skew in Bypass mode  
nominal value @ 35°C, 3.3V  
CLK_IN, DIF[x:0]  
ps  
ns  
ps  
1,2,4,5,8  
1,2,3,5,8  
1,2,3,5,8  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
2.5  
-50  
3.6  
0
4.5  
50  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
tDSPO_PLL  
Input-to-Output Skew Varation in Bypass mode  
across temperature for a given voltage  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF[x:0]  
tDSPO_BYP  
-250  
0
1
250  
5
ps  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,8  
Random Differential Tracking error beween two  
9ZX devices in Hi BW Mode  
ps  
(rms)  
tDTE  
Random Differential Spread Spectrum Tracking  
error beween two 9ZX devices in Hi BW Mode  
tDSSTE  
5
75  
50  
ps  
Output-to-Output Skew across all outputs  
(Common to Bypass and PLL mode). 100MHz  
LOBW#_BYPASS_HIBW = 1  
tSKEW_ALL  
37  
ps  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
0
0
1.8  
0.7  
3.3  
1.2  
50  
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
2
4
MHz  
MHz  
%
0.7  
45  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
0
0.7  
1.5  
%
1,10  
PLL mode  
12  
0
50  
10  
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Additive Jitter in Bypass Mode  
Notes for preceding table:  
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.  
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
2
3
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6. t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
8
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Electrical Characteristics–Phase Jitter Parameters  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
tjphPCIeG1  
CONDITIONS  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
MIN  
TYP  
34  
MAX  
86  
UNITS  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
Notes  
1,2,3  
1.2  
2.1  
0.5  
0.2  
0.1  
3
3.1  
1
1,2  
1,2  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
tjphPCIeG3  
1,2,4  
1,5  
Phase Jitter, PLL Mode  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
0.5  
0.3  
tjphQPI_SMI  
1,5  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
0.1  
0.1  
0.1  
0.2  
10  
1,5  
(rms)  
tjphPCIeG1  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1,2,3  
1,2,6  
0.3  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
0.1  
0.0  
0.0  
0.0  
0.0  
0.7  
1,2,6  
1,2,4,6  
1,5,6  
0.3  
AdditivePhase Jitter,  
tjphPCIeG3  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Bypass mode  
0.3  
0.1  
0.1  
tjphQPI_SMI  
1,5,6  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
1,5,6  
(rms)  
1 Applies to all outputs.  
2 See http://www.pcisig.com for complete specs  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 Subject to final ratification by PCI SIG.  
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.4  
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2  
Test Loads  
Differential Output Terminations  
Ω
Ω
Rs ( )  
DIF Zo ( )  
85  
Internal  
7.5  
(External)  
100  
9ZXL Differential Test Loads  
Zo = 85Dif.,  
10 inches  
Rs  
Rs  
2pF  
2pF  
LP-HCSL  
Differential  
Output  
REVISION E 11/20/15  
9
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
General SMBus Serial Interface Information  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
written to Byte 8)  
(H)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Index Block Read Operation  
Controller (Host)  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
starT bit  
T
Slave Address  
Slave Address  
WRite  
WR  
WRite  
WR  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
O
O
O
P
stoP bit  
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 10  
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
9ZXL1950 SMBus Addressing  
SADR(1:0)_tri  
SMBus Address (Rd/Wrt bit = 0)  
00  
0M  
01  
M0  
MM  
M1  
10  
D8  
DA  
DE  
C2  
C4  
C6  
CA  
CC  
CE  
1M  
11  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Pin #  
4
4
72/71  
68/67  
66/65  
Name  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Output Control  
Output Control  
Output Control  
Reserved  
Reserved  
Frequency Select Readback  
Type  
R
R
RW  
RW  
RW  
0
1
Default  
Latch  
Latch  
1
PLL Mode 1  
PLL Mode 0  
DIF_18_En  
DIF_17_En  
DIF_16_En  
See PLL Operating Mode  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Readback Table  
Low/Low  
Low/Low  
Low/Low  
Enable  
Enable  
Enable  
1
1
0
0
133MHz  
100MHz  
3
100M_133M#  
Latch  
R
SMBusTable: Output Control Register  
Byte 1  
Bit 7  
Pin #  
38/37  
Name  
Control Function  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_7_En  
DIF_6_En  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
DIF_1_En  
DIF_0_En  
1
1
1
1
1
1
1
1
35/36  
31/32  
29/30  
25/26  
23/24  
19/20  
17/18  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Bit 7  
Pin #  
62/61  
Name  
Control Function  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Output Control  
Type  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_15_En  
DIF_14_En  
DIF_13_En  
DIF_12_En  
DIF_11_En  
DIF_10_En  
DIF_9_En  
DIF_8_En  
1
1
1
1
1
1
1
1
60/59  
56/55  
54/53  
50/49  
48/47  
44/43  
42/41  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
SMBusTable: PLL SW Override Control Register  
Byte 3  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
1
1
0
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Note:  
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
Enable S/W control of PLL BW  
PLL Operating Mode 1  
PLL Operating Mode 1  
Reserved  
RW  
RW  
RW  
HW Latch  
See PLL Operating Mode  
SMBus Control  
Readback Table  
Setting bit 3 to '1' allows the user to overide the Latch value from pin 4 via use of bits 2 and 1. Use the values from the PLL Operating  
Mode Readback Table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. A warm reset of the system will have to  
accomplished if the user changes these bits.  
REVISION E 11/20/15  
11  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
SMBusTable: Reserved Register  
Byte 4  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin #  
-
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
X
X
X
X
0
0
0
1
A rev = 0000  
B rev = 0001  
etc.  
-
-
-
-
-
-
-
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
-
-
-
-
-
-
-
-
VENDOR ID  
SMBusTable: DEVICE ID  
Byte 6 Pin #  
Bit 7  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
1
1
0
0
0
0
1
1
-
-
-
-
-
-
-
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1950 is 195 Decimal  
or C3 Hex  
1550 is 155 Decimal  
or 9B Hex  
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
-
-
-
-
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 12  
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Alternate Terminations  
The 9ZXL1950 can be terminated to other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's  
"Universal" Low-Power HCSL Outputs” for details.  
Marking Diagram  
ICS  
9ZXL1950BKLF  
LOT  
YYWW  
Notes:  
1. “LOT” denotes the lot number.  
2. “YYWW” is the last two digits of the year and week that the part was assembled.  
3. “LF” denotes RoHS compliant package.  
4. Bottom marking: country of origin if not USA.  
REVISION E 11/20/15  
13  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
Package Outline and Package Dimensions (NLG72)  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 14  
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Package Outline and Package Dimensions (NLG72), cont. Use EPAD Option P1.  
REVISION E 11/20/15  
15  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
9ZXL1950 DATASHEET  
Package Outline and Package Dimensions (NLG72), cont. Use P1 EPAD 5.9mm SAWN pattern.  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 16  
REVISION E 11/20/15  
9ZXL1950 DATASHEET  
Ordering Information  
Part / Order Number Shipping Package  
Package  
72-pin VFQFPN  
72-pin VFQFPN  
Temperature  
0 to +70°C  
0 to +70°C  
9ZXL1950BKLF  
9ZXL1950BKLFT  
Trays  
Tape and Reel  
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“B” is the device revision designator (will not correlate with the datasheet revision).  
Revision History  
Rev. Issuer Issue Date Description  
Page #  
A
B
C
RDW  
RDW  
RDW  
3/11/2014 Moved to final.  
1. Cleaned up output pin names to be DIFxx instead of DIF_xx  
2. Updated electrical tables to new format  
3/7/2015 3. Updated ordering info to B rev along with Rev ID.  
4. Updated termination schemes for driving LVDS.  
5. Minor cleanup/reformatting of DS, including front page text.  
6/16/2015 Added landing pattern from POD  
Various  
17  
1,8  
2
1. Tightened O2O spec from 75 to 50ps  
2. Added epad (pin 73) to power connections table  
3. Updated pin 73 pin name from "GND" to "epad"  
4
4. Clarified SMBus operating frequency by removing the word "Maximum"  
and updated the symbol from fMINSMB to fSMB  
5. Tightened duty cycle distortion and additive cycle to cycle jitter specs  
6. Updated Rs from 7 to 7.5 ohms in Test Loads Table  
7. Replaced LVDS termination info with reference to AN891.  
6
D
E
RDW  
RDW  
7/30/2015  
8
9
13  
1. Updated QPI references to QPI/UPI  
11/20/2015  
1,5  
2. Updated DIF_IN table to match PCI SIG specification, no silicon change  
REVISION E 11/20/15  
17  
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
Sales  
Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in  
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined  
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether  
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This  
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected  
names, logos and designs, are the property of IDT or their respective third party owners.  
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.  
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