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9ZXL0831

型号：

9ZXL0831

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

18 页

PDF大小：

347 K

下载PDF手册
DATASHEET  
8-OUTPUT DB800ZL  
9ZXL0831  
General Description  
Features/Benefits  
The 9ZXL0831 is a low-power 8-output differential buffer  
that meets all the performance requirements of the Intel  
DB800ZL specification. It is suitable for PCI-Express  
Gen1/2/3 or QPI/UPI applications, and uses a fixed external  
feedback to maintain low drift for demanding QPI/UPI  
applications.  
• Low-power push-pull outputs; Save power and board  
space - no Rp  
• Space-saving 48-pin VFQFPN package  
• Fixed feedback path for 0ps input-to-output delay  
• 8 OE# pins; hardware control of each output  
• PLL or bypass mode; PLL can dejitter incoming clock  
• 100MHz or 133MHz PLL mode operation; supports PCIe  
Recommended Application  
Buffer for Romley, Grantley and Purley Servers, SSD drives  
and PCIe  
and QPI applications  
• Selectable PLL bandwidth; minimizes jitter peaking in  
downstream PLL's  
Output Features  
• 8 - LP-HCSL Output Pairs  
• Spread Spectrum Compatible; tracks spreading input  
clock for low EMI  
Key Specifications  
• Cycle-to-cycle jitter <50ps  
• Output-to-output skew <65 ps  
• Input-to-output delay variation <50ps  
• PCIe Gen3 phase jitter <1.0ps RMS  
• QPI/UPI 9.6GT/s 12UI phase jitter <0.2ps RMS  
Block Diagram  
OE(7:0)#  
DFB_OUT_NC  
Z-PLL  
(SS Compatible)  
DIF_IN  
DIF_IN#  
DIF(7:0)  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
Logic  
SMBDAT  
SMBCLK  
IDT® 8-OUTPUT DB800ZL  
1
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Pin Configuration  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
3
4
5
6
7
8
9
CKPWRGD_PD#  
GND  
DIF_6#  
DIF_6  
VDD  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDR  
DIF_IN  
DIF_5#  
DIF_5  
vOE5#  
vOE4#  
DIF_4#  
DIF_4  
VDD  
DIF_IN#  
9ZXL0831  
SMBDAT  
SMBCLK  
DFB_OUT_NC#  
DFB_OUT_NC  
VDD  
Paddle is  
pin 49  
Connect to GND  
10  
11  
12  
vOE0#  
DIF_3#  
DIF_3  
NC  
13 14 15 16 17 18 19 20 21 22 23 24  
48-pin VFQFPN, 6x6 mm, 0.4mm pitch  
Power Management Table  
PLL STATE  
IF NOT IN  
DIF_IN/  
DIF_IN#  
SMBus  
EN bit  
DIF(7:0)/  
DIF(7:0)#  
Low/Low  
Low/Low  
Running  
BYPASS  
MODE  
OFF  
CKPWRGD_PD#  
0
X
X
0
1
ON  
ON  
1
Running  
Functionality at Power-up (PLL mode)  
PLL Operating Mode Readback Table  
DIF_IN  
MHz  
100.00  
133.33  
HiBW_BypM_LoBW#  
Low (Low BW)  
Byte0, bit 7  
Byte 0, bit 6  
100M_133M#  
DIF(7:0)  
0
0
1
0
1
1
1
0
DIF_IN  
DIF_IN  
Mid (Bypass)  
High (High BW)  
Power Connections  
Tri-Level Input Thresholds  
Pin Number  
Level  
Low  
Mid  
Voltage  
<0.8V  
1.2<Vin<1.8V  
Vin > 2.2V  
Description  
VDD  
44  
GND  
49  
Analog PLL  
Analog Input  
High  
3
2
10,15,19,  
27,34,38, 42  
49  
DIF clocks  
PLL Operating Mode  
HiBW_BypM_LoBW#  
MODE  
SMBus Address  
Low  
PLL Lo BW  
Address  
+
Read/Write bit  
Mid  
Bypass  
1101100  
x
High  
PLL Hi BW  
NOTE: PLL is OFF in Bypass Mode  
IDT® 8-OUTPUT DB800ZL  
2
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Pin Descriptions  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
3.3V Input notifies device to sample latched inputs and start up on first high  
1
CKPWRGD_PD#  
IN assertion, or exit Power Down Mode on subsequent assertions. Low enters  
Power Down Mode.  
GND Ground pin.  
2
3
GND  
3.3V power for differential input clock (receiver). This VDD should be  
VDDR  
PWR  
treated as an analog power rail and filtered appropriately.  
4
5
6
7
DIF_IN  
IN 0.7 V Differential True input  
DIF_IN#  
SMBDAT  
SMBCLK  
IN 0.7 V Differential Complementary Input  
I/O Data pin of SMBUS circuitry, 5V tolerant  
IN Clock pin of SMBUS circuitry, 5V tolerant  
Complementary half of differential feedback output, provides feedback  
signal to the PLL for synchronization with input clock to eliminate phase  
error. This pin should NOT be connected on the circuit board, the feedback  
is internal to the package.  
True half of differential feedback output, provides feedback signal to the  
PLL for synchronization with the input clock to eliminate phase error. This  
pin should NOT be connected on the circuit board, the feedback is internal  
8
9
DFB_OUT_NC#  
DFB_OUT_NC  
OUT  
OUT  
to the package.  
10 VDD  
PWR Power supply, nominal 3.3V  
Active low input for enabling DIF pair 0. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
11 vOE0#  
IN  
12 NC  
N/A No Connection.  
13 DIF_0  
14 DIF_0#  
15 VDD  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
PWR Power supply, nominal 3.3V  
16 DIF_1  
17 DIF_1#  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
Active low input for enabling DIF pair 1. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
18 vOE1#  
IN  
19 VDD  
20 NC  
PWR Power supply, nominal 3.3V  
N/A No Connection.  
21 DIF_2  
22 DIF_2#  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
Active low input for enabling DIF pair 2. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
23 vOE2#  
24 vOE3#  
IN  
Active low input for enabling DIF pair 3. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
IN  
25 DIF_3  
26 DIF_3#  
27 VDD  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
PWR Power supply, nominal 3.3V  
28 DIF_4  
29 DIF_4#  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
Active low input for enabling DIF pair 4. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
30 vOE4#  
31 vOE5#  
IN  
Active low input for enabling DIF pair 5. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
IN  
IDT® 8-OUTPUT DB800ZL  
3
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Pin Descriptions (cont.)  
PIN #  
PIN NAME  
TYPE  
DESCRIPTION  
32 DIF_5  
33 DIF_5#  
34 VDD  
35 DIF_6  
36 DIF_6#  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
PWR Power supply, nominal 3.3V  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
Active low input for enabling DIF pair 6. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
37 vOE6#  
IN  
38 VDD  
PWR Power supply, nominal 3.3V  
39 DIF_7  
40 DIF_7#  
OUT 0.7V differential true clock output  
OUT 0.7V differential Complementary clock output  
Active low input for enabling DIF pair 7. This pin has an internal pull-down.  
1 =disable outputs, 0 = enable outputs  
41 vOE7#  
IN  
42 VDD  
43 NC  
PWR Power supply, nominal 3.3V  
N/A No Connection.  
44 VDDA  
45 NC  
PWR 3.3V power for the PLL core.  
N/A No Connection.  
46 NC  
N/A No Connection.  
3.3V Input to select operating frequency.  
See Functionality Table for Definition  
47 100M_133M#  
IN  
Trilevel input to select High BW, Bypass or Low BW mode.  
See PLL Operating Mode Table for Details.  
PWR Ground  
48 HIBW_BYPM_LOBW#  
49 GND  
IN  
IDT® 8-OUTPUT DB800ZL  
4
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Absolute Maximum Ratings  
Stresses above the ratings listed below can cause permanent damage to the 9ZXL0831. These ratings, which are standard  
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other  
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over  
the recommended operating temperature range.  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
4.6  
VDD, VDDA,  
VDDR  
3.3V Supply Voltage  
VDD for core logic and PLL  
V
1,2  
Input Low Voltage  
Input High Voltage  
Input High Voltage  
VIL  
GND-0.5  
V
V
V
°C  
°C  
V
1
1
1
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5V  
5.5V  
VIHSMB  
1
1
1
Storage Temperature  
Junction Temperature  
Input ESD protection  
Ts  
Tj  
ESD prot  
-65  
150  
125  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
Electrical Characteristics–DIF_IN Clock Input Parameters (HCSL-compatible)  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
VCROSS  
CONDITIONS  
MIN  
150  
TYP  
MAX  
900  
UNITS NOTES  
Input Crossover Voltage -  
DIF_IN  
Cross Over Voltage  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.4  
-5  
mV  
V/ns  
uA  
1
8
5
1,2  
VIN = VDD , VIN = GND  
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
IDT® 8-OUTPUT DB800ZL  
5
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Electrical Characteristics–Input/Supply/Common Parameters  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
TCOM  
CONDITIONS  
MIN  
0
TYP  
MAX  
70  
UNITS NOTES  
Ambient Operating  
Temperature  
Commmercial range  
°C  
V
1
1
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Single-ended inputs, except SMBus, low  
threshold and tri-level inputs  
Input High Voltage  
Input Low Voltage  
VIH  
2
VDD + 0.3  
VIL  
IIN  
GND - 0.3  
-5  
0.8  
5
V
1
1
Single-ended inputs, VIN = GND, VIN = VDD  
uA  
Single-ended inputs  
VIN = 0 V; Inputs with internal pull-up resistors  
IN = VDD; Inputs with internal pull-down resistors  
Input Current  
IINP  
-200  
200  
uA  
1
V
Fibyp  
Fipll  
VDD = 3.3 V, Bypass mode  
VDD = 3.3 V, 100MHz PLL mode  
VDD = 3.3 V, 133.33MHz PLL mode  
33  
90  
150  
110  
147  
7
MHz  
MHz  
MHz  
nH  
2
2
Input Frequency  
Pin Inductance  
Capacitance  
100.00  
133.33  
Fipll  
120  
2
Lpin  
1
CIN  
Logic Inputs, except DIF_IN  
DIF_IN differential clock inputs  
Output pin capacitance  
1.5  
1.5  
5
pF  
1
CINDIF_IN  
COUT  
2.7  
6
pF  
1,4  
1
pF  
From VDD Power-Up and after input clock  
stabilization or de-assertion of PD# to 1st clock  
Allowable Frequency  
Clk Stabilization  
TSTAB  
fMODIN  
tLATOE#  
tDRVPD  
0.250  
1
ms  
kHz  
1,2  
1
Input SS Modulation  
Frequency  
30  
4
33  
(Triangular Modulation)  
DIF start after OE# assertion  
DIF stop after OE# deassertion  
DIF output enable after  
OE# Latency  
Tdrive_PD#  
12  
cycles  
us  
1,3  
1,3  
300  
PD# de-assertion  
Tfall  
tF  
Fall time of control inputs  
10  
10  
ns  
ns  
V
1,2  
1,2  
1
Trise  
tR  
Rise time of control inputs  
SMBus Input Low Voltage  
SMBus Input High Voltage  
SMBus Output Low Voltage  
SMBus Sink Current  
Nominal Bus Voltage  
SCLK/SDATA Rise Time  
VILSMB  
VIHSMB  
VOLSMB  
IPULLUP  
VDDSMB  
tRSMB  
tFSMB  
0.8  
2.1  
VDDSMB  
0.4  
V
1
@ IPULLUP  
@ VOL  
V
1
4
mA  
V
1
3V to 5V +/- 10%  
2.7  
5.5  
1000  
300  
1
(Max VIL - 0.15) to (Min VIH + 0.15)  
(Min VIH + 0.15) to (Max VIL - 0.15)  
ns  
ns  
1
SCLK/SDATA Fall Time  
SMBus Operating  
Frequency  
1
fMAXSMB  
Maximum SMBus operating frequency  
100  
kHz  
1,5  
1Guaranteed by design and characterization, not 100% tested in production.  
2Control input must be monotonic from 20% to 80% of input swing.  
3Time from deassertion until outputs are >200 mV  
4DIF_IN input  
5The differential input clock must be running for the SMBus to be active  
IDT® 8-OUTPUT DB800ZL  
6
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
Trf  
CONDITIONS  
MIN  
2
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Scope averaging on  
Slew rate matching, Scope averaging on  
3.3  
6.8  
4
20  
1, 2, 3  
1, 2, 4  
∆
Trf  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
778  
0
850  
1
1
mV  
-150  
150  
Max Voltage  
Min Voltage  
Vswing  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vswing  
Measurement on single ended signal using  
absolute value. (Scope averaging off)  
Scope averaging off  
918  
-71  
1556 1812  
458  
17  
1150  
1
1
1, 2  
1, 5  
1, 6  
mV  
-300  
300  
300  
mV  
mV  
mV  
Vcross_abs  
Scope averaging off  
Scope averaging off  
550  
140  
∆
-Vcross  
1
Ω
Ω
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 27 for Zo = 85 differential trace  
impedance).  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross  
∆
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Electrical Characteristics–Current Consumption  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
59  
MAX  
UNITS NOTES  
IDDVDD  
IDDVDDA  
IDDVDDPD  
IDDVDDAPD  
133MHz, VDD rail  
133MHz, VDDA + VDDR rail, PLL Mode  
Power Down, VDD Rail  
75  
25  
2
mA  
mA  
mA  
mA  
1
1
1
1
Operating Current  
19  
1.2  
2.5  
Powerdown Current  
Power Down, VDDA Rail  
5
1Guaranteed by design and characterization, not 100% tested in production.  
2
Ω
Ω
CL = 2pF with RS = 27 for Zo = 85 differential trace impedance  
IDT® 8-OUTPUT DB800ZL  
7
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Electrical Characteristics–Skew and Differential Jitter Parameters  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
tSPO_PLL  
CONDITIONS  
Input-to-Output Skew in PLL mode  
nominal value @ 25°C, 3.3V  
MIN  
-100  
TYP  
-60  
MAX  
100  
UNITS NOTES  
CLK_IN, DIF[x:0]  
ps  
ns  
ps  
1,2,4,5,8  
1,2,3,5,8  
1,2,3,5,8  
Input-to-Output Skew in Bypass mode  
nominal value @ 25°C, 3.3V  
Input-to-Output Skew Varation in PLL mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
tPD_BYP  
2.5  
-50  
3.2  
4.5  
50  
tDSPO_PLL  
Input-to-Output Skew Varation in Bypass mode  
across voltage and temperature  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
CLK_IN, DIF[x:0]  
DIF{x:0]  
tDSPO_BYP  
-250  
250  
5
ps  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,5,8  
1,2,3,8  
Random Differential Tracking error beween two  
9ZX devices in Hi BW Mode  
ps  
(rms)  
tDTE  
1
5
Random Differential Spread Spectrum Tracking  
error beween two 9ZX devices in Hi BW Mode  
tDSSTE  
75  
65  
ps  
Output-to-Output Skew across all outputs  
(Common to Bypass and PLL mode)  
LOBW#_BYPASS_HIBW = 1  
tSKEW_ALL  
53  
ps  
PLL Jitter Peaking  
PLL Jitter Peaking  
PLL Bandwidth  
PLL Bandwidth  
Duty Cycle  
jpeak-hibw  
jpeak-lobw  
pllHIBW  
pllLOBW  
tDC  
0
0
1.2  
0.76  
3
2.5  
2
dB  
dB  
7,8  
7,8  
8,9  
8,9  
1
LOBW#_BYPASS_HIBW = 0  
LOBW#_BYPASS_HIBW = 1  
LOBW#_BYPASS_HIBW = 0  
2
4
MHz  
MHz  
%
0.7  
45  
1.1  
50.1  
1.4  
55  
Measured differentially, PLL Mode  
Measured differentially, Bypass Mode  
@100MHz  
Duty Cycle Distortion  
Jitter, Cycle to cycle  
tDCD  
-2  
0
2
%
1,10  
PLL mode  
Additive Jitter in Bypass Mode  
34  
17  
50  
50  
ps  
ps  
1,11  
1,11  
tjcyc-cyc  
Notes for preceding table:  
1
Ω
Ω
CL = 2pF with RS = 27 for Zo = 85 differential trace impedance. Input to output skew is measured at the first output edge following the  
corresponding input.  
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.  
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.  
3
4 This parameter is deterministic for a given device  
5
Measured with scope averaging on to find mean value.  
6.t is the period of the input clock  
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.  
8.  
Guaranteed by design and characterization, not 100% tested in production.  
9
Measured at 3 db down or half power point.  
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.  
11 Measured from differential waveform  
IDT® 8-OUTPUT DB800ZL  
8
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Electrical Characteristics–Phase Jitter Parameters  
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%  
PARAMETER  
SYMBOL  
tjphPCIeG1  
CONDITIONS  
PCIe Gen 1  
MIN  
TYP  
34  
MAX  
86  
UNITS  
ps (p-p)  
Notes  
1,2,3  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1.2  
2.2  
3
3.1  
1
1,2  
1,2  
tjphPCIeG2  
tjphPCIeG3  
0.5  
1,2,4  
1,5  
Phase Jitter, PLL Mode  
(PLL BW of 2-4MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
0.24  
0.14  
0.5  
0.3  
tjphQPI_SMI  
1,5  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
(rms)  
ps  
(rms)  
0.12  
3.7  
0.2  
10  
1,5  
tjphPCIeG1  
PCIe Gen 1  
PCIe Gen 2 Lo Band  
10kHz < f < 1.5MHz  
ps (p-p)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
(rms)  
ps  
1,2,3  
1,2,6  
0.1  
0.3  
tjphPCIeG2  
PCIe Gen 2 High Band  
1.5MHz < f < Nyquist (50MHz)  
PCIe Gen 3  
0.4  
0.6  
1,2,6  
1,2,4,6  
1,5,6  
0.2  
AdditivePhase Jitter,  
tjphPCIeG3  
0.00  
0.14  
0.00  
0.00  
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)  
QPI & SMI  
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)  
QPI & SMI  
Bypass mode  
0.2  
0.1  
0.1  
tjphQPI_SMI  
1,5,6  
(100MHz, 8.0Gb/s, 12UI)  
QPI & SMI  
(100MHz, 9.6Gb/s, 12UI)  
1,5,6  
(rms)  
1 Applies to all outputs.  
2 See http://www.pcisig.com for complete specs  
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.  
4 Subject to final ratification by PCI SIG.  
5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3  
6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2  
IDT® 8-OUTPUT DB800ZL  
9
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
99.75  
133.00  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Notes:  
1Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+  
accuracy requirements (+/-100ppm). The device itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
Test Loads  
Differential Output Terminations  
Ω
Ω
Rs ( )  
DIF Zo ( )  
100  
85  
33  
27  
Differential Test Loads  
10 inches  
Rs  
Rs  
85ohm Differential Zo  
2pF  
2pF  
Low-Power  
HCSL-  
Compatible  
Output buffer  
IDT® 8-OUTPUT DB800ZL  
10  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
General SMBus Serial Interface Information for 9ZXL0831  
How to Write  
How to Read  
• Controller (host) sends a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) will send a start bit  
• Controller (host) sends the write address  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the beginning byte location = N  
• IDT clock will acknowledge  
• Controller (host) sends the byte count = X  
• IDT clock will acknowledge  
• Controller (host) will send a separate start bit  
• Controller (host) sends the read address  
• IDT clock will acknowledge  
• IDT clock will send the data byte count = X  
• IDT clock sends Byte N+X-1  
• Controller (host) starts sending Byte N through Byte  
N+X-1  
• IDT clock will acknowledge each byte one at a time  
• Controller (host) sends a Stop bit  
• IDT clock sends Byte 0 through Byte X (if X was  
(H)  
written to Byte 8)  
• Controller (host) will need to acknowledge each byte  
• Controller (host) will send a not acknowledge bit  
• Controller (host) will send a stop bit  
Index Block Write Operation  
Index Block Read Operation  
Controller (Host)  
starT bit  
Slave Address  
IDT (Slave/Receiver)  
Controller (Host)  
starT bit  
IDT (Slave/Receiver)  
T
T
Slave Address  
WR  
WRite  
WR  
WRite  
ACK  
ACK  
ACK  
ACK  
ACK  
ACK  
Beginning Byte = N  
Data Byte Count = X  
Beginning Byte N  
Beginning Byte = N  
RT  
Repeat starT  
Slave Address  
ReaD  
RD  
ACK  
O
O
O
O
O
O
Data Byte Count=X  
Beginning Byte N  
ACK  
ACK  
Byte N + X - 1  
ACK  
O
O
O
P
stoP bit  
O
O
O
Byte N + X - 1  
N
P
Not acknowledge  
stoP bit  
IDT® 8-OUTPUT DB800ZL  
11  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
SMBusTable: PLL Mode, and Frequency Select Register  
Byte 0  
Bit 7  
Pin #  
48  
48  
Name  
PLL Mode 1  
PLL Mode 0  
Control Function  
PLL Operating Mode Rd back 1  
PLL Operating Mode Rd back 0  
Reserved  
Type  
R
R
0
1
Default  
Latch  
Latch  
0
See PLL Operating Mode  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Note:  
Readback Table  
Reserved  
0
0
1
PLL_SW_EN  
PLL Mode 1  
PLL Mode 0  
100M_133M#  
Enable S/W control of PLL BW  
PLL Operating Mode 1  
PLL Operating Mode 0  
Frequency Select Readback  
RW  
RW  
RW  
R
HW Latch  
See PLL Operating Mode  
Readback Table  
133MHz  
SMBus Control  
1
100MHz  
47  
Latch  
Setting bit 3 to '1' allows the user to overide the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating  
Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the system will have to  
accomplished if the user changes these bits.  
SMBusTable: Output Control Register  
Byte 1  
Bit 7  
Pin #  
32/33  
28/29  
25/26  
21/22  
Name  
Control Function  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Reserved  
Output Control - '0' overrides OE# pin  
Output Control - '0' overrides OE# pin  
Reserved  
Type  
RW  
RW  
RW  
RW  
0
1
Default  
DIF_5_En  
DIF_4_En  
DIF_3_En  
DIF_2_En  
1
1
1
1
1
1
1
1
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Low/Low  
Enable  
16/17  
13/14  
DIF_1_En  
DIF_0_En  
RW  
RW  
Low/Low  
Enable  
SMBusTable: Output Control Register  
Byte 2  
Bit 7  
Pin #  
Name  
Control Function  
Type  
0
1
Default  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
1
1
1
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
39/40  
35/36  
DIF_7_En  
DIF_6_En  
Output Control - '0' overrides OE# pin  
Reserved  
Output Control - '0' overrides OE# pin  
RW  
RW  
Low/Low  
Low/Low  
Enable  
Enable  
SMBusTable: Reserved Register  
Byte 3 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SMBusTable: Reserved Register  
Byte 4 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
IDT® 8-OUTPUT DB800ZL  
12  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
SMBusTable: Vendor & Revision ID Register  
Byte 5  
Bit 7  
Pin #  
-
Name  
RID3  
RID2  
RID1  
RID0  
VID3  
VID2  
VID1  
VID0  
Control Function  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
X
X
X
X
0
0
0
1
-
-
-
-
-
-
-
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
REVISION ID  
A rev = 0000  
-
-
-
-
-
-
-
-
VENDOR ID  
SMBusTable: DEVICE ID  
Byte 6 Pin #  
Bit 7  
Name  
Control Function  
Device ID 7 (MSB)  
Type  
R
R
R
R
R
R
R
R
0
1
Default  
-
1
1
1
0
0
1
1
1
-
-
-
-
-
-
-
Device ID 6  
Device ID 5  
Device ID 4  
Device ID 3  
Device ID 2  
Device ID 1  
Device ID 0  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0831 is 231 Decimal  
or E7 Hex  
SMBusTable: Byte Count Register  
Byte 7  
Bit 7  
Pin #  
Name  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
1
0
0
0
Reserved  
Reserved  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
-
BC4  
BC3  
BC2  
BC1  
BC0  
RW  
RW  
RW  
RW  
RW  
Default value is 8 hex, so 9  
bytes (0 to 8) will be read back  
by default.  
-
-
-
-
Writing to this register configures how  
many bytes will be read back.  
SMBusTable: Reserved Register  
Byte 8 Pin # Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Control Function  
Reserved  
Type  
0
1
Default  
0
0
0
0
0
0
0
0
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
IDT® 8-OUTPUT DB800ZL  
13  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Marking Diagram  
ICS  
ZXL0831AL  
YYWW  
COO  
LOT  
Notes:  
1. “L” denotes RoHS compliant package.  
2. “YYWW” is the last two digits of the year and week that the part was assembled.  
3. “COO”: country of origin.  
4. “LOT” denotes the lot number.  
IDT® 8-OUTPUT DB800ZL  
14  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Package Outline and Package Dimensions (NDG48), Use Option 1  
IDT® 8-OUTPUT DB800ZL  
15  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Package Outline and Package Dimensions (NDG48), cont. Use Epad 4.2mm Sq.  
IDT® 8-OUTPUT DB800ZL  
16  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
Ordering Information  
Part / Order Number Shipping Package  
Package  
48-VFQFN  
48-VFQFN  
Temperature  
0 to +70°C  
0 to +70°C  
9ZXL0831AKLF  
9ZXL0831AKLFT  
Trays  
Tape and Reel  
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
“A” is the device revision designator (will not correlate with the datasheet revision).  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes  
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No  
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications  
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not  
recommended without additional processing by IDT. IDT does not authorize or warrant any IDT product for use in life support devices or  
critical medical instruments.  
Revision History  
Rev.  
A
B
C
Issuer Issue Date Description  
Page #  
Various  
1
RDW  
RDW  
RDW  
10/21/2013 Updated electrical tables with Char data. Move to final  
7/30/2014 Changed DB1200ZL reference in "general description" to DB800ZL  
7/1/2015 Updated POD drawing.  
15  
1. Updated QPI references to QPI/UPI  
11/20/2015  
D
E
RDW  
RDW  
1,5  
17  
2. Updated DIF_IN table to match PCI SIG specification, no silicon change  
8/16/2016 Corrected typos in package ordering information  
IDT® 8-OUTPUT DB800ZL  
17  
9ZXL0831  
REV E 081616  
9ZXL0831  
8-OUTPUT DB800ZL  
SYNTHESIZERS  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
800-345-7015  
408-284-8200  
Fax: 408-284-2775  
For Tech Support  
www.idt.com/go/support  
Corporate Headquarters  
Integrated Device Technology, Inc.  
www.idt.com  
© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated  
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or  
registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
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