WV3HG2128M72AER-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Parameter
Symbol Condition
553
403
Units
Operating one
device bank active-
precharge current;
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is HIGH
ICC0 between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
2,284
2,284
mA
Operating one device
bank active-read-
precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN
ICC1 (ICC), tRCD = tRCD (ICC); CKE is HIGH, S# is HIGH between valid commands; Address
2,554
2,554
mA
bus inputs are SWITCHING; Data pattern is same as ICC4W
.
Precharge power-
down current;
All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
ICC2P
ICC2Q
ICC2N
988
988
mA
mA
mA
mA
mA
Precharge quiet
standby current;
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
1,780
1,960
1,780
1,132
1,780
1,960
1,780
1,132
Precharge standby
current;
All device banks idle; tCK = tCK (ICC); CKE is HIGH, S# is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Fast PDN Exit
All device banks open; tCK = tCK (ICC); CKE is LOW; Other
MR[12] = 0
Active power-down
current;
ICC3P control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Slow PDN Exit
MR[12] = 1
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC); CKE is
ICC3N HIGH, S# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Active standby
current;
2,500
2,824
2,500
2,644
mA
mA
All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC), AL = 0; tCK
=
Operating burst write
current;
ICC4W tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (ICC), AL
Operating burst read
current;
= 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
ICC4R
2,914
2,734
mA
SWITCHING.
tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE is HIGH, CS#
ICC5 is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
Self refresh current;
5,740
288
5,740
288
mA
mA
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING;
ICC6
Data bus inputs are FLOATING.
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC), AL = tRCD (ICC)-1
x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = tRCD(ICC); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See ICC7 Conditions for detail.
Operating device
bank interleave read
current;
ICC7
4,804
4,804
mA
NOTE:
I
CC specification is based on SAMSUNG components. Other DRAM manufactures speicification may be different.
* Value calculated as on module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
November 2006
Rev. 1
6
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