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5V995PFGI

型号：

5V995PFGI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

14 页

PDF大小：

308 K

下载PDF手册
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER  
TURBOCLOCK™ II  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014  
IDT5V995  
FEATURES:  
DESCRIPTION:  
• Ref input is 5V tolerant  
The IDT5V995 is a high fanout 3.3V PLL based clock driver  
intended for high performance computing and data-communica-  
tions applications. A key feature of the programmable skew is the  
ability of outputs to lead or lag the REF input signal. The  
IDT5V995 has eight programmable skew outputs in four banks of  
2. Skew is controlled by 3-level input signals that may be hard-  
wired to appropriate HIGH-MID-LOW levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 185ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchroniza-  
tion:  
Excellent for DSP applications  
• Synchronous output enable  
• Input frequency: 2MHz to 200MHz  
• Output frequency: 6MHz to 200MHz  
• 3-level inputs for skew and PLL range control  
• 3-level inputs for feedback divide selection multiply /  
divide ratios of (1-6, 8, 10, 12) / (2, 4)  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Power-down mode  
The feedback input allows divide-by-functionality from 1 to 12  
through the use of the DS[1:0] inputs. This provides the user with  
frequency multiplication from 1 to 12 without using divided  
outputs for feedback.  
When the sOE pin is held low, all the outputs are synchro-  
nously enabled. However, if sOE is held high, all the outputs  
except 2Q0 and 2Q1 are synchronously disabled. The LOCK  
output asserts to indicate when Phase Lock has been achieved.  
Furthermore, when PE is held high, all the outputs are synchro-  
nized with the positive edge of the REF clock input. When PE is  
held low, all the outputs are synchronized with the negative edge  
of REF. The IDT5V995 has LVTTL outputs with 12mA balanced  
drive outputs.  
• Lock indicator  
• Available in TQFP package  
• Not Recommended for New Design  
PE  
TEST  
LOCK  
FS  
PD  
sOE  
FUNCTIONAL BLOCK
3
3
REF  
PLL  
/ N  
FB  
3
3
DS1:0  
3
3
1Q0  
1Q1  
Skew  
Select  
1F1:0  
2F1:0  
3F1:0  
4F1:0  
3
3
2Q0  
2Q1  
Skew  
Select  
3
3
3Q0  
3Q1  
Skew  
Select  
3
3
4Q0  
4Q1  
Skew  
Select  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
1
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Description  
Max  
–0.5 to +4.6  
–0.5 to VDD+0.5  
–0.5 to +5.5  
0.7  
Unit  
V
VDDQ, VDD Supply Voltage to Ground  
VI  
DC Input Voltage  
REF Input Voltage  
Maximum Power  
Dissipation  
V
42  
38 37 36  
34  
44 43  
41 40 39  
35  
V
4F1  
sOE  
PD  
1
1F0  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
TA = 85°C  
TA = 55°C  
W
2
DS1  
1.1  
DS0  
3
TSTG  
Storage Temperature Range  
–65 to +150  
°C  
LOCK  
VDDQ  
VDDQ  
1Q0  
PE  
4
NOTE:  
VDDQ  
VDDQ  
4Q1  
5
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-  
manent damage to the device. These are stress ratings only, and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-  
tions for extended periods may affect device reliability.  
6
7
1Q1  
4Q0  
8
GND  
GND  
GND  
GND  
GND  
GND  
9
10  
11  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
12 13 14 15 16 17 18 19 20 21 22  
Parameter Description  
Typ. Max.  
Unit  
CINInput Capacitance  
5
7
pF  
NOTE:  
1. Capacitance applies to all inputs except TEST, FS, nF[1:0], and DS[1:0].  
TQFP  
TOP VIEW  
PIN DESCRIPTION  
Pin Name  
Type  
Description  
REF  
FB  
TEST (1)  
IN  
IN  
IN  
Reference Clock Input  
Feedback Input  
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control  
Summary Table) remain in effect. Set LOW for normal operation.  
sOE(1)  
IN  
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H) - 2Q0 and  
2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0]  
pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation (has internal pull  
down).  
PE  
IN  
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of  
the  
reference clock (has internal pull-up).  
nF[1:0]  
FS  
IN  
IN  
3-level inputs for selecting 1 of 9 skew taps or frequency functions  
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)  
Four banks of two outputs with programmable skew  
nQ[1:0]  
DS[1:0]  
PD  
OUT  
IN  
3-level inputs for feedback divider selection  
IN  
Power down control. Shuts off entire chip when LOW (has internal pull-up).  
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized  
LOCK  
OUT  
to  
the inputs. (For more information on application specific use of the LOCK pin, please see AN237.)  
Power supply for output buffers  
VDDQ  
PWR  
VDD  
PWR  
Power supply for phase locked loop, lock output, and other internal circuitry  
NOTE: 1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in  
effect unless nF[1:0] = LL.  
GND  
PWR  
Ground  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
2
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
PROGRAMMABLE SKEW  
Output skew with respect to the REF input is adjustable to  
compensate for PCB trace delays, backplane propagation de-  
lays or to accommodate requirements for special timing rela-  
tionships between clocked components. Skew is selectable as  
a multiple of a time unit (tu) which ranges from 625ps to 1.3ns  
(see Programmable Skew Range and Resolution Table). There  
are nine skew configurations available for each output pair.  
These configurations are chosen by the nF1:0 control pins. In  
order to minimize the number of control pins, 3-level inputs  
(HIGH-MID-LOW) are used, they are intended for but not re-  
stricted to hard-wiring. Undriven 3-level inputs default to the  
MID level. Where programmable skew is not a requirement,  
the control pins can be left open for the zero skew default  
setting. The Control Summary Table shows how to select spe-  
cific skew taps by using the nF1:0 control pins.  
EXTERNAL FEEDBACK  
By providing external feedback, the IDT5V995 gives users  
flexibility with regard to skew adjustment. The FB signal is  
compared with the input REF signal at the phase detector in  
order to drive the VCO. Phase differences cause the VCO of  
the PLL to adjust upwards or downwards accordingly.  
An internal loop filter moderates the response of the VCO to  
the phase detector. The loop filter transfer function has been  
chosen to provide minimal jitter (or frequency variation) while  
still providing accurate responses to input frequency changes.  
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE  
FS = LOW  
FS = MID  
FS = HIGH  
Comments  
Timing Unit Calculation (tU)  
1/(32 x FNOM)  
24 to 50MHz  
1/(16 x FNOM)  
48 to 100MHz  
1/(8 x FNOM)  
VCO Frequency Range (FNOM)(1,2)  
Skew Adjustment Range(3)  
Max Adjustment:  
96 to 200MHz  
±7.8125ns  
±7.8125ns  
±7.8125ns  
ns  
±67.5°  
±135°  
±270°  
±75%  
Phase Degrees  
% of Cycle Time  
±18.75%  
±37.5%  
Example 1, FNOM = 25MHz  
Example 2, FNOM = 37.5MHz  
Example 3, FNOM = 50MHz  
Example 4, FNOM = 75MHz  
Example 5, FNOM = 100MHz  
Example 6, FNOM = 150MHz  
tU = 1.25ns  
—
—
—
tU = 0.833ns  
—
—
tU = 0.625ns  
tU = 1.25ns  
tU = 0.833ns  
tU = 0.625ns  
—
—
—
—
—
tU = 1.25ns  
tU = 0.833ns  
Example 7, FNOM = 200MHz  
—
—
tU = 0.625ns  
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs  
when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be FNOM when the output connected to FB is undivided and DS[1:0] = MM. The  
frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the FB input and setting DS[1:0] = MM.  
Using the DS[1:0] inputs allows a different method for frequency multiplication (see Divide Selection Table).  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU  
skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to  
output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
3
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
DIVIDE SELECTION TABLE  
DS [1:0]  
FB Divide-by-n  
Permitted Output Divide-by-n connected to FB(1)  
LL  
LM  
LH  
2
3
1 or 2  
1
4
1, 2, or 4  
1 or 2  
1, 2, or 4  
1 or 2  
1 or 2  
1
ML  
MM  
MH  
HL  
5
1
6
8
HM  
10  
HH  
12  
1
NOTE: 1.Permissible output division ratios connected to FB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an  
undivided output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12).  
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS  
nF1:0  
LL (1)  
LM  
Skew (Pair #1, #2)  
Skew (Pair #3)  
Divide by 2  
–6tU  
Skew (Pair #4)  
Divide by 2  
–6tU  
–4tU  
–3tU  
LH  
–2tU  
–4tU  
–4tU  
ML  
–1tU  
–2tU  
–2tU  
MM  
MH  
HL  
Zero Skew  
1tU  
Zero Skew  
2tU  
Zero Skew  
2tU  
2tU  
4tU  
4tU  
HM  
3tU  
6tU  
6tU  
HH  
4tU  
Divide by 4  
Inverted (2)  
NOTES: 1. LL DISABLES OUTPUTS IF TEST = MID AND SOE = HIGH.  
2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.  
RECOMMENDED OPERATING RANGE  
Symbol  
VDD/VDDQ  
TA  
Description  
Min.  
3
Typ.  
3.3  
Max.  
Unit  
V
Power Supply Voltage  
Ambient Operating Temperature  
3.6  
-40  
+25  
+85  
°C  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
4
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
INPUT TIMING REQUIREMENTS  
Symbol  
tR, tF  
tPWC  
DH  
Description(1)  
Maximum input rise and fall times, 0.8V to 2V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
2
Max.  
10  
Unit  
ns/V  
ns  
—
10  
2
90  
%
FS = LOW  
FS = MID  
FS = HIGH  
50  
FREF  
Reference clock input frequency  
4
100  
200  
MHz  
8
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
5
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
FNOM  
VCO Frequency Range  
REF Pulse Width HIGH  
See Programmable Skew Range and Resolution Table  
(1)  
tRPWH  
tRPWL  
tU  
2
2
—
—
—
ns  
ns  
(1)  
REF Pulse Width LOW  
—
Programmable Skew Time Unit  
See Control Summary Table  
(2,3)  
tSKEWPR  
tSKEW0  
tSKEW1  
tSKEW2  
tSKEW3  
tSKEW4  
tDEV  
Zero Output Matched-Pair Skew (xQ0, xQ1)  
—
—
50  
0.1  
0.1  
0.2  
0.15  
0.3  
—
185  
0.25  
0.25  
0.5  
0.5  
0.9  
0.75  
0.25  
0.25  
0.5  
0.7  
1
ps  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(4)  
Zero Output Skew (All Outputs)  
(5)  
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)  
—
(5)  
(2)  
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)  
—
(5)  
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)  
—
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)  
—
(2,6)  
Device-to-Device Skew  
—
(7)  
(φ)1-3  
Static Phase Offset (FS = L, M, H) (FB Divide-by-n = 1, 2, 3)  
−0.25  
−0.25  
−0.5  
−0.7  
−1  
−1  
—
—
(7)  
(φ)H  
Static Phase Offset (FS = H)  
—
(7)  
t(φ)M  
Static Phase Offset (FS = M)  
—
(7)  
t(φ)L1-6  
t(φ)L8-12  
tODCV  
tPWH  
Static Phase Offset (FS = L) (FB Divide-by-n = 1, 2, 3, 4, 5, 6)  
—
(7)  
Static Phase Offset (FS = L) (FB Divide-by-n = 8, 10, 12)  
—
Output Duty Cycle Variation from 50%  
0
1
(8)  
Output HIGH Time Deviation from 50%  
—
1.5  
2
(9)  
tPWL  
Output LOW Time Deviation from 50%  
—
—
tORISE  
tOFALL  
tLOCK  
tCCJH  
Output Rise Time  
Output Fall Time  
0.15  
0.15  
—
0.7  
0.7  
—
1.5  
1.5  
0.5  
100  
(10,11)  
PLL Lock Time  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
—
—
(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)  
tCCJHA  
tCCJM  
tCCJL  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
—
—
—
—
—
—
150  
150  
200  
(divide by 1 output frequency, FS = H, FB divide-by-n=any)  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
(divide by 1 output frequency, FS = M)  
ps  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
(divide by 1 output frequency, FS = L, FREF > 3MHz)  
tCCJLA  
Cycle-to-Cycle Output Jitter (peak-to-peak)  
—
—
300  
(divide by 1 output frequency, FS = L, FREF < 3MHz)  
Notes on next page  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
6
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
NOTES:  
1. Refer to Input Timing Requirements table for more detail.  
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load.  
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
4. tSK(0) is the skew between outputs when they are selected for 0tU.  
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).  
Test condition: nF0:1=MM is set on unused outputs.  
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)  
7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB.  
8. Measured at 2V.  
9. Measured at 0.8V.  
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
11. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
7
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
AC TEST LOADS AND WAVEFORMS  
VDDQ  
150  
150  
Output  
Output  
20pF  
20pF  
For LOCK output  
For all other outputs  
tOFALL  
tORISE  
2.0V  
VTH = 1.5V  
0.8V  
tPWH  
tPWL  
LVTTL Output Waveform  
1ns  
1ns  
3.0V  
2.0V  
VTH = 1.5V  
0.8V  
0V  
LVTTL Input Test Waveform  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
8
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
AC TIMING DIAGRAM  
tRPWL  
tREF  
tRPWH  
REF  
FB  
Q
t(  
tODCV  
tODCV  
tCCJH, HA,  
M, L, LA  
tSKEWPR  
tSKEW0, 1  
tSKEWPR  
tSKEW0, 1  
OTHER Q  
tSKEW2  
tSKEW2  
INVERTED Q  
tSKEW3, 4  
tSKEW3, 4  
tSKEW3, 4  
tSKEW2, 4  
REF DIVIDED BY 2  
tSKEW1, 3, 4  
REF DIVIDED BY 4  
NOTES:  
PE:  
The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF,  
and the positive edges of the divide-by-2 and the divide-by-4 signals align.  
Skew:  
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with  
75Ω to VDDQ/2.  
tSKEWPR:  
tSKEW0:  
tDEV:  
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
The skew between outputs when they are selected for 0tU  
.
The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)  
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.  
tODCV:  
tPWH is measured at 2V.  
tPWL is measured at 0.8V.  
tORISE and tOFALL are measured between 0.8V and 2V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
9
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
PACKAGE OUTLINE & DIMENSIONS -Y SUFFIX FOR 44 LEAD TQFP  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
10  
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
11  
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
ORDERING INFORMATION  
IDT  
XXXXX  
XX  
X
Device Type Package Process  
I
-40ºC to +85ºC (Industrial)  
TQFP - Green  
PFG  
3.3V Programmable Skew PLL Clock Driver  
TurboClock II  
5V995  
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
12  
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V995  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
REVISION HISTORY SHEET  
Rev  
Table  
Page  
Description of Change  
Date  
A
10-11 Added Package Outline & Dimensions.  
5/6/09  
Product Discontinuation Notice - Last Time Buy Expires October 28, 2014  
PDN# CQ-13-02  
12/20/13  
B
1
IDT™ / ICS™ PLL CLOCK DRIVER TURBOCLOCK™ II  
13  
IDT5V995 REV. B DECEMBER 20, 2013  
IDT5V955  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ II  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
Corporate Headquarters  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
netcom@idt.com  
+480-763-2056  
www.IDT.com/go/contactIDT  
United States  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of  
Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be  
trademarks or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
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