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5V926APGI

型号:

5V926APGI

品牌:

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数:

6 页

PDF大小:

94 K

Single Output Clock Generator  
IDT5V926A  
DATA SHEET  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014  
FEATURES:  
DESCRIPTION:  
• 3V to 3.6V operating voltage  
The IDT5V926A is a low-cost, low skew, low jitter, and  
high-performance clock multiplier with a reference clock  
from either a lower frequency crystal or clock input. It has  
been specially designed to interface with Gigabit Ethernet  
and Fast Ethernet applications by providing a 125MHz  
clock from 25MHz input. It can be programmed to provide  
output frequencies ranging from 48MHz to 160MHz, with  
input frequencies ranging from 6MHz to 80MHz.  
The IDT5V926A includes an internal RC filter that pro-  
vides excellent jitter characteristics and eliminates the  
need for external components. When using the optional  
crystal input, the device accepts a 10 - 40MHz fundamental  
mode crystal with a maximum equivalent series resistance  
of 50Ω.  
• 48MHz to 160MHz output frequency range  
• Input from fundamental crystal oscillator or external  
source  
• Internal PLL feedback (loading the feedback output  
relative to the other outputs, will adjust the propagation  
delay between REF inputs and outputs)  
• Select inputs (S[1:0]) for FB divide selection (multiply  
ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8)  
• Low jitter  
• PLL bypass for testing and power-down control  
(S1 = H, S0 = H, powers part down <500µA)  
• Available in TSSOP package  
• Pin and function compatible to IDT5V926  
• Use replacement parts: 840004AG or  
8T49004A-dddNLGI  
APPLICATIONS:  
• Gigabit ethernet  
• Router  
• Network switches  
• SAN  
• Instrumentation  
• Fibre channel  
FUNCTIONAL BLOCK DIAGRAM  
OE  
VCO DIVIDE  
1/N  
PHASE  
DETECTOR  
CHARGE  
PUMP  
LOOP  
FILTER  
VCO  
QOUT  
0
1
X1/REF  
CRYSTAL  
OSCILLATOR  
QREF  
X2  
SELECT MODE  
S1 S0  
REFE  
IDT5V926A REVISION B DECEMBER 18, 2013  
1
©2013 Integrated Device Technology, Inc.  
IDT5V926A Data Sheet  
SINGLE OUTPUT CLOCK GENERATOR  
ABSOLUTE MAXIMUM RATINGS(1)  
PIN CONFIGURATION  
Symbol  
Parameter  
Max.  
-0.5 to +4.6  
-0.5 to +4.6  
±50  
Unit  
V
V
DD/  
I
V
DDQ  
Supply Voltage to Ground  
Input Voltage  
V
S0  
1
2
3
4
5
6
7
8
REFE  
X1/REF  
X2  
16  
15  
14  
13  
12  
11  
10  
V
S1  
IO  
Output Current  
mA  
°C  
°C  
OE  
TSTG  
Storage Temperature  
Junction Temperature  
-65 to +150  
150  
VDD  
GND  
VDDQ  
GND  
QOUT  
VDDQ  
VDDQ  
GND  
QREF  
VDDQ  
TJ  
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
9
TSSOP  
TOP VIEW  
PIN DESCRIPTION  
Pin Name Type Description  
S[1:0]  
I
I
Three level divider/mode select pins. Float to MID.  
Output enable bar. Outputs Qout and QREF are in a high-impedance state when  
HIGH. Set OE LOW for normal operation (has internal pull-down).  
OE  
I
QREF enable input. QREF stopped LOW when HIGH. When set REFE LOW, the  
QREF is enabled (has internal pull-down).  
REFE  
X1/REF  
X2  
I
I
Crystal oscillator input or clock input.  
Crystal oscillator output. Leave unconnected for clock input.  
Output at N*REF frequency.  
CRYSTAL SPECIFICATION  
QOUT  
QREF  
VDDQ  
VDD  
O
O
The crystal oscillators should be fundamental mode quartz  
crystals: overtone crystals are not suitable. Crystal frequency  
should be specified for parallel resonance with 50Ω maximum  
equivalent series resonance. Crystal tuning capacitors should  
be connected from X1/REF to GND and from X2 to GND.  
Output at REF frequency.  
PWR Power supply for the device outputs. Connect to VDD on PCB.  
PWR Power supply for the device core and inputs. Connect to VDD on PCB.  
PWR Ground supply.  
GND  
DIVIDE SELECTION TABLE(1)  
S1  
S0  
Divide-by-N Value  
Mode  
PLL  
L
L
2
3
L
M
H
L
PLL  
L
4
PLL  
M
M
M
H
H
H
4.25  
5
PLL  
M
H
L
PLL  
6
PLL  
6.25  
8
PLL  
M
H
PLL  
TEST  
TEST (2)  
NOTES:  
1. H = HIGH, M = MID, L = LOW  
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.  
DT5V926A REVISION B DECEMBER 18, 2013  
2
©2013 Integrated Device Technology, Inc.  
IDT5V926A Data Sheet  
SINGLE OUTPUT CLOCK GENERATOR  
COMMON OUTPUT FREQUENCY EXAMPLES (MHz)  
Output  
48  
24  
LL  
60  
64  
16  
LH  
72  
75  
80  
10  
90  
15  
100  
20  
Input  
10  
12  
25  
FB Divide Selection S[1:0]  
MH  
MH  
LM  
HM  
MH  
MM  
Output  
Input  
106.25  
17  
106.25  
25  
120  
15  
125  
20  
125  
25  
125  
62.5  
LL  
150  
25  
155.52  
19.44  
HM  
FB Divide Selection S[1:0]  
HL  
ML  
HM  
HL  
MM  
MH  
OPERATING CONDITIONS  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
VDD/VDDQ  
Power Supply Voltage  
OperatingTemperature  
3
3.3  
25  
5
3.6  
V
TA  
- 40  
+85  
°C  
pF  
CIN  
Input Capacitance, OE, F = 1MHz, VIN = 0V, TA = 25°C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Following Conditions Apply Unless Otherwise Specified:  
Industrial: TA = –40°C to +85°C, VDD/VDDQ = 3.3V ±0.3V  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
2
Max  
Unit  
VIL  
InputLOWVoltage  
0.8  
V
V
V
V
V
VIH  
Input HIGH Voltage  
Input HIGH Voltage  
InputMIDVoltage  
InputLOWVoltage  
2
VDD - 0.6  
VDD/2 - 0.3  
VIHH  
VIMM  
VILL  
3-levelinputonly  
3-levelinputonly  
3-levelinputonly  
VIN = VDD  
VDD/2 + 0.3  
0.6  
+200  
+50  
HIGH Level  
MID Level  
LOW Level  
OE, REFE  
X1/REF  
I3  
3-Level Input DC Current, S[1:0]  
Input HIGH Current  
VIN = VDD/2  
- 50  
μA  
VIN = GND  
-200  
IIH  
VIN = VDD  
100  
4
μA  
mA  
V
VIN = VDD, S[1:0] = HH  
IOL = 12mA  
VOL  
OutputLOWVoltage  
Output HIGH Voltage  
0.4  
VOH  
IOH = -12mA  
2.4  
V
DT5V926A REVISION B DECEMBER 18, 2013  
3
©2013 Integrated Device Technology, Inc.  
IDT5V926A Data Sheet  
SINGLE OUTPUT CLOCK GENERATOR  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions (1)  
Min.  
Typ.  
Max  
Unit  
IDD_PD  
Power Down Current  
VDD = Max.  
500  
μA  
S[1:0] = HH  
OE = L; X1/REF = L  
All outputs unloaded  
ΔIDD  
Supply Current per Input  
Dynamic Supply Current  
VDD = Max., VIN = 3V  
VDD = 3.6V  
30  
50  
μA  
IDD  
mA  
S[1:0] = LL  
OE = L  
FOUT = 160MHz  
All outputs unloaded  
NOTE:  
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.  
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
tR,  
tF  
Rise Time, Fall Time  
0.8V to 2V  
Q
OUT  
REF  
0.7  
1.5  
2.0  
ns  
Q
0.7  
d
T
Output/Duty Cycle  
VT = VDDQ/2  
Q
OUT < 125MHz  
OUT > 125MHz  
45  
44  
55  
56  
%
Q
QREF  
40  
60  
100  
90  
F
F
F
OUT = 106.25MHz  
t
J
Cycle - Cycle Jitter  
Output Frequency  
OUT = 125MHz  
ps  
OUT = 155.52MHz  
125  
160  
f
OUT  
48  
MHz  
INPUT TIMING REQUIREMENTS  
Symbol  
tR, tF  
tPWC  
DH  
Description(1)  
Min.  
Max.  
10  
Unit  
ns/V  
ns  
Maximum input rise and fall time, 0.8V to 2V(2)  
Input clock pulse, HIGH or LOW(2)  
Input duty cycle(2)  
2
10  
90  
%
fOSC  
fIN  
XTALoscillator frequency  
Input frequency(2)  
10  
40  
MHz  
MHz  
48/N  
160/N  
NOTES:  
1. Where pulse width implied by DH is less than the tPWC limit, tPWC limit applies.  
2. When using a clock input.  
DT5V926A REVISION B DECEMBER 18, 2013  
4
©2013 Integrated Device Technology, Inc.  
IDT5V926A Data Sheet  
SINGLE OUTPUT CLOCK GENERATOR  
PARAMETER MEASUREMENT INFORMATION  
1.65V 0.15V  
SCOPE  
VDD,  
VDDQ  
QOUT  
Qx  
LVCMOS  
GND  
tcycle n  
tcycle n+1  
tjit(cc) = tcycle n – tcycle n+1  
|
|
1000 Cycles  
-1.65V 0.15V  
3.3V CORE/3.3V OUTPUT LOAD ACTEST CIRCUIT  
CYCLE-TO-CYCLE JITTER  
VDD  
2V  
2V  
2
QREF,  
QOUT  
tPW  
0.8V  
0.8V  
tPERIOD  
QREF,  
QOUT  
tR  
tF  
tPW  
x 100%  
odc =  
tPERIOD  
OUTPUT RISE/FALLT IME  
OUTPUT DUTY CYCLE/PULSEWIDTH/PERIOD  
DT5V926A REVISION B DECEMBER 18, 2013  
5
©2013 Integrated Device Technology, Inc.  
IDT5V926A  
SINGLE OUTPUT CLOCK GENERATOR  
DATASHEET  
ORDERING INFORMATION  
X
X
IDT  
XXXX  
Package  
Process  
Device Type  
I
-40°C to +85C° (Industrial)  
PG  
PGG  
Thin Shrink Small Outline Package  
TSSOP - Green  
Single Output Clock Generator  
5V926A  
REVISIONHISTORY  
12/18/13  
Product Discontinuation Notice - Last Time Buy Expires October 28, 2014,  
PDN# CQ-13-02  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
netcom@idt.com  
Corporate Headquarters  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
+480-763-2056  
www.IDT.com/go/contactIDT  
United States  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are  
trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and  
marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.  
Printed in USA  
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