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5V991A-7JI

型号：

5V991A-7JI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

8 页

PDF大小：

74 K

下载PDF手册
RANGES  
IDT5V991A  
NRND  
3.3V PROGRAMMABLE SKEW  
PLL CLOCK DRIVER  
TURBOCLOCK™  
FEATURES:  
DESCRIPTION:  
• REF is 5V tolerant  
The IDT5V991A is a high fanout 3.3V PLL based clock driver  
intended for high performance computing and data-communications  
applications. A key feature of the programmable skew is the ability of  
outputs to lead or lag the REF input signal. The IDT5V991A has eight  
programmable skew outputs in four banks of 2. Skew is controlled by  
3-level input signals that may be hard-wired to appropriate HIGH-MID-  
LOW levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Output frequency: 3.75MHz to 85MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
When the GND/sOE pin is held low, all the outputs are synchro-  
nously enabled. However, if GND/sOE is held high, all the outputs  
except 3Q0 and 3Q1 are synchronously disabled.  
• 3 skew grades:  
IDT5V991A-2: tSKEW0<250ps  
IDT5V991A-5: tSKEW0<500ps  
IDT5V991A-7: tSKEW0<750ps  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <200ps peak-to-peak  
• Available in 32-pin PLCC Package  
• Not Recommended for New Design  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronized with the positive edge of the REF clock input. When  
VCCQ/PE is held low, all the outputs are synchronized with the negative  
edge of REF. Both devices have LVTTL outputs with 12mA balanced  
drive outputs.  
FUNCTIONAL BLOCK DIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
1F1:0  
2F1:0  
3F1:0  
4F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
3
3
FS  
4Q0  
4Q1  
Skew  
Select  
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
NOVEMBER 7, 2013  
1
c
2013 Integrated Device Technology, Inc.  
DSC 5963/3  
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Description  
Supply Voltage to Ground  
DC Input Voltage  
Max  
–0.5 to +7  
–0.5 to VCC+0.5  
–0.5 to +5.5  
150  
Unit  
V
VI  
V
4
3
2
1 32 31 30  
2F0  
REF Input Voltage  
V
3F1  
4F0  
4F1  
5
6
29  
28  
27  
26  
25  
24  
23  
22  
21  
TJ  
Junction Temperature  
Storage Temperature  
°C  
°C  
GND/sOE  
1F1  
TSTG  
–65 to +150  
7
NOTE:  
1F0  
8
VCCQ/PE  
VCCN  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-  
manent damage to the device. These are stress ratings only, and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-  
tions for extended periods may affect device reliability.  
32-PLCC  
9
VCCN  
1Q0  
4Q1  
4Q0  
10  
11  
12  
13  
1Q1  
GND  
GND  
GND  
GND  
14 15 16 17 18 19 20  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
Parameter Description  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
5
7
pF  
PLCC  
TOP VIEW  
NOTE:  
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.  
PIN DESCRIPTION  
Pin Name  
REF  
Type  
IN  
Description  
Reference Clock Input  
Feedback Input  
FB  
IN  
TEST (1)  
IN  
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control  
Summary Table) remain in effect. Set LOW for normal operation.  
(1)  
GND/ sOE  
IN  
IN  
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be  
used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins  
act as output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation.  
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of  
the reference clock.  
VCCQ/PE  
nF[1:0]  
FS  
IN  
3-level inputs for selecting 1 of 9 skew taps or frequency functions  
IN  
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)  
Four banks of two outputs with programmable skew  
nQ[1:0]  
VCCN  
OUT  
PWR  
PWR  
PWR  
Power supply for output buffers  
VCCQ  
Power supply for phase locked loop and other internal circuitry  
GND  
Ground  
NOTE:  
1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect  
unless nF[1:0] = LL.  
PROGRAMMABLE SKEW  
Output skew with respect to the REF input is adjustable to com- by the nF1:0 control pins. In order to minimize the number of control  
pensate for PCB trace delays, backplane propagation delays or to pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for  
accommodate requirements for special timing relationships between but not restricted to hard-wiring. Undriven 3-level inputs default to  
clocked components. Skew is selectable as a multiple of a time unit the MID level. Where programmable skew is not a requirement, the  
tU which is of the order of a nanosecond (see PLL Programmable control pins can be left open for the zero skew default setting. The  
Skew Range and Resolution Table). There are nine skew configura- Control Summary Table shows how to select specific skew taps by  
tions available for each output pair. These configurations are chosen using the nF1:0 control pins.  
2
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
EXTERNAL FEEDBACK  
By providing external feedback, the IDT5V991A gives users flex-  
ibility with regard to skew adjustment. The FB signal is compared  
with the input REF signal at the phase detector in order to drive the  
VCO. Phase differences cause the VCO of the PLL to adjust upwards  
or downwards accordingly.  
An internal loop filter moderates the response of the VCO to the  
phase detector. The loop filter transfer function has been chosen to  
provide minimal jitter (or frequency variation) while still providing ac-  
curate responses to input frequency changes.  
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE  
FS = LOW  
1/(44 x FNOM)  
15 to 35MHz  
FS = MID  
1/(26 x FNOM)  
25 to 60MHz  
FS = HIGH  
1/(16 x FNOM)  
40 to 85 MHz  
Comments  
Timing Unit Calculation (tU)  
VCO Frequency Range (FNOM)(1,2)  
Skew Adjustment Range(3)  
Max Adjustment:  
±9.09ns  
±49º  
±9.23ns  
±83º  
±9.38ns  
±135º  
ns  
Phase Degrees  
% of Cycle Time  
±14%  
±23%  
±37%  
Example 1, FNOM = 15MHz  
Example 2, FNOM = 25MHz  
Example 3, FNOM = 30MHz  
Example 4, FNOM = 40MHz  
Example 5, FNOM = 50MHz  
Example 6, FNOM = 80MHz  
tU = 1.52ns  
tU = 0.91ns  
tU = 0.76ns  
—
—
—
tU = 1.54ns  
tU = 1.28ns  
tU = 0.96ns  
tU = 0.77ns  
—
—
—
tU = 1.56ns  
tU = 1.25ns  
tU = 0.78ns  
—
—
NOTES:  
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input  
frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.  
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher  
outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided.  
The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input.  
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed  
output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and  
4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.  
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS  
nF1:0  
LL(1)  
LM  
Skew (Pair #1, #2)  
Skew (Pair #3)  
Divide by 2  
–6tU  
Skew (Pair #4)  
Divide by 2  
–6tU  
–4tU  
–3tU  
LH  
–2tU  
–4tU  
–4tU  
ML  
–1tU  
–2tU  
–2tU  
MM  
MH  
HL  
Zero Skew  
1tU  
Zero Skew  
2tU  
Zero Skew  
2tU  
2tU  
4tU  
4tU  
HM  
HH  
3tU  
6tU  
6tU  
Inverted(2)  
4tU  
Divide by 4  
NOTES:  
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.  
2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ/PE = LOW.  
3
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
RECOMMENDED OPERATING RANGE  
IDT5V991A-2, -5, -7  
(Industrial)  
IDT5V991A-2  
(Commercial)  
Symbol  
Vcc  
Description  
Min.  
3
Max.  
3.6  
Min.  
Max.  
3.6  
Unit  
V
Power Supply Voltage  
Ambient Operating Temperature  
3
0
TA  
-40  
+85  
+70  
°C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Conditions  
Guaranteed Logic HIGH (REF, FB Inputs Only)  
Guaranteed Logic LOW (REF, FB Inputs Only)  
3-Level Inputs Only  
Min.  
Max.  
Unit  
V
VIH  
Input HIGH Voltage  
2
—
—
0.8  
VIL  
Input LOW Voltage  
Input HIGH Voltage(1)  
Input MID Voltage(1)  
Input LOW Voltage(1)  
Input Leakage Current  
(REF, FB Inputs Only)  
V
VIHH  
VIMM  
VILL  
IIN  
VCC−0.6  
VCC/2−0.3  
—
—
V
3-Level Inputs Only  
VCC/2+0.3  
0.6  
V
3-Level Inputs Only  
V
VIN = VCC or GND  
—
±5  
µA  
VCC = Max.  
VIN = VCC  
HIGH Level  
MID Level  
LOW Level  
—
—
—
—
—
2.4  
—
±200  
±50  
I3  
3-Level Input DC Current (TEST, FS, nF1:0)  
VIN = VCC/2  
µA  
VIN = GND  
±200  
±100  
±100  
—
IPU  
IPD  
Input Pull-Up Current (VCCQ/PE)  
Input Pull-Down Current (GND/sOE)  
Output HIGH Voltage  
VCC = Max., VIN = GND  
VCC = Max., VIN = VCC  
VCC = Min., IOH = −12mA  
VCC = Min., IOL = 12mA  
µA  
µA  
V
VOH  
VOL  
Output LOW Voltage  
0.55  
V
NOTE:  
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the  
outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
VCC = Max., TEST = MID, REF = LOW,  
VCCQ/PE = LOW, GND/sOE = LOW  
All outputs unloaded  
Typ.(2)  
Max.  
Unit  
ICCQ  
Quiescent Power Supply Current  
8
25  
mA  
ΔICC  
ICCD  
ITOT  
Power Supply Current per Input HIGH  
Dynamic Power Supply Current per Output  
Total Power Supply Current  
VCC = Max., VIN = 3V  
1
30  
90  
—
—
—
μA  
VCC = Max., CL = 0pF  
55  
29  
42  
76  
μA/MHz  
VCC = 3.3V, FREF = 20MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 33MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 66MHz, CL = 160pF(1)  
mA  
NOTE:  
1. For eight outputs, each loaded with 20pF.  
INPUT TIMING REQUIREMENTS  
Symbol  
tR, tF  
tPWC  
DH  
Description (1)  
Maximum input rise and fall times, 0.8V to 2V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
Max.  
Unit  
ns/V  
ns  
10  
—
90  
85  
3
10  
%
REF  
Reference Clock Input  
3.75  
MHz  
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
4
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE  
IDT5V991A-2  
IDT5V991A-5  
IDT5V991A-7  
Typ.  
Symbol Parameter  
Min.  
Typ.  
Max.  
Min.  
Typ.  
Max.  
Min.  
Max.  
Unit  
FNOM  
tRPWH  
tRPWL  
tU  
VCO Frequency Range  
See PLL Programmable Skew Range and Resolution Table  
REF Pulse Width HIGH(11)  
REF Pulse Width LOW(11)  
Programmable Skew Time Unit  
3
3
—
—
—
—
3
3
—
—
—
—
3
3
—
—
—
—
ns  
ns  
See Control Summary Table  
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)  
tSKEW0 Zero Output Skew (All Outputs)(1,4,5)  
tSKEW1 Output Skew  
—
—
—
0.05  
0.1  
0.2  
0.25  
0.5  
—
—
—
0.1  
0.25  
0.6  
0.25  
0.5  
—
—
—
0.1  
0.3  
0.6  
0.25  
0.75  
1
ns  
ns  
ns  
0.25  
0.7  
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,6)  
tSKEW2 Output Skew  
—
—
—
0.3  
0.25  
0.5  
1.2  
0.5  
0.9  
—
—
—
0.5  
0.5  
0.5  
1.2  
0.7  
1
—
—
—
1
1.5  
1.2  
1.7  
ns  
ns  
ns  
(Rise-Fall, Nominal-Inverted, Divided-Divided)(1,6)  
tSKEW3 Output Skew  
0.7  
1.2  
(Rise-Rise, Fall-Fall, Different Class Outputs)(1,6)  
tSKEW4 Output Skew  
(Rise-Fall, Nominal-Divided, Divided-Inverted)(1,2)  
tDEV  
tPD  
Device-to-Device Skew(1,2,7)  
—
−0.25  
−1.2  
—
—
0
0.75  
0.25  
1.2  
2
—
−0.5  
−1.2  
—
—
0
1.25  
0.5  
1.2  
2.5  
3
—
−0.7  
−1.2  
—
—
0
1.65  
0.7  
1.2  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ps  
REF Input to FB Propagation Delay(1,9)  
Output Duty Cycle Variation from 50%(1)  
Output HIGH Time Deviation from 50%(1,10)  
Output LOW Time Deviation from 50%(1,11)  
Output Rise Time(1)  
Output Fall Time(1)  
PLL Lock Time(1,8)  
Cycle-to-Cycle Output Jitter(1)  
tODCV  
tPWH  
tPWL  
tORISE  
tOFALL  
tLOCK  
tJR  
0
0
0
—
—
1
—
—
1
—
—
1.5  
1.5  
—
—
—
—
1.5  
1.2  
1.2  
0.5  
25  
—
—
3.5  
2.5  
2.5  
0.5  
25  
0.15  
0.15  
—
0.15  
0.15  
—
1.5  
1.5  
0.5  
25  
0.15  
0.15  
—
1
1
—
—
—
—
—
—
RMS  
—
—
—
Peak-to-Peak  
—
200  
—
200  
—
200  
NOTES:  
1. All timing and jitter tolerances apply for FNOM > 25MHz.  
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load.  
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
4. tSKEW0 is the skew between outputs when they are selected for 0tU.  
5. For IDT5V991A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max.  
6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).  
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.  
10. Measured at 2V.  
11. Measured at 0.8V.  
5
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
AC TEST LOADS AND WAVEFORMS  
VCC  
150  
Output  
150  
20pF  
Test Load  
tOFALL  
tORISE  
2.0V  
0.8V  
tPWH  
tPWL  
LVTTL Output Waveform  
1ns  
1ns  
3.0V  
2.0V  
Vth = 1.5V  
0.8V  
0V  
LVTTL Input Test Waveform  
6
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
AC TIMING DIAGRAM  
tRPWL  
tREF  
tRPWH  
REF  
tPD  
tODCV  
tODCV  
FB  
Q
tJR  
tSKEWPR  
tSKEW0, 1  
tSKEWPR  
tSKEW0, 1  
OTHER Q  
tSKEW2  
tSKEW2  
INVERTED Q  
REF DIVIDED BY 2  
REF DIVIDED BY 4  
tSKEW3, 4  
tSKEW3, 4  
tSKEW3, 4  
tSKEW2, 4  
tSKEW1, 3, 4  
NOTES:  
VCCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge  
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.  
Skew:  
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with  
75Ω to VCC/2.  
tSKEWPR:  
tSKEW0:  
tDEV:  
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.  
The skew between outputs when they are selected for 0tU  
.
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.  
tODCV:  
tPWH is measured at 2V.  
tPWL is measured at 0.8V.  
tORISE and tOFALL are measured between 0.8V and 2V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from  
the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
7
IDT5V991A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK  
ORDERING INFORMATION  
X
IDT  
XXXXX  
XX  
X
Shipping Packaging  
Device Type Package Process  
Blank  
8
Tray or Tube  
Tape & Reel  
Blank  
I
0ºC to +70ºC (Commercial)  
-40ºC to +85ºC (Industrial)  
JG  
PLCC - Green  
3.3V Programmable Skew PLL Clock Driver  
TurboClock  
5V991A-2  
5V991A-5  
5V991A-7  
REVISION HISTORY  
November 7, 2013  
Page 8, added Tape & Reel ordering information  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
clockhelp@idt.com  
www.idt.com  
8
厂商 型号 描述 页数 下载

IDT

 		5V925BQGI 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQGI8 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQI 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925BQI8 可编程LVCMOS / LVTTL时钟发生器[ Programmable LVCMOS/LVTTL Clock Generator ] 18 页

IDT

 		5V925QGI [ Clock Generator, PDSO16 ] 7 页

IDT

 		5V925QGI8 [ Clock Generator, PDSO16 ] 7 页

IDT

 		5V926APGGI [ TSSOP-16, Tube ] 6 页

IDT

 		5V926APGGI8 [ TSSOP-16, Reel ] 6 页

IDT

 		5V926APGI [ Clock Generator, 160MHz, PDSO16, TSSOP-16 ] 6 页

IDT

 		5V927PGGI8 [ TSSOP-16, Reel ] 6 页

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