请登录

免费注册
全部商品
电子元器件
方案中心
工业品
PDF资料
购物车 0
上传BOM

产品分类

找货询价

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

QQ咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

会员中心
购物车
技术支持

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

售后咨询

一对一服务 找料无忧

专属客服

服务时间

周一 - 周六 9:00-18:00

IXA531S10

型号：

IXA531S10

品牌：

IXYS[ IXYS CORPORATION ]

页数：

11 页

PDF大小：

266 K

下载PDF手册
IXA531  
Preliminary Data Sheet  
500mA 3-Phase Bridge Driver  
Features  
General Description  
• Fully operational to +650V  
• Tolerant of negative transient voltages  
• dV/dt immune (50V/ns)  
TheIXA531isamonolithic, 3-phase, MOSFET/IGBT  
gate driver consisting of three independent, high and low  
side output channels. In addition to the six inputs,  
which are CMOS/TTL Compatible, for the three  
corresponding high side and three low side outputs,  
there are dedicated lines for FAULT, ENABLE and  
RESET. Overload/Short Circuit protection is  
implemented by sensing a voltage across a shunt or low  
value resistor which carries load current. Upon  
Overload/Short Circuit detection, all outputs are  
disabled. Likewise ENABLE (EN) pin, when LOW under  
abnormal operating conditions, affords soft shut down of  
outputs. FAULT(FLT) signal‘s status indicates that shut  
down has occurred either due to Overload/Short Circuit  
in driven MOSFET/IGBT or Under Voltage on VCL.  
ClearingofFAULT(FLT)signalandrestorationof  
normal operation ensue automatically after a  
• Latch-up protected over entire operating range  
• Fault-current shutdown for all drive outputs  
• User selectable delay or latching function for  
clearing of the FAULT signal, independent  
user controlled clearing of the FAULT signal  
is also available  
• UVLO protection for all drive outputs  
• Enable signal capable of disabling all driver outputs  
• 3 half-bridge driver pairs (independent)  
• 3.3V logic compatible  
• Cross-conduction prevention logic,  
220 ns - 360ns Phase leg deadtime  
• Peak output current: 600mA Pull-up/Source,  
600mA Pull-down/Sink  
programmed delay using an RC Network wired at RST  
(RESET)pin. Matchedpropagationdelaysensure  
properoperationevenatveryhighswitching  
frequencies. Absence of cross conduction in output  
stages removes possibility of shoot through in driven  
powerMOSFETsorIGBTs.  
• Wide operating supply voltage range: 8.0V to 35V  
• Capacitive load drive capability: 1250pF in < 100ns  
• Matched, low propagation delay times  
• Low supply current  
• Monolithic construction  
___  
• Fault monitoring is accompanied by a FLT  
signal indication, with programmable reset or user  
selectable latched protection  
• Target package power dissipation capability is 2.0W.  
• Full level of function available from -55°C to + 125°C  
Applications  
• DrivingMOSFETsandIGBTsinhalf-bridgecircuits  
• High voltage, high side and low side drivers  
• MotorControls  
• Available in 48-Lead 7mm x 7mm MLP Quad  
package and 44-Lead PLCC package  
• Switch Mode Power Supplies (SMPS)  
• DCtoDCConverters  
• Class D Switching Amplifiers  
Ordering Information  
Part  
Package  
IXA531S10  
IXA531L4  
48L - SSLGA  
44L - PLCC  
Warning: The IXA531 is ESD sensitive.  
DS99187A(12/05)  
Copyright © IXYS CORPORATION 2005  
First Release  
1
IXA531  
Fig. 1. Single Phase Application  
up to + 650 V  
VCL  
HIN1  
LIN1  
FLT  
VCL  
HIN1  
LIN1  
VCH1  
HGO1  
HS1  
To  
FLT  
EN  
EN  
Load  
IXA531  
RST  
UVSEL  
LGO1  
ITRP  
LS  
LGO3  
DG  
HS3  
LIN3  
LGO2  
LIN2  
HG02  
HG03  
HIN2  
HS2  
VCH3  
VCH2  
HIN3  
Pin Description And Configuration  
SYMBOL  
FUNCTION DESCRIPTION  
_______  
HIN1,2,3  
_______  
LIN1,2,3  
HS Input  
High side Input signal, TTL or CMOS compatible; HGO1,2,3 out of phase  
LS Input  
Enable  
Low side Input signal, TTL or CMOS compatible; LGO1,2,3 out of phase  
Chip enable. When driven high, both outputs go low.  
EN  
DG  
Ground  
LogicReferenceGround  
VCH1,2,3  
HGO1,2,3  
HS1,2,3  
Supply Voltage High Side Power Supply  
Output  
Return  
Highsidedriveroutput  
Highsidevoltagereturn  
V
CL  
Supply Voltage Low side and Logic fixed power supply. This power supply provides power for  
all outputs. Voltage range is from 8.0 to 35V.  
LGO1,2,3  
LS  
Output  
Lowsidedriveroutput  
Low side return Lowsidedriverreturn  
___  
FLT  
Fault  
Trip  
IndicatesLow-SideundervoltageorOverCurrentTrip  
ITRP  
RST  
Input for over current shutdown  
Delay after trip  
Externally connected RC network decide FAULT CLEAR delay.  
2
IXA531  
3
IXA531  
Absolute Maximum Ratings  
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage  
parameters are absolute voltages referenced to LS. The thermal resistance and power dissipation ratings are  
measured under board mounted and still air conditions  
Symbol Definition  
High side floating supply voltage , (V  
Min.  
-200  
Max.  
650  
Units  
V
CH  
)
V
V
V
V
V
V
CH1,2,3  
V
V
V
V
V
High side floating supply offset voltage , (V  
High side floating output voltage , (V  
)
V
V
V
CH1,2,3 - 35  
CH1,2,3 + 0.3  
HS  
HS1,2,3  
)
V
HS1,2,3– 0.3  
8.0  
CH1,2,3 + 0.3  
35  
HGO  
CL  
HGO1,2,3  
Low side and logic fixed supply voltage  
Logic Supply offset voltage  
V
- 0.7  
V
0.7  
DG  
LS  
LS +  
Lowsideoutputvoltage  
_______ _______  
- 0.3  
V + 0.3  
LGO  
CL  
Lower of  
(V + 35) or  
V
Input voltage HIN1,2,3, LIN1,2,3, ITRP, RST , EN  
V
DG  
– 0.3  
V
IN  
DG  
(V  
CL + 0.3)  
V
FAULToutputvoltage  
V
– 0.3  
V
V
V/ns  
W
FLT  
DG  
CL + 0.3  
50  
lewrate  
dV/dt  
Allowableoffsetvoltageslewrate  
P
D
Package power dissipation@ T ≤ +25OC  
2.0  
63  
A
Rth  
Thermal resistance, junction to ambient  
Junctiontemperature  
K/W  
OC  
OC  
JA  
T
J
125  
150  
300  
T
S
Storagetemperature  
-55  
T
L
Leadtemperature(soldering, 10seconds)  
OC  
Recommended Operating Conditions  
For proper operation the device should be used within the recommended conditions.All voltage parameters are absolute  
values referenced to LS. The V offset rating is tested with all supplies baised at 15V differential.  
HS  
Symbol  
Definition  
Min.  
Max.  
Units  
V
V
V
V
V
V
High side floating supply voltage  
High side floating supply offset voltage  
Highsidefloatingoutputvoltage  
Lowsideoutputvoltage  
V
V
V
V
V
V
V
V
CH1,2,3  
HS1,2,3 + 12  
-200  
HS1,2,3 + 35  
650  
HS1,2,3  
HGO1,2,3  
LGO1,2,3  
CL  
V
V
CH1,2,3  
HS1,2,3  
0
V
CL  
35  
+ 0.3  
Low side and logic fixed supply voltage  
LogicSupplyoffsetvoltage  
FAULToutputvoltage  
12  
V
- 0.3  
V
DG  
LS  
LS  
V
FLT  
V
V
CL  
V
V
DG  
DG  
V
RST  
RSTinputvoltage  
V
V
CL  
V
V
ITRP  
ITRPinputvoltage  
V
DG  
V
CL  
_______ _______  
V
OC  
V
Logic input voltage HIN1,2,3, LIN1,2,3, EN  
V
or V  
-40  
V
IN  
DG  
LS  
CL  
T
A
Ambient temperature  
125  
4
IXA531  
Static Electrical Characteristics  
VBIAS (VCL, VCH1,2,3) = 15V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to DG and are  
applicable to all six channels . The VO and IO parameters are referenced to LS and V and are applicable to the  
HS1,2,3  
respectiveoutputleads:H  
andLGO1,2,3.  
GO1,2,3  
Symbol  
Definition  
Min. Typ. Max. Units Test Conditions  
V
INL  
Logic“0”inputvoltageHIN1,2,3;LIN1,2,3  
0.8  
V
V
Logic“1”inputvoltageHIN1,2,3;LIN1,2,3  
ENpositvegoingthreshold  
ENnegativegoingthreshold  
ITRPpositvegoingthreshold  
ITRP input hysteresis  
3.0  
0.8  
V
V
V
INH  
V
V
V
V
V
V
V
V
3.0  
EN,TH+  
EN,TH-  
0.37 0.46 0.55 V  
ITRP,TH+  
ITRP, HYS  
RST,TH+  
RST,HYS  
OH1,2,3  
.07  
V
V
V
V
V
RSTpositivegoingthreshold  
RST input hysteresis  
8
3
High level output voltage, V  
Low level output voltage, V  
V
or V  
V
0.9 1.4  
0.4 0.6  
I =20mA  
0
CH - HGO  
CL- LGO  
V
I =20mA  
0
OL1,2,3  
HGO or LGO  
VCLUV+  
VCLsupplyunder-voltagepositivegoingthreshold  
10.6 11.1 11.6 V  
V
V
V
V
V
V
V
V
V
V
supplyunder-voltagepositivegoingthreshold  
supplyunder-voltagenegaitivegoingthreshold  
supplyunder-voltagenegaitivegoingthreshold  
supplyunder-voltagelockouthysteresis  
supplyunder-voltagelockouthysteresis  
V
V
CHUV+  
CH  
CL  
CH  
CL  
CH  
10.6 11.1 11.6  
10.4 10.9 11.4  
CLUV-  
10.4 10.9 11.4 V  
CHUV-  
CLUVH  
CHUVH  
0.2  
0.2  
V
V
I
Offset supply leakage current  
50  
μA  
V
V
LK  
CH1,2,3=  
HS1,2,3=600 V  
I
Quiescent V  
Quiescent V  
supply current  
supply current  
70  
120 μA  
V
V
=0V or 5V  
=0V or 5V  
IN  
IN  
QVCH  
CH  
CL  
I
1.6 2.3 mA  
4.9  
QVCL  
V
Inputclampvoltage(HIN,LIN,ITRP,EN)  
Logic “1“ Input bias current for LIN1,2,3  
Logic “0“ Input bias current for LIN1,2,3  
Logic “1“ Input bias current for HIN1,2,3  
Logic “0“ Input bias current for HIN1,2,3  
“high” ITRP input bias current  
V
I
=100μA  
IN  
IN  
I
I
200 300 μA  
100 220 μA  
200 300 μA  
100 220 μA  
V
V
V
V
V
V
V
V
V
LIN+or IN+  
LIN = 5V  
I
I
LIN-or IN-  
LIN = 0V  
I
I
HIN+or IN+  
HIN = 5V  
I
I
HIN-or IN-  
HIN = 0V  
I
30  
0
100 μA  
μA  
100 μA  
ITRP+  
ITRP = 5V  
ITRP = 0V  
EN = 5V  
I
“low” ITRP input bias current  
1
ITRP-  
I
“high” ENABLE input bias current  
“low” ENABLE input bias current  
RST input bias current  
30  
0
EN+  
I
1
1
μA  
μA  
EN-  
EN = 0V  
I
0
RST  
RST = 0Vor 15V  
I
Output high short circuit pulsed current  
Output low short circuit pulsed current  
RST low on resistance  
600  
600  
50  
50  
mA V =0V,PW <10 μs  
0
GO+  
I
mA V =15V,PW<10μs  
GO-  
0
R
100  
100  
Ω
Ω
ON,RST  
ON,FLT  
R
FLT low on resistance  
5
IXA531  
Dynamic Electrical Characteristics  
VCL =VCH = VBIAS = 15V,VHS1,2,3 = VDG = V , T = 25°C and C = 1000pF unless otherwise specified.  
A
LS  
L
Symbol  
Definition  
Min.  
Typ.  
Max. Units Test Conds.  
ton  
toff  
Turn-on propagation delay  
Turn-off propagation delay  
Turn-on rise time  
300  
250  
425  
400  
125  
50  
550  
550  
190  
75  
nS  
nS  
nS  
nS  
nS  
VIN=0V & 5V  
VIN=0V & 5V  
----  
t
r
tf  
Turn-on fall time  
----  
tEN  
ENABLE low to output shutdown  
propagation delay  
300  
450  
600  
VIN , VEN = 0 V  
or 5 V  
tITRP  
tbl  
ITRP to output shutdown propagation delay  
500  
100  
750  
150  
1000  
nS  
nS  
VITRP=5V  
VIN=0V or 5V  
VITRP = 5V  
ITRP blanking time  
V
IN = 0V or 5V  
VITRP = 5V  
tFLT  
ITRP to FAULT propagation delay  
400  
600  
800  
2
nS  
tFILIN  
Input filter time (HIN, LIN, EN)  
100  
1.3  
200  
nS  
VIN = 0V & 5V  
VIN = 0V or 5V  
VITRP=0V  
tFLCLR  
FAULT clear time RST=2meg, C=1nF  
1.65  
mS  
DT  
Dead time  
220  
290  
40  
360  
75  
nS  
nS  
VIN = 0V & 5V  
MT  
Matching delay ON and OFF  
Matching delay, max (ton , toff) - min (ton , toff)  
(ton,toff are applicable to all 3 channels)  
External Dead  
MDT  
Time  
25  
40  
70  
75  
nS  
nS  
>400nsec  
PM  
Output pulse width matching, PWMIN-PWMOUT  
VCL  
VCH  
ITRP  
ENABLE  
FAULT  
LGO1,2,3  
HGO1,2,3  
<UVCL  
15V  
X
<UVCH  
15V  
X
X
0(note 1)  
high imp  
high imp  
0 (note 2)  
high imp  
0
0
0V  
0V  
15V  
15V  
15V  
0V  
LIN1,2,3  
0
15V  
LIN1,2,3  
HIN1,2,3  
15V  
15V  
>V  
0
0
0
0
ITRP  
0V  
15V  
15V  
Notes: A Cross Conduction logic prevents LGO1,2,3 and HGO1,2,3 for each channel from turning on  
simultaneously.  
1. UVCL is not latched, when VCL>UVCL, FAULT returns to high impedance.  
2. When ITRP < VITRP,FAULT returns to high-impedance after RST pin becomes greater then 8V  
(@VCL= 15V).  
6
IXA531  
HIN1,2,3  
HIN1,2,3  
LIN1,2,3  
EN  
ITRP  
FLT  
RST  
HO1,2,3  
LO1,2,3  
Fig. 3. Timing Diagram  
EN  
50%  
t
EN  
90%  
LO1,2,3  
HO1,2,3  
Fig. 4. ENABLE Timing Waveforms  
LIN1,2,3  
HIN1,2,3  
50%  
50%  
PWMIN  
LIN1,2,3  
HIN1,2,3  
50%  
on  
50%  
t
t
off  
t
r
t
f
PWMOUT  
90%  
90%  
HO1,2,3  
LO1,2,3  
10%  
10%  
Fig. 5. Switching Time Definitions  
7
IXA531  
LIN1,2,3  
HIN1,2,3  
50%  
50%  
LIN1,2,3  
HIN1,2,3  
50%  
50%  
LO1,2,3  
HO1,2,3  
DT  
DT  
Fig. 6. Deadtime Waveforms  
RST  
VRST,th+  
50%  
50%  
50%  
ITRP  
FLT  
50%  
50%  
tFLT  
t FLCLR  
OUTPUT  
90%  
ITRP  
t
Fig. 7. ITRP / RST Waveforms  
t FILIN  
t FILIN  
on  
on  
off  
off  
on  
off  
HIN / LIN  
HO / LO  
high  
low  
Fig. 8. ENABLE Timing Waveforms  
8
IXA531  
VCL  
VCL  
VCH  
VCL  
VCL  
VCH1  
HGO1  
HS1  
750K  
Low to  
High  
Out  
600mA  
Gate  
Driver  
5V LOGIC  
hin1  
en1  
HIN1  
LIN1  
h01  
iO1  
In  
CMOS  
to VCL  
Rst  
In  
Isolation  
Level Shift , &  
Anti-Cross  
UVCC  
Detect  
750K  
Conduction  
Logic  
HS  
lin1  
Isolated High Side  
VCL  
VCL  
VCH  
VCL  
VCH2  
HGO2  
HS2  
750K  
750K  
Low to  
High  
Out  
600mA  
Gate  
Driver  
5V LOGIC  
hin2  
en2  
HIN2  
LIN2  
h02  
iO2  
In  
CMOS  
to VCL  
Rst  
In  
VCL  
Isolation  
Level Shift , &  
UVCC  
Detect  
Anti-Cross  
Conduction  
Logic  
HS  
lin2  
Isolated High Side  
VCL  
VCL  
VCH  
VCL  
750K  
VCH3  
HGO3  
HS3  
Low to  
High  
Out  
600mA  
Gate  
Driver  
5V LOGIC  
hin3  
en3  
HIN3  
LIN3  
h03  
iO3  
In  
CMOS  
to VCL  
Rst  
In  
VCL  
Isolation  
Level Shift , &  
UVCC  
Detect  
Anti-Cross  
Conduction  
Logic  
750K  
HS  
lin3  
Isolated High Side  
VCL  
OUT  
VCL  
VCL  
Low to High  
Delay  
600mA  
Gate  
Driver  
UVCL  
Detect  
In  
Out  
LGO1  
EN  
Equalizer  
50K  
VCL  
+
ITRP  
Set  
S
R
-
50K  
Dominant  
Latch  
Low to High  
Delay  
600mA  
Gate  
Driver  
Out  
In  
LGO2  
QB  
+
Equalizer  
0.5 V  
-
VCL  
RST  
Low to High  
Delay  
600mA  
Gate  
Driver  
Out  
N
In  
LGO3  
LS  
Equalizer  
FLT  
DG  
N
1
Fig. (9) IXA531 Block Diagram  
9
IXA531  
Fig. 10. Pin Diagram for the IXA531S10 48-Lead MLP Quad Package  
0.276±0.002 [7.00±0.05]  
0.039±0.002 [1.00±0.05]  
0.015±0.001 [0.38±0.03]  
0.009±0.001 [0.23±0.03]  
0.030±0.001 [0.75±0.03]  
0.020 [0.50]  
Fig. 11. Pin Diagram for the IXA531L4 44-Lead PLCC package  
4
6
5
3
43  
42 41 
LS  
7
8
37  
36  
35  
31  
LIN1  
LIN2  
LIN3  
NC  
9
VCH2  
HGO2  
HS2  
IXA531L4  
10  
11  
12  
13  
14  
15  
16  
17  
FLT  
NC  
ITRP  
NC  
VCH3  
HGO3  
HS3  
EN  
30  
29  
RST  
18 19 20 21 22 23 24 25
10  
IXA531  
Fig. 12. 44-Lead PLCC Outline Diagram  
IXYS Corporation  
IXYS Semiconductor GmbH  
3540 Bassett St; Santa Clara, CA 95054  
Tel: 408-982-0700; Fax: 408-496-0670  
e-mail: sales@ixys.net  
Edisonstrasse15 ; D-68623; Lampertheim  
Tel: +49-6206-503-0; Fax: +49-6206-503627  
e-mail: marcom@ixys.de  
www.ixys.com  
11  
厂商 型号 描述 页数 下载

IXYS

 		IXA12IF1200HB 由于易于并联的导通电压的正温度系数[ Easy paralleling due to the positive temperature coefficient of the on-state voltage ] 6 页

IXYS

 		IXA12IF1200PB 由于易于并联的导通电压的正温度系数[ Easy paralleling due to the positive temperature coefficient of the on-state voltage ] 6 页

IXYS

 		IXA12IF1200TC 由于易于并联的导通电压的正温度系数[ Easy paralleling due to the positive temperature coefficient of the on-state voltage ] 6 页

ILSI

 		IXA16-BADF18-12.999999MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

ILSI

 		IXA16-BAFF32-20.999999MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

ILSI

 		IXA16-BBDF32-20.999999MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

ILSI

 		IXA16-BBDF8-30.000MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

ILSI

 		IXA16-BBFF18-12.999999MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

ILSI

 		IXA16-BBFF32-20.999999MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

ILSI

 		IXA16-BBFF32-21.000MHZ [ Parallel - Fundamental Quartz Crystal, ] 2 页

购物指南

支付方式

配送服务

售后服务

发票须知

优惠券使用规则

特色服务

PCBA制造

国产品牌推荐

国产料号替代

质量保证

技术资料

行业资讯

关于我们

关于壹壹捌

联系我们

联系我们

服务热线：400-618-9990

企业邮箱：sales@ic118.com

服务时间：周一至周六 8:30-17:30

壹壹捌官方微信号

PDF索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

IC型号索引：

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

U

V

W

X

Y

Z

0

1

2

3

4

5

6

7

8

9

Copyright 2024 gkzhan.com Al Rights Reserved 京ICP备06008810号-21 京

深圳网络警察报警平台
公共信息安全网络监察
经营性网站备案信息
不良信息举报中心
工商网监电子标识
全国公安机关备案
0.207946s