WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
ICC SPECIFICATION
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
665
534
403
Units
t
680
640
640
mA
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as ICC4W
800
760
720
mA
ICC2P** Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
64
64
64
mA
mA
mA
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputsare
STABLE; Data bus inputs are FLOATING
280
320
240
280
240
280
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
240
96
280
96
240
96
mA
mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
440
1120
1160
400
960
400
880
880
mA
mA
mA
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRASmax(ICC), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
=
1000
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1200
64
1120
64
1120
64
mA
mA
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs Normal
vre FLOATING; Data bus inputs are FLOATING
ICC6**
ICC7*
Operating bank interleave read current;
All bank interleaVINg reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
1760
1760
1760
mA
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
October 2006
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
