IDT5V993A
COMMERCIAL AND INDUSTRIAL TEMPERATURE
RANGES
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
INPUT TIMING REQUIREMENTS
Symbol
tR, tF
tPWC
DH
Description (1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
—
Max.
10
Unit
ns/V
ns
3
—
10
90
%
REF
Reference Clock Input
3.75
85
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT5V993A-2
IDT5V993A-5
IDT5V993A-7
Typ.
Symbol Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
FNOM
tRPWH
tRPWL
tU
VCO Frequency Range
See PLL Programmable Skew Range and Resolution Table
REF Pulse Width HIGH(11)
REF Pulse Width LOW(11)
Programmable Skew Time Unit
3
3
—
—
—
—
3
3
—
—
—
—
3
3
—
—
—
ns
ns
—
See Control Summary Table
tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(1,2,3)
tSKEW0 Zero Output Skew (All Outputs)(1,4)
tSKEW1 Output Skew
—
—
—
0.05
0.1
0.2
0.25
0.5
—
—
—
0.1
0.25
0.6
0.25
0.5
—
—
—
0.1
0.3
0.6
0.25
0.75
1
ns
ns
ns
0.25
0.7
(Rise-Rise, Fall-Fall, Same Class Outputs)(1,6)
tSKEW2 Output Skew
—
—
—
0.3
0.25
0.5
1.2
0.5
0.9
—
—
—
0.5
0.5
0.5
1.2
0.7
1
—
—
—
1
1.5
1.2
1.7
ns
ns
ns
(Rise-Fall, Divided-Divided)(1,6)
tSKEW3 Output Skew
0.7
1.2
(Rise-Rise, Fall-Fall, Different Class Outputs)(1,6)
tSKEW4 Output Skew
(Rise-Fall, Nominal-Divided)(1,2)
tDEV
tPD
Device-to-Device Skew(1,2,7)
—
−0.25
−1.2
—
—
0
0.75
0.25
1.2
2
—
−0.5
−1.2
—
—
0
1.25
0.5
1.2
2.5
3
—
−0.7
−1.2
—
—
0
1.65
0.7
1.2
3
ns
ns
ns
ns
ns
ns
ns
ms
ps
REF Input to FB Propagation Delay(1,9)
Output Duty Cycle Variation from 50%(1)
Output HIGH Time Deviation from 50%(1,10)
Output LOW Time Deviation from 50%(1,11)
Output Rise Time(1)
Output Fall Time(1)
PLL Lock Time(1,8)
Cycle-to-Cycle Output Jitter(1)
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
0
0
0
—
—
1
—
—
1
—
—
1.5
1.5
—
—
—
—
1.5
1.2
1.2
0.5
25
—
—
3.5
2.5
2.5
0.5
25
0.15
0.15
—
0.15
0.15
—
1.8
1.8
0.5
25
0.15
0.15
—
1
1
—
—
—
—
—
—
RMS
—
—
—
Peak-to-Peak
—
200
—
200
—
200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. For IDT5V993A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.
6. There are 2 classes of outputs: Nominal (multiple of tU delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).
7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
10. Measured at 2V.
11. Measured at 0.8V.
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