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5V9910A-7SOG

型号：

5V9910A-7SOG

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

6 页

PDF大小：

91 K

下载PDF手册
IDT5VR9A9N1G0EAS  
3.3V LOW SKEW  
PLL CLOCK DRIVER  
TURBOCLOCK™ JR.  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015  
FEATURES:  
DESCRIPTION:  
• Eight zero delay outputs  
• <250ps of output to output skew  
The IDT5V9910A is a high fanout phase locked-loop clock driver  
intended for high performance computing and data-communications  
• Selectable positive or negative edge synchronization  
• Synchronous output enable  
• Output frequency: 15MHz to 85MHz  
• 3 skew grades:  
IDT5V9910A-2: tSKEW0<250ps  
IDT5V9910A-5: tSKEW0<500ps  
IDT5V9910A-7: tSKEW0<750ps  
• 3-level inputs for PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <200ps peak-to-peak  
• Available in SOIC package  
• Not Recommended for New Design  
• Functional replacement part: 8T49N008-dddNLGI  
applications. It has eight zero delay LVTTL outputs.  
When the GND/sOE pin is held low, all the outputs are synchronously  
enabled. However, if GND/sOE is held high, all the outputs except Q2  
and Q3 are synchronously disabled.  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronized with the positive edge of the REF clock input. When VCCQ/  
PE is held low, all the outputs are synchronized with the negative edge  
of REF.  
The FB signal is compared with the input REF signal at the phase  
detector in order to drive the VCO. Phase differences cause the VCO of  
the PLL to adjust upwards or downwards accordingly.  
An internal loop filter moderates the response of the VCO to the phase  
detector. The loop filter transfer function has been chosen to provide  
minimal jitter (or frequency variation) while still providing accurate  
responses to input frequency changes.  
FUNCTIONAL BLOCK DIAGRAM  
VCCQ/PE  
GND/sOE  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
FB  
PLL  
REF  
FS  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MARCH 21, 2014  
1
c
2014 Integrated Device Technology, Inc.  
DSC 5847/3  
IDT5V9910A  
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Description  
Supply Voltage to Ground  
DC Input Voltage  
Max  
–0.5 to +7  
–0.5 to VCC+0.5  
–0.5 to +5.5  
530  
Unit  
V
VI  
V
1
GND  
TEST  
NC  
REF  
VCCQ  
FS  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
REF Input Voltage  
V
2
Maximum Power Dissipation (TA = 85°C)  
Storage Temperature  
mW  
°C  
3
TSTG  
–65 to +150  
NC  
4
GND/sOE  
VCCN  
Q7  
NOTE:  
5
VCCQ/PE  
VCCN  
Q0  
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause per-  
manent damage to the device. These are stress ratings only, and functional operation of  
the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute-maximum-rated condi-  
tions for extended periods may affect device reliability.  
6
7
Q6  
Q1  
8
GND  
Q5  
GND  
Q2  
9
10  
11  
12  
Q4  
Q3  
VCCN  
FB  
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)  
VCCN  
Parameter Description  
Typ.  
Max.  
Unit  
CIN  
Input Capacitance  
5
7
pF  
NOTE:  
SOIC  
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not produc-  
tion tested.  
TOP VIEW  
PIN DESCRIPTION  
Pin Name  
REF  
Type  
IN  
Description  
Reference Clock Input  
Feedback Input  
FB  
IN  
TEST (1)  
GND/ sOE(1)  
IN  
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.  
IN  
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as  
the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.  
VCCQ/PE  
FS(2)  
IN  
IN  
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of  
the reference clock.  
Frequency range select:  
FS = GND: 15 to 35MHz  
FS = MID (or open): 25 to 60MHz  
FS = VCC: 40 to 85MHz  
Q0 - Q7  
VCCN  
VCCQ  
GND  
OUT  
PWR  
PWR  
PWR  
Eight clock output  
Power supply for output buffers  
Power supply for phase locked loop and other internal circuitry  
Ground  
NOTES:  
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.  
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time  
before all data sheet limits are achieved.  
2
IDT5V9910A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.  
RECOMMENDED OPERATING RANGE  
IDT5V9910A-5, -7  
(Industrial)  
IDT5V9910A-2  
(Commercial)  
Symbol  
VCC  
Description  
Min.  
3
Max.  
3.6  
Min.  
Max.  
3.6  
Unit  
V
Power Supply Voltage  
Ambient Operating Temperature  
3
0
TA  
-40  
+85  
+70  
°C  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Conditions  
Guaranteed Logic HIGH (REF, FB Inputs Only)  
Guaranteed Logic LOW (REF, FB Inputs Only)  
3-Level Inputs Only  
Min.  
Max.  
—
Unit  
V
VIH  
Input HIGH Voltage  
2
—
VIL  
Input LOW Voltage  
Input HIGH Voltage(1)  
Input MID Voltage(1)  
Input LOW Voltage(1)  
Input Leakage Current  
(REF, FB Inputs Only)  
0.8  
V
VIHH  
VIMM  
VILL  
IIN  
VCC−0.6  
VCC/2−0.3  
—
—
V
3-Level Inputs Only  
VCC/2+0.3  
0.6  
V
3-Level Inputs Only  
V
VIN = VCC or GND  
—
±5  
μA  
VCC = Max.  
VIN = VCC  
HIGH Level  
MID Level  
LOW Level  
—
—
—
—
—
2.4  
—
±200  
±50  
I3  
3-Level Input DC Current (TEST, FS)  
VIN = VCC/2  
μA  
VIN = GND  
±200  
±100  
±100  
—
IPU  
IPD  
Input Pull-Up Current (VCCQ/PE)  
Input Pull-Down Current (GND/sOE)  
Output HIGH Voltage  
VCC = Max., VIN = GND  
VCC = Max., VIN = VCC  
VCC = Min., IOH = −12mA  
VCC = Min., IOL = 12mA  
μA  
μA  
V
VOH  
VOL  
Output LOW Voltage  
0.55  
V
NOTE:  
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the  
outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
VCC = Max., TEST = MID, REF = LOW,  
GND/sOE = LOW, All outputs unloaded  
VCC = Max., VIN = 3V  
Typ.(2)  
Max.  
Unit  
ICCQ  
Quiescent Power Supply Current  
8
25  
mA  
ΔICC  
ICCD  
ITOT  
Power Supply Current per Input HIGH  
Dynamic Power Supply Current per Output  
Total Power Supply Current  
1
30  
90  
—
—
—
μA  
VCC = Max., CL = 0pF  
55  
34  
42  
76  
μA/MHz  
VCC = 3.3V, FREF = 25MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 33MHz, CL = 160pF(1)  
VCC = 3.3V, FREF = 66MHz, CL = 160pF(1)  
mA  
NOTE:  
1. For eight outputs, each loaded with 20pF.  
3
IDT5V9910A  
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
INPUT TIMING REQUIREMENTS  
Symbol  
tR, tF  
tPWC  
DH  
Description (1)  
Maximum input rise and fall times, 0.8V to 2V  
Input clock pulse, HIGH or LOW  
Input duty cycle  
Min.  
—
Max.  
10  
Unit  
ns/V  
ns  
3
—
10  
15  
90  
%
REF  
Reference clock input  
85  
MHz  
NOTE:  
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE  
IDT5V9910A-2  
IDT5V9910A-5  
IDT5V9910A-7  
Symbol Parameter  
Min.  
15  
Typ.  
—
—
—
—
—
0.1  
—
0
Max.  
35  
Min.  
15  
25  
40  
3
Typ.  
—
Max.  
35  
Min.  
Typ.  
—
—
—
—
—
0.3  
—
0
Max.  
Unit  
FS = LOW  
FS = MED  
FS = HIGH  
15  
25  
35  
60  
FREF  
REF Frequency Range  
25  
60  
—
60  
MHz  
40  
85  
—
85  
40  
85  
tRPWH  
tRPWL  
REF Pulse Width HIGH(8)  
REF Pulse Width LOW(8)  
3
—
—
—
3
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ps  
3
—
3
—
—
3
—
tSKEW0 Zero Output Skew (All Outputs)(1,3,4)  
—
0.25  
0.75  
0.25  
1.2  
1.2  
1.2  
0.5  
25  
—
—
0.25  
—
0.5  
1.25  
0.5  
1.2  
1.5  
1.5  
0.5  
25  
—
0.75  
1.65  
0.7  
1.2  
2.5  
2.5  
0.5  
25  
tDEV  
tPD  
Device-to-Device Skew(1,2,5)  
REF Input to FB Propagation Delay(1,7)  
Output Duty Cycle Variation from 50%(1)  
Output Rise Time(1)  
Output Fall Time(1)  
PLL Lock Time(1,6)  
—
—
−0.25  
−1.2  
0.15  
0.15  
—
−0.5  
−1.2  
0.15  
0.15  
—
0
0
−0.7  
−1.2  
0.15  
0.15  
—
tODCV  
tORISE  
tOFALL  
tLOCK  
tJR  
0
0
1
1
1.5  
1.5  
—
—
—
1
1
—
—
—
—
—
—
Cycle-to-Cycle Output Jitter(1)  
RMS  
—
—
—
Peak-to-Peak  
—
200  
—
200  
—
200  
NOTES:  
1. All timing and jitter tolerances apply for FNOM > 25MHz.  
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.  
3. tSKEW is the skew between all outlets. See AC TEST LOADS.  
4. For IDT5V9910A-2 tSKEW0 is measured with CL = 0pF; for CL = 20pF, tSKEW0 = 0.35ns Max.  
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.  
8. Refer to INPUT TIMING REQUIREMENTS for more detail.  
4
IDT5V9910A  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.  
AC TEST LOADS AND WAVEFORMS  
1ns  
1ns  
VCC  
3.0V  
2.0V  
Vth =1.5V  
0.8V  
150  
0V  
Output  
LVTTL Input Test Waveform  
150  
20pF  
tORISE  
tOFALL  
Test Load  
2.0V  
0.8V  
LVTTL Output Waveform  
AC TIMING DIAGRAM  
tREF  
tRPWH  
tRPWL  
REF  
tPD  
tODCV  
tODCV  
FB  
tJR  
Q
tSKEW  
tSKEW  
OTHER Q  
NOTES:  
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω to VCC/2.  
tSKEW:  
The skew between all outputs.  
tDEV:  
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)  
The deviation of the output from a 50% duty cycle.  
tODCV:  
tORISE and tOFALL are measured between 0.8V and 2V.  
tLOCK:  
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured  
from the application of a new signal or frequency at REF or FB until tPD is within specified limits.  
5
IDT5V9910A  
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE  
RANGES  
ORDERING INFORMATION  
IDT  
XXXXX  
XX  
X
Device Type Package Process  
Blank  
I
0ºC to +70ºC (Commercial)  
-40ºC to +85ºC (Industrial)  
SOG  
SOIC - Green  
5V9910A-2 3.3V Low Skew PLL Clock Driver TurboClock Jr.  
5V9910A-5  
5V9910A-7  
REVISION HISTORY  
3/21/14  
Product Discontinuation Notice - Last Time Buy expires January 27, 2015, PDN# CQ-14-01  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
clockhelp@idt.com  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
6
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