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ICs for Communications

ATM Layer Processor

ALP

PXB 4350 Version 1.1

Product Overview 04.97

T4350-XV11-O1-7600

PXB 4350

Revision History:

Current Version: 04.97

Editorial Update

Previous Version:

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Page

Subjects (major changes since last revision)

(in previous (in current

Version)

Edition 04.97

This edition was realized using the software system FrameMaker .

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1

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failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

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PXB 4350

Page

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.1

1.2

1.3

2

2.1

2.2

2.3

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Core Functions and Interfaces of the ALP . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Functional Description of user data flow in up- and downstream direction . .15

Address Reduction and Header Translation . . . . . . . . . . . . . . . . . . . . . . . . .16

Address Reduction in upstream direction . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Internal Address Reduction Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

External Address Reduction Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Difference between external and internal ARC . . . . . . . . . . . . . . . . . . . . . . .20

LCI Structure given by the internal ARC . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Cell Header Structure generated by the ALP . . . . . . . . . . . . . . . . . . . . . . . . .22

Policing in upstream direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Header Translation in downstream direction . . . . . . . . . . . . . . . . . . . . . . . . .25

Multicast in downstream direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Buffer management in downstream direction . . . . . . . . . . . . . . . . . . . . . . . . .26

OAM Management Unit for up- and downstream direction . . . . . . . . . . . . . .26

Traffic Measurement Unit for up- and downstream direction . . . . . . . . . . . . .26

Microprocessor Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.11.1 Microprocessor Access to the internal and external RAMs . . . . . . . . . . . . . .28

3

Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

External RAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Microprocessor and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Test/Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Clock And Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

ARC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

3.1

3.2

3.3

3.4

3.5

3.6

4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.1

4.2

4.3

4.4

5

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

6

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

6.1

Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

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PXB 4350

Overview

1

Overview

The second generation of the Siemens ATM layer chip set consists of the five chips

• PXB 4310 ATM Switching Matrix ASM

• PXB 4325 ATM Switching Preprocessor ASP

• PXB 4330 ATM Buffer Manager ABM

• PXB 4340 ATM OAM Processor AOP

• PXB 4350 ATM Layer Processor ALP.

These chips form a complete chip set to build an ATM switch. A generic ATM switch con-

sists of a switching fabric and switch ports as shown in figure 1.

Conn.

RAM

Cell

RAM

Conn.

RAM

Pol.

RAM

Conn.

RAM

Conn.

RAM

ARC

UTOPIA

SLIF

ATM

PXB 4330

switching

fabric

ABM

PXB 4350

PXB 4325

PXB 4340

consisting

of

PXB 4310

PHYs

ALP

ASP

AOP

ASM

PXB 4330

chips

ABM

Cell

RAM

Conn.

RAM

Conn.

RAM

Conn.

RAM

Conn.

RAM

Conn. RAM = connection data RAM

Pol. RAM = policing data RAM

ARC = address reduction circuit

Cell RAM = ATM cell storage RAM

switch port

Figure 1

ATM switch basic configuration

In the Siemens ATM layer chip set the switching fabric only does cell routing using the

PXB 4310 ASM, which can be used stand alone or in arrays to scale switching network

throughput from 2.5 Gbit/s up to more than 40 Gbit/s. All other ATM layer functions are

performed on the switch ports: policing, header translation and cell counting by the

PXB 4350 ALP, OAM functions by the PXB 4340 AOP and traffic management by the

PXB 4330 ABM. The PXB 4325 ASP is the access device to the switching fabric and

adds/removes the routing header. It also supports redundant switching fabrics and does

multicast.

Only two interfaces are used for data transfer: the industry standard UTOPIA [1, 2] Level

2 multi-PHY interfaces and the proprietary Switch Link InterFace SLIF. This is a serial,

differential high speed link using LVDS [3] levels.

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PXB 4350

Overview

For low end applications a single board switch with 622 Mbit/s throughput can be built

with only one PXB 4350 ALP and one PXB 4330 ABM. Such a mini-switch is basically

one switch port stand alone, without switching network access via the PXB 4325 ASP. If

the full OAM functionality is not needed the PXB 4340 AOP chip can be omitted as

shown in figure 2. Minimum OAM and multicast functionality is also built into the

PXB 4350 ALP. No external Address Reduction Circuit ARC is required if the built-in ad-

dress reduction is used.

Conn. RAM = connection data R

Pol. RAM = policing data RAM

Cell RAM = ATM cell storage R

Conn.

RAM

Pol.

RAM

UTOPIA

PXB 4350

PHYs

ALP

PXB 4330

ABM

Cell

RAM

Conn.

RAM

Conn.

RAM

Figure 2

Mini switch with 622 Mbit/s throughput

Apart from the two applications of figure 1 and 2, many other combinations of the chip

set are possible in designing ATM switches. Functionality is selectable in many combi-

nations due to the modular function split of the chip set. Address reduction, multicast, po-

licing, redundant switching network and other functions can be implemented by appro-

priate chip combinations. The number of supported connections scales with the size of

the external connection RAMs. The policing data RAM can be omitted if this function is

not required.Thus functionality and size of an ATM switch can be tailored exactly to what

the respective application requires, without carrying the overhead of unnecessary func-

tions.

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04.97

ATM Layer Processor

ALP

PXB 4350

CMOS

Version 1.1

1.1

Features

Performance

• Performance up to STM-4/OC-12 equivalent ATM

layer processing

• Throughput up to 687 Mbit/s bi-directional

• Up to 16384 connections in both directions (VPC/

VCC

BGA-456

• Temperature range from 0°C to +70°C

Header Translation

• Header Verification and discarding of unallocated PN/VPI/VCIs

• Address Reduction in upstream direction (PN/VPI/VCIs -> LCI); two modes

–Built-in, programmable, versatile address reduction

–Optional external address reduction

• Header translation in downstream direction (LCI -> PN/VPI/VCIs)

Policing

• Policing according to ITU-T I.371 and ATM Forum UNI Specification

• UPC/NPC function capability on a per connection basis for up to 16384 connections

• Modification of adjusted UPC/NPC parameters on a per established connection basis

without additional cell losses

• Up to 3 Leaky Buckets (LB) per connection with 2 parallel branches: branch 1 contain-

ing LB1 and optionally LB2; branch 2 containing LB3

• 4 Leaky Bucket configurations selectable per connection

• Flexible Policing of each port specific cell flow (user data, F4 RM, F5 RM, F4 segment

OAM, F5 segment OAM, F4 end-to-end OAM, F5 end-to-end OAM) with SW program-

mable control flags indicating whether the flow is policed in branch 1, branch 2 or is not

policed at all

• CDV tolerance (i.e. size of PCR Leaky Bucket) up to 4s

Type

Ordering Code

Package

PXB 4350

Q67001-H9311

BGA-456

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PXB 4350

• Maximum Burst Size (MBS) given by the size of SCR Leaky Bucket of up to 2¹⁰

s

• 2³²PCR values ranging between 1 cell/s and 1 620 000 cells/s. PCR and SCR can be

adjusted with a granularity of at least 2^-10cells/s

Multicast in downstream direction

• Spatial (different ports) and logical (different VPI/VCI for one port) Multicast

OAM Management for up- and downstream

• OAM Levels and Flows (F4/F5) according to ITU-T/I.610 and Bellcore GR-1248-core

• Extraction and insertion of OAM, RM and 2 programmable cell types for both up- and

downstream direction via a 12 cell extraction and 1 cell insertion buffer to the micro-

processor

• Supported OAM cells are AIS, RDI, Continuity Check and Loopback cells

• Check and Generation of CRC-10 for incoming and outgoing cells

• Extraction and Insertion point can be configured as originating, intermediate or termi-

nating point for F4 and F5 Flow (segment and end-to-end)

• Cell processing options as forwarding, dropping, copying and discarding of cells at the

extraction and insertion point

Traffic Measurement for up- and downstream

• Traffic Measurement (can be dis/enabled) according Bellcore GR-1248

• Traffic Measurement intervals of at least 15 minutes

• At VCC level

–Total Incoming and Outgoing Cells

–Total Incoming and Outgoing Cells with CLP=0

–Total Discarded Cells due to UPC/NPC with CLP=1 and CLP=0

–Total Tagged Cells due to UPC/NPC

• At VPC level

–VPC specific Total Incoming and Outgoing Cells

–VPC specific Total Incoming and Outgoing Cells with CLP=0

• At Port level

–Total Discarded Cells due to unallocated PN/VPI/VCI

–Total Incoming Cells with non-zero GFC field

–Total Incoming and Outgoing Cells

–Total Incoming and Outgoing OAM/RM Cells enabled per connection

UTOPIA Interface

• Multiport UTOPIA [1, 2] Level 2 interface in up- and downstream direction according

to ATM forum, UTOPIA level 2 specification

• PHY side is Master, ATM side is Master/Slave configurable for both TX and RX direc-

tion

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PXB 4350

• UTOPIA frequency up to 51.84 MHz

• Statistical Demultiplexing with 64 cell shared buffer for up to 24 queues with flexible

queue size at UTOPIA downstream transmit interface

• Support of up to 24 PHYs with one queue respectively

• In addition to the Utopia-PN a second PN in UDF1 is supported for enhanced PHY ad-

dressing

External SSRAM

• Policing Data SSRAM; can be omitted if policing is not needed.

• Connection Data upstream SSRAM; can be omitted if traffic statistic and OAM is not

needed.

• Connection Data downstream SSRAM; mandatory for header translation and multi-

cast

• All SSRAMs scale with the number of connections; usable SSRAM Types:

– e.g. Toshiba TC55V135FF-8 1MSSRAM(32k*32) or TC55V2326FF-133 2M(64k*32)

similar devices are available from Hitachi and NEC.

Microcomputer Interface

• Intel 386 EX microprocessor interface

• Support of DMA for fast data transfer between external RAM and microprocessor

Boundary Scan

• Boundary scan support according to JTAG

Internal Loops

• Internal hardwired loop: upstream to downstream and downstream to upstream

Technology

• BGA-456 package

• expected power dissipation 2.5 W

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04.97

PXB 4350

1.2

Logic Symbol

Figure 3 ALP Logic Symbol

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04.97

PXB 4350

1.3

Pin Definitions and Functions

Pin No.

Symbol

Input (I)

Function

Output (O)

General (3 pins)

RESET

I

Chip reset

SYSCLK

Core operating clock

UTOPIA clock at PHY side

UTPHY-

CLK

UTATM-

CLK

I

UTOPIA clock at ATM side

UTOPIA Receive Interface, upstream

RXDATU

(15:0)

I

Receive data from PHY side

Address to PHY side

RXADRU

(3:0)

O

RXPRTYU

I

Odd parity of RXDATU(15:0) from PHY side

Enable signal to PHY side

RXENBU

(3:0)

O

RXCLAVU

(3:0)

I

Cell available signal from PHY side

Start of cell signal from PHY side

RXSOCU

Utopia Transmit Interface, downstream

TXDATD

(15:0)

O

Transmit data to PHY side

Address to PHY side

TXA-

DRD(3:0)

TXPRTYD

O

Odd parity to PHY side

TXENBD

(3:0)

Enable signal to PHY side

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PXB 4350

Pin Definitions and Functions

Pin No.

Symbol

Input (I)

Function

Output (O)

TXCLAVD

(3:0)

I

Cell available signal from PHY side

Start of cell signal to PHY side

TXSOCD

O

UTOPIA Receive Interface, downstream

RXDATD

(15:0)

I

Receive data from ATM side

Address from ATM side

RXA-

I/O

DRD(3:0)

RXPRTYD

I

Odd parity of RXDATD(15:0) from ATM side

Enable signals from ATM side

RXENBD

(3:0)

I/O

RXCLAVD I/O

(3:0)

Cell available signal to ATM side

Start of cell signal from ATM side

RXSOCD

I

Utopia Transmit Interface, upstream

TXDATU

(15:0)

O

Transmit data to ATM side

Address from ATM side

TXA-

I/O

DRU(3:0)

TXPRTY

O

Odd parity of TXDATU(15:0) to ATM side

Enable signal from ATM side

TXENBU

(3:0)

I/O

TXCLAVU I/O

(3:0)

Cell available signal to ATM side

Start of cell signal from ATM side

TXSOCU

O

Microprocessor Interface

MPDATA

(15:0)

I/O

Data to/ from microprocessor

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PXB 4350

Pin Definitions and Functions

Pin No.

Symbol

Input (I)

Function

Output (O)

MPADR

(7:1)

I

address to microprocessor

MPWR

MPRD

I

write enable from microprocessor

read enable from microprocessor

chip select from microprocessor

I

MPCS

I

MPINT

MPDREQ

MPRDY

O

interrupt request to microprocessor

DMA request to microprocessor

ready output signal for MPDATA write/ read

to microprocessor

RAM Interface (SSRAM)

RAMADR

(17:0)

O

Common address to all external RAMs

Upstream Connection RAM Interface

RDTAU

(31:0)

I/O

Data to/ from connection RAM upstream incl.

parity bit

RADSCU

RADVU

RCEU

O

upstream RAM address status control

upstream RAM advance input

upstream RAM chip enable

RGWU

ROEU

upstream RAM global write

upstream RAM output enable

Policing RAM Interface

POLDATA I/O

(31:0)

multiplexed data to/ from Policing-RAM/ test-

bus incl. parity bit

POLADSC

POLADV

POLCE

O

address status control to Policing RAM

advance input to Policing RAM

chip enable to Policing RAM

POLCE1

second chip enable for 16k connections

mode using 4Mbyte SSRAMS to POLRAM

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PXB 4350

Pin Definitions and Functions

Pin No.

Symbol

Input (I)

Function

Output (O)

POLGW

POLOE

O

global write to Policing RAM

output enable to Policing RAM

Downstream Connection RAM Interface

RDATAD

(31:0)

I/O

Data to/ from connection RAM upstream incl.

parity bit

RADSCD

RADVD

O

downstream RAM address status control

downstream RAM advance input

downstream RAM chip enable

RCED(3:0)

RGWD

downstream RAM global write

ROED(3:0) O

downstream RAM output enable

RSCD

O

downstream RAM status controller for all

RAM chips

RSPD

O

downstream RAM status processor signal for

all RAM chips

JTAG Interface

TRST

TDI

I

Boundary scan reset

test data input

test clock

I

TCK

TMS

TDO

I

test mode select

test data output

O

Test Interface

OUTTRI

UTTRI

I

puts all outputs except TDO into tristate mode

puts all UTOPIA outputs into tristate mode

Address Reduction Circuit Interface, ARC

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PXB 4350

Pin Definitions and Functions

Pin No.

Symbol

Input (I)

Function

Output (O)

ARC-

I/O

Data from/to ARC incl. parity bit

DAT(16:0)

ARCADR

ARCRES

ARCCS

O

address to ARC

reset to ARC

chip select to ARC

write enable to ARC

output enable to ARC

clock to ARC

ARCWE

ARCOE

ARCCLK

Additional Testpins

Test

Supply

VDD

Power Supply 3.3V.

Ground

VSS

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PXB 4350

Functional Description

2

Functional Description

2.1

Core Functions and Interfaces of the ALP

The ATM Layer Processor (ALP) is a device which has a bi-directional data transfer

throughput of 687Mbit/s for up to 16384 connections. The ALP performs Header Trans-

lation, Traffic Measurement and a simple OAM Fault Management Function in both di-

rections. Additionally a Policing unit is implemented in upstream and a logical Multicast

and Buffer Management Unit is implemented in downstream direction. The Utopia Inter-

face at the ingress and engress side transfers the standardized ATM cell format.

The connection specific data for Policing, Traffic Measurement and OAM can be stored

in external RAM’s. If these functions are not needed the related RAMs can be omitted.

For Header Translation in downstream direction an external RAM is mandatory. In up-

stream direction either an external or an internal Address Reduction Circuit (ARC) can

be used for the conversion of the PN/VPI/VCI into a Local Connection Identifier (LCI).

The internal ARC is limited in the arbitrary usage of the VPI and VCI range.

Address Reduction

Processor

Policing

Processor

OAM and Traffic

Measurement

Processor

Header Translation

and

Multicast Processor

Buffer Management

Processor

µP-Interface

Figure 4 ALP Block Diagram

2.2

Functional Description of user data flow in up- and downstream direction

Throughout this specification the term ‘port’ is used in the meaning given in the UTOPIA

specification [1]. ‘Upstream’ means the direction towards the switching network, ‘Down-

stream’ towards the physical layer device (PHY).

Upstream:

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PXB 4350

Functional Description

In the upstream direction the cells are taken from the PHY-devices into the input UTOPIA

buffer, which performs the speed adaptation between the UTOPIA clock and the internal

ALP clock. Subsequently the header of the cell is extracted together with the port number

used for address reduction. The resulting reduced address is called Local Connection

Identifier (LCI). It uniquely identifies the connection during the processing in the ATM

Layer. In order to make the LCI accessible to the following ATM Layer devices (e.g. AOP,

ABM or ASP) it is mapped into the header of the cell. Additionally the so-called house-

keeping (HK) bits are mapped into the cell header (UDF1 byte), which carry Siemens

proprietary cell identification (e.g.: Cross Office Check) evaluated by the ATM Layer de-

vices within the system. The mapping of new contents into the header is called Header

Translation (HT). In the ALP the LCI is used as address for accessing the external RAMs

containing the connection specific data. All subsequent ATM Layer chips (AOP, ABM,

and ASP) also use the LCI to address connection specific RAMs. The LCI is usually iden-

tical for both upstream and downstream direction.

Two other functions performed upon the upstream cell flow are traffic measurement and

policing. In course of traffic measurement the various traffic counters are read from the

external connection RAM (CONNRAMUP), updated and stored back. The policing unit

(POLU) reads the variables, constants and flags needed by the UPC/NPC algorithm,

performs it and stores the updated state variables back into the policing RAM (POLU-

RAM). If an overflow of contracted bit rate happens, cells will be discarded or tagged de-

pending on the chosen configuration. Both, policing and traffic measurement, require a

preliminary cell type recognition, which uses the cell header and the connection config-

uration flags read from the CONNRAMUP. If not discarded, the cell with the new header

(including LCI and HK) exits ALP through the upstream transmit UTOPIA interface.

Downstream:

After the cell has passed the input UTOPIA buffer the LCI is extracted from the header

and used for addressing the external connection RAM (CONNRAMDO), which contains

the new VPI,VCI and PN as well as the traffic counters for downstream direction. In

course of the header translation the restored VPI, VCI and PN are mapped into the head-

er as defined by the external ATM UTOPIA cell format. For special ‘low end’ applications

there is a possibility to perform a so-called ‘Multicast-light’ function, which means broad-

casting the incoming cell to different ports and/or connections, in exchange for lower per-

formance. The traffic measurements downstream are performed in a similar way as in

the upstream direction. The outgoing cell is intermediately stored in the UTOPIA output

buffer until the addressed PHY device is able to receive it.´

2.3

Address Reduction and Header Translation

At the UNI 256 and at the NNI 4096 Virtual Paths each with 65536 Virtual Connections

can be transferred. [10] requires a minimum support of 4096 connections for a STM-1

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PXB 4350

Functional Description

link and 8192 connections for a STM-4 link. The ALP with a bidirectional STM-4 through-

put supports up to 16384 connections.

The ALP translates in upstream direction the Port Number, VPI and VCI of a connection

into a Local Connection Identifier (LCI). Generally speaking we reduce the huge number

(2*³²) of possible connections to 16384 local connections identified by the LCI. All ATM

Layer functions are related to the LCI. In downstream direction the ALP translates the

LCI of a connection into a Port Number, VPI and VCI. Thus every VPI/VCI value at the

ingress side (upstream) of the ALP can be translated to another arbitrary VPI/VCI value

at the engress side (downstream) of the ALP.

2.3.1

Address Reduction in upstream direction

For the address reduction in upstream direction two operation modes exist. In the first

mode the external Address Reduction Circuit is used for the allocation of an arbitrary

Port Number, VPI and VCI to a LCI. The eternal ACR is user defined. The internal Ad-

dress Reduction Unit can be used in the second mode if the PN, VPI and VCI value is in

a predefined interval.

2.3.2

Internal Address Reduction Circuit

The internal Address Reduction Circuit can be configured by the three register parame-

ters P, M and V. They control the mapping principle of the PN, VPI and VCI to the LCI.

P[2:0] determines the maximum count of PHYs (PN

=2^P)

max

M[3:0] determines the Block size BLS (BLS

=2^M)

max

V[3:0] is the smallest not terminated Virtual Path (VPI =2^V)

min

Internal Address Reduction Circuit

13-M

M-P

P

5

0

PN(5:0)

15

0

VCI(15:0)

VPI(11:0)

11

0

13

M

P

LCI(13:0)

Address Reduction Processor

Figure 5 ALP Internal Address Reduction for the terminated VPI

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Functional Description

The above figure depicts the LCI mapping mechanism for all terminated VPC with VPIs

lower than 2^V-1. The LCI for the not terminated VPC with a VPI value equal or higher than

2^V-1 is only build by the PN and VPI. The Bundle size of the VPC (not terminated) is

equal to the Bundle size (2^M-P-1) of the VCC.

The bit field of the PN and VPI not mapped into the LCI must be zero in the header of the

incoming cell. Otherwise the cell will be discarded. The same is true for the not mapped

bit fields of the VCI of the cell with VPI < 2^V-1 (terminated VPI).

The mapping rule gives the following LCI structure. The LCI address range is divided into

two sections. The upper section contains the LCI which corresponds to the VPI of the not

terminated Virtual Path Connections. The lower block contains the LCI corresponding to

the VPI and VCI values of the terminated Virtual Path Connections. The PHY numbers

PN constitute the LSBs of the LCI so the ascending LCI-values are cyclically associated

with the PHYs. Details about the LCI structure are presented in chapter 2.3.5.

2.3.3

External Address Reduction Circuit

The Address Reduction Circuit can be a Content Addressable Memory or a Pointer

Look-up Circuit which reads the PN, VPI and VCI and delivers the corresponding LCI as

a search result. The ALP supports 4 access modes for the configuration, test and oper-

ation of the external ARC.

External Address

Reduction

Circuit

Address Reduction Processor

32

16

V

1

LCI

VCI

Write an entry

Mode(2): Write

Mode(3): Write

Mode(6): Read

LCI

PN

VPI

Portnumber + VPI + VCI

Status after 30 cycle

S

Read an entry

Mode(0): Write

Mode(1): Read

Mode(6): Read

LCI

VCI

LCI

Portnumber + VPI + VCI

Status after 30 cycle

PN

V

Status (S) informs on mismatch and multimatch

Connection Information (V) valid and/or VP-termination

Figure 6 ALP Interface to the external ARC with configuration, test mode and Data

structure

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Functional Description

a) Programming of the ARC. The LCI and subsequently the PN, VPI and VCI is written

to the ARC. The ARC delivers a status information after 30 cycles.

b) Testing of the ALP. The LCI is written to the ARC. Thereafter the PN, VPI, VCI and

status information is given to the ALP. The status information bit informs whether a

mismatch or multi match occur

c) Testing of the ALP. The PN, VPI and VCI is written to the ARC. Thereafter the LCI

and status information is given to the ALP. The status information bit informs wheth-

er a mismatch or multi match occur.

d) Operation Mode of the ALP. The PN, VPI and VCI is written to the ARC which gives

the corresponding LCI and status information to the ALP after 30 cycles.

External Address

Reduction

Circuit

Address Reduction Processor

32

16

V

1

Address Reduction only using PN/VPI

PN

VPI

Mode(4): Write

Mode(6): Read

Portnumber + VPI

LCI and Status after 30 cycle

S

LCI

Address Reduction during Cell Processing

PN

VCI

LCI

Mode(5): Write

Mode(6): Read

Portnumber + VPI + VCI

LCI and Status after 30 cycle

V

Address Reduction Test

VPI

VCI

LCI

Mode(6): Write

Mode(6): Read

Portnumber + VPI + VCI

LCI + Status after 30 cycle

S

Status (S) informs on mismatch and multimatch

Connection Information (V) valid and/or VP-termination

Figure 7 ALP Interface to the external ARC with operation, test mode and Data

structure

The operation mode is executed for each cell incoming from Utopia receive interface.

The programming mode is used for set-up of connections.

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Functional Description

2.3.4

Difference between external and internal ARC

The selection of the internal or external ARC is generally determined by the usage of VPI

and VCI values. It is shortly explained and depicted in the figure 8 for 2 physical lines

connected to the switch at port 1 and 2.

a) At port 1: There are defined 10 terminated and 205 not terminated VPCs. VPI = 0

contains 73 VCCs (VCI = 0...72) and VPI = 9 contains 40 VCCs (VCI = 0...39).

b) At port 2: There are defined 1 terminated and 180 not terminated VPCs. VPI = 0

contains 86 VCCs (VCI = 0...85).

For the selected VPI and VCI values the usage of the external ARC is mandatory. How-

ever, with different VPI/VCI values for the same number of transmitted VPCs and VCCs

the usage of the internal ARC is possible. The steps for the selection of the right VPI val-

ues is depicted in figure 8.

• Shifting of the VPI values for the first not terminated VP to VPI = 16.

• Additionally the number of all VCC of each terminated VPC have to be the same as the

number of all transmitted VPCs. A VCI range of 256 is defined in this example. With

such VPI/VCI values up to 4 port each transmitting 4096 connections can be served.

A

Search the biggest VP and VC Bundle

Biggest VP-Bundle contains 205 VPs

Biggest VC-Bundle contains 85 VCs

Bundle size will be 256 (rounded to 2^N)

Port 1

Port 2

255

B

Determine the highest number of the terminated VP

Highest VP number is 9

255

221

Range of not

ternimated VPs

Number of terminated VPs is 16 (rounded to 2^N)

196

16

15

16

15

Port 2

Port 1

215

255

Range of

ternimated VPs

10

9

0

180

39

72

1

0

255

0

85

0

VPI

VCI

VPI

VCI

VPI

VCI

Figure 8 VPI/VCI range needed for usage of internal ARC

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Functional Description

2.3.5

LCI Structure given by the internal ARC

In the following figure the relationship between the PN, VPI and VCI and the LCI is de-

picted. The example shows the LCI structure for 4 Ports and a VCI- and VPI-Bundle size

of 128. The Parameters for the internal ARC are:

a) 4 Ports -> P = 2 (PN

=2^P)

max

b) VCI- and VPI-Bundle size of 128 -> M-P = 7 ->

c) 4 Ports a 128 VCI -> Block size 512 -> M = 9 (BLS

d) Number of Blocks are 16384/512 = 32 ->

=2^M)

max

31 Blocks with terminated VPCs and 1 Block with not terminated VPCs ->

VPCs with VPI < 31 are terminated and VPCs with VPI ≥ 31 are transparent ->

the smallest not terminated VPI is 31 -> V = 4 (VPI =2^V-1)

min

16 3 8 3

16 3 8 2

16 3 8 1

16 3 8 0

P N=3

P N=2

P N=1

P N=0

VP I=12 7

:

VP I=1

VP I=0

4

P o r ts e a c h

w ith

1 2 8 n o t

VP C b lo c k

fo r V P I * = 0 -1 2 7

5 1 2 e ntri e s

te r m i n a te d V P C s

VCC bloc k

for VP I=3 0

5 12 e nt r ie s

15 8 7 5

15 8 7 4

15 8 7 3

P N=3

P N=2

P N=1

P N=0

4

P o r ts e a c h

w ith

LCI va lue s

3 1 te rm in a te d

V P C

e a c h

c o n t a in in g

P N=3

P N=2

P N=1

P N=0

5 15

5 14

5 13

5 12

VCI=12 7

:

VCI=1

VCI=0

VCC bloc k

for VP I=1

5 12 e nt r ie s

1 2 8 V C C s

VCI=12 7

:

VCI=1

VCI=0

P N=3

P N=2

P N=1

P N=0

3

VCC bloc k

for VP I=0

5 12 e nt r ie s

2

1

0

* VP I e nt r ie s 0 ..3 0 c ont a in VP -s pe c ific d a t a for t e r m ina t e d VP s

Figure 9 LCI structure for 4 ports with a VCI- and VPI Bundle size of 128

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Functional Description

2.4

Cell Header Structure generated by the ALP

The ATM cell structure transmitted and received at the ingress and engress side of the

ALP is depicted in the figure 10.

15

0

15

0

7

0

VCI(15:12)

VPI(11:0)

VCI(11:0)

PN(5:0)

LCI(11:0)

VCI(11:0)

VPI

VCI

PTI

C

PTI

C

VPI

VCI

LCI HK(2:0)

PD(2:0)*

PT

C

LCI generation

UDF/PN

13

0

A

LCI

PN, VPI and VCI reduction

B

LCI

shown mapping according to

A

an external ARC

or

B

an internal ACR

AOP

ABM

ASP

PHY

ALP

Figure 10 ATM cell structure used by the ALP, AOP, ABM and ASP at the Utopia

Interface

The LCI is mapped into the VPI field and 2 bits (LCI(13:12) in the UDF1 field. This allows

to transport the VCI field transparently through the switch. The housekeeping (HK) bits

are used to differentiate various cell types inside the Siemens switching system e.g. for

user cells HK=111. The ALP extracts in downstream direction all cells with HK=111. The

PD(2:0) field is used to address one of the 8 channels of the IWE8.

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Functional Description

2.5

Policing in upstream direction

At the announcement of a connection request, an acceptance algorithm checks in ATM

networks if enough capacity is available on the transmission line in order to transmit the

user data at the desired bit rate assuring quality of services objectives. The connection

acceptance algorithm usually requires separate policing of Sustainable Cell Rate (SCR)

and Peak Cell Rate (PCR). The policing function checks if the cells of the incoming cell

stream are conforming to the negotiated connection parameters in order to guarantee

the transmission quality for each network user. If the contracted cell rate is exceeded the

cell is either discarded or tagged (changing the CLP bit from 0 to 1, i.e. increasing the cell

loss probability). Policing at the entrance of the public network is called Usage Parame-

ter Control (UPC); policing between two networks is called Network Parameter Control

(NPC).

The UPC/NPC algorithm implemented in the ALP is functionally equivalent to the Gener-

ic Cell Rate Algorithm (i.e. Leaky Bucket or Virtual Scheduling Algorithm, abbreviated

GCRA, LB or VSA) as defined in the ATM Forum, UNI specification [7] and the ITU-T rec-

ommendation [8].

The ALP has a UPC/NPC function capability on a per connection basis for up to 16384

connections. As both, SCR and PCR, should be supervised simultaneously for different

cell flows up to 3 Leaky Buckets (LB) can be provisioned per connection which are ar-

ranged in 2 parallel branches. The first branch contains a LB1 and optionally a LB2 in se-

rial. The second branch contains the LB3.

A port specific policing of 7 different cell flow

• user data

• F4-RM

• F5-RM

• F4-OAM-Segment

• F5-OAM-Segment

• F4-OAM-End-to-End

• F5-OAM-End-to-End

is possible. Each cell flow can be policed either in branch1 or in branch2 or is not policed.

It is possible to disable the UPC/NPC function per connection via SW. The already ad-

justed UPC/NPC parameters can be modified for an established connection without ad-

ditional cell losses.

Via SW up to 4 different Leacky Bucket configurations are selectable per connection.

The policing configuration modes are summarized in table1 and are depicted in the

figure 11 and 12.

The policing unit supports 2*³²PCR values which ranges between 1 cell/s and

1620000 cells/s. The PCR and SCR can be adjusted with a granularity of at least

2*^(-10)cells/s. The maximum burst size of the SCR from LB1 is 1024s. The cell delay vari-

ation of the PCR from LB2 and LB3 can be adjusted up to 4s.

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Functional Description

Table 1 Policing Operation Modes

Configuration Tagging LB1

LB2

LB3

Mode

Option

Yes

No

2)

0

3)

1

2

3

SCR ¹⁾, MBS

PCR

0

0+1

SCR , MBS

PCR

0

0+1

No

SCR

,

0+1

MBS

0+1

4

No

PCR

disabled

PCR

0+1

1) SCR = Sustainable Cell Rate in cell/s

2) MBS = Maximum Burst Size in cell

3) PCR = Peak Cell Rate in cell/s

Σ

CLP = 1

LB2

with cell tagging

Tagging

Σ

CLP=0+1, PCR

CLP = 0

LB1

Discarding

1a) CLP=0, PCR

1b) CLP=0, SCR

LB3

CLP=0+1, PCR

Discarding

Figure 11 Leaky Bucket with cell tagging for policing configuration mode 1

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Functional Description

LB1

2a) CLP=0, PCR

2b) CLP=0, SCR

3) CLP=0+1, SCR

4) CLP=0+1, PCR

LB2

without cell tagging

CLP=0+1, PCR

Discarding

signal

LB3

CLP=0+1, PCR

Discarding

Figure 12 Leaky Bucket without cell tagging for policing configuration mode 2-4

2.6

Header Translation in downstream direction

The ALP translate the LCI into arbitrary PN, VPI and VCI values which are stored in the

external RAM for downstream direction (CONNRAMDO). The PN value determines the

Queue number of the Buffer manager. Additionally to the PN a second Port number can

be written into the UDF1. This is a useful feature especially for low bit rate lines. Per

queue up to 64 ports can be supported which will be served by the Utopia interface with

a single Utopia address. However it is necessary that the PHY device translates the sec-

ond PN in the UDF1 into the corresponding PN of the physical line. The Siemens chip

IWE8 (PXB4220) supports this feature.

2.7

Multicast in downstream direction

Both types of multicast, namely the spatial (sending to several ports) and the logical

(sending to different VPs/VCs running on one port) are possible.The multicast function-

ality is a sequential multicast. That means that for n multicast copies the multicast cell re-

mains n cell cycles in the Utopia input buffer. During the time the cell remains in the buff-

er all other cells are blocked, so that the UTOPIA back pressure signal is asserted to the

previous chip. As the sequential multicast causes additional delay for the succeeding

cells the number of multicast branches has to be carefully taken into account when cal-

culating load and cell delay.

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Functional Description

The cell processing of the multicast is different with respect to point-to-point connections.

The entries in the external RAM for downstream direction (CONNRAMDO) are formed in

a linked list for all connections the cell has to be sent to. Together with the PN/VPI/VCI

value a pointer to the next connection entry is read from the RAM. The cell is kept in the

buffer and transmitted several times to the respective queue of the buffer manager, each

time with the corresponding VPI/VCI combination.

2.8

Buffer management in downstream direction

The Buffer management unit has a shared buffer for 64 cells. Up to 24 queues can be ac-

tivated within the shared buffer. All queues have a common threshold as well as the total

shared buffer. Overflow of queues result in a selective back pressure signals on the re-

ceive downstream Utopia interface. Shared buffer overflow sets the back pressure sig-

nals of all queues.

2.9

OAM Management Unit for up- and downstream direction

Several cell types can be extracted from the cell stream in up- and downstream direction

via an internal 12 cell extraction buffer to the microprocessor interface. The insertion is

possible via a 1 cell insertion buffer. The ALP supports the detection of OAM cells (AIS

cells, RDI cells Continuity Check cells, Continuity Check Activation cells, Loopback

cells), RM cells, and two programmable cell types.

The extraction and insertion point can be defined as an Originating End Point, an Origi-

nating Segment Point, an Intermediate Point, a Terminating Segment Point and a Ter-

minating End Point for both the F4 and F5 flow. Depending on the F4/F5 configuration

the OAM cells are connection specifically treated (forwarded, copied, dropped, or dis-

carded in case of misinserted cells) according to ITU-T [6] and Bellcore Core [9]. For in-

termediate points it is SW selectable whether the OAM cells are forwarded or dropped so

that a monitoring function is possible. For terminating points it is SW selectable per cell

type whether the OAM cells are discarded. Optionally the CRC-10 (EDC) is calculated

for dropped or inserted cells.

2.10

Traffic Measurement Unit for up- and downstream direction

The ALP provides several traffic counters which can be used for Accounting Manage-

ment (i.e. Billing), for observation of the ATM cell traffic behavior as well as for Protocol

Monitoring Measurement. The Traffic Measurement counters can be enabled via SW.

The Traffic Measurement fulfills the Bellcore Requirements GR-1248-core. Traffic mea-

surement data are collected at VCC and VPC level in the external RAMs and at Port level

in the internal Port Tables RAM. The ALP supports a minimum measurement interval of

at least 15 minutes.The following data are collected for the 3 levels:

a) Port level

– Total incoming and outgoing cells

– Total incoming cells with non-zero GFC field

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Functional Description

– Total discarded incoming cells due to unallocated PN/VPI/VCI

– Total incoming and outgoing OAM/RM cells

b) VPC level

– Total incoming and outgoing cells

– Total incoming and outgoing cells with CLP=0

Virtual connection specific counting of

Total incoming and outgoing cells

Total incoming cells with CLP = 0

Total discarded incoming cells due to

UPC/NPC with CLP = 0 and CLP = 1

Total tagged incoming cells due to

UPC/NPC

Traffic Measurement Processor

1

M

Enable / disable Traffic Measurement

according to Bellcore GR-1248-core

VCC Mux

Virtual path specific counting of

Total incoming and outgoing cells

with CLP = 0

1

N

VPC Mux

Port specific counting of

Total incoming and outgoing cells

1

24

Total incoming cells with non-zero GFC field

Total discarded incoming cells due to

unallocated PN/VPI/VCI

Port Mux

Total incoming and outgoing OAM/RM cells

Figure 13 Traffic Measurement at the Port, VPC and VCC level

a) VCC level

– Total incoming and outgoing cells

– Total incoming and outgoing cells with CLP=0

– Total discarded incoming cells due to UPC/NPC with CLP=0 and CLP=1

– Total tagged incoming cells due to UPC/NPC

It is SW selectable per flag whether the port specific special studies counter for down-

stream direction counts OAM cells, or RM cells or discarded F5 RM and PTI reserved

cells. The discarding of F5 RM and PTI reserved cells is a special feature for the IWE8

applications because the IWE8 can’t process RM cells. Furthermore it is SW selectable

per connection with a flag whether this specific connection is counted. With this function-

ality it is possible that one, some or all connections running on this port are counted.

2.11

Microprocessor Access

Four different communication modes are supported by the microprocessor interface:

1. Direct read/write of registers with immediate results.

2. Command mode issued via command register and used e.g. for access to the external

or internal RAMs or for inserting a cell. This mode requires a task specific completion

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Functional Description

time. Therefore after a command is activated the microprocessor has to poll the com-

mand status bit.

3. Interrupt mode, controlled by the interrupt mask and the interrupt status registers.

4. Direct Memory Access (DMA) mode is used for fast data transfer of selected contents

of the Connection RAM directly to the microprocessor RAM. An application for this mode

is to readout the billing counters for all connections (max. 16384).

The microprocessor can insert cells into as well as extract cells from the main cell stream

(up- and downstream). For this purpose a one-cell insertion and a 12-cell extraction buff-

er are provided. Which cells are captured is determined by the contents of SW-config-

urable cell filters using the header, the UDF1 byte and the first payload byte of the exter-

nal ATM cell format.

2.11.1 Microprocessor Access to the internal and external RAMs

Access to internal and external RAMs/tables is done via read and write transfer register

sets. A register set holds the data for one complete entry. The control processor writes

the desired data into the write transfer register set, specifies destination and address and

then issues a command to transfer the data to the respective location. In the same way

data can be transferred back from a RAM location to the read transfer register set.

In addition a read-modify-write command is available to change individual words in the

external RAM. This command is used to enable/disable a connection without having to

reprogram the whole entry.

For the ALP all registers involved in RAM/table transfer commands are shown in

figure 14. Up to 22 words (16Bit) in the read and write transfer registers are transferred

to or from the external RAMs (POLURAM, CONNRAMUP, CONNRAMDO), external

address reduction circuit, the internal cell type filter and the traffic measurement tables.

The selection is done by the microprocessor request definition in the command register.

CONNRAMUP

ARC

POLURAM

ALP-Register

ALP

Write Transfer

Register

Cell Type Filter

Register

Data

22 x 16 Bit

µP

Address

Read Transfer

Register

Traffic Measurement

Port Table

22 x 16 Bit

CONNRAMDO

Figure 14 Microprocessor access to the internal and external RAMs

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Interface Description

3

Interface Description

UTOPIA Interface

3.1

The ALP provides 4 UTOPIA Level 2 interfaces for data transfer up to STM-4. A

maximum of 24 ports is supported with the Utopia address lines. At the PHY side the ALP

acts as an UTOPIA master. At the ATM side it is SW selectable for the receive and

transmit direction of the UTOPIA interface whether it acts as an UTOPIA master or slave.

The UTOPIA mode can be adjusted: single port/multi port with 8 bit/16 bit data bus with

optional parity protection and cell level handshake.

The standard frequencies are up to 25MHz (8 bit, single PHY/multi PHY), 33MHz (8 bit/

16 bit, single PHY/multi PHY), 50 MHz (16bit, single PHY/multi PHY). Up to 8 PHY

devices are supported for a 155 Mbit/s ATM layer and up to 4 PHY devices for a 622

Mbit/s ATM layer.

According to appendix 1 UTOPIA Level 2 specification the ALP provides 4 CLAV/EN

groups the PHYs can be distributed on. This has the advantage that the polling of the

maximally 24 PHYs can be done within 1 cell cycle. The CLAV/EN groups can be

configured in 4 modes: 2*12 PHYs, 3*8 PHYs, 4*6 PHYs and 4*1 PHY without

addressing (Utopia level 1). An example of the Utopia Level 2 configuration for the 4*6

PHYs is depicted in figure15.

Address 1-24

25Mbit/s

1

Address 0:3

CLAV 0

Enb. 0

Enb. 1

PHY

25Mbit/s

6

7

PHY

CLAV 1

25Mbit/s 12

25Mbit/s 13

Enb. 2

Enb. 3

CLAV 2

CLAV 3

25Mbit/s 18

25Mbit/s 19

Operation Mode

A 2 Groups a 12 Addresses

B 3 Groups a 8 Addresses

C 4 Groups a 6 Addresses

D 4 Groups without Address

25Mbit/s 24

Figure 15 Utopia Interface configuration for 4*6 PHYs

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Interface Description

Utopia Handshaking at the PHY side:

• If one of the ports of the upstream receive line is selected (RXADRU) by the ALP and

this port is able to transmit one cell, RXCLAVU is asserted. By asserting RXENBUthe

ALP forces the transmission of a whole cell. RXSOCU indicates the Start Of Cell.

• In downstream direction the ALP selects one port and if the port is able to receive one

cell TXCLAVD is asserted. When the transmission to this port starts, TXENBD and the

TXSOCD is set.

Utopia Handshaking at the ATM side:

• For the upstream transmit line the ALP represents one of 24 ports. Its valid port

address is programmable. If the ALP is selected and TXCLAVU is asserted, then

TXENBU is set, if one cell is available for transmission.

• The cells downstream can be received from up to 24 ports. The selected ALP with

programmable port address asserts RXCLAVD, if it is able to receive one cell. When

the transmission to this port starts, RXENBD and RXSOCD is set.

In the following figures three Utopia configurations with the corresponding system

architecture are depicted. Figure 16 depicts the ALP between the PHYs and an other

ATM Layer device e.g. AOP, ABM or ASP. For this application the Utopia interface at the

ATM side is in slave mode. Figure 17 and 18 depicts an ALP between PHYs used as

multiplexor for access networks or backbone applications.

Figure 16 UTOPIA interface configuration with slave mode at the ATM side

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Interface Description

Figure 17 UTOPIA interface configuration with master mode at the ATM side

Figure 18 UTOPIA interface configuration with master mode for Tx and slave

mode for Rx direction at the ATM side

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Interface Description

The following table gives an overview over the UTOPIA signals:

Backpressure Mechanism

Backpressure means that cell transmission is disabled even if cells are available from

the transmitting port of the preceding ATM device. In this case no RXENBU / RXCLAVD

is set by the ALP in response to an asserted RXCLAVU /TXENBD.

Upstream line: A backpressure is only asserted if an adjacent ATM device asserts a

backpressure to the ALP.

Downstream line: A backpressure is asserted by the ALP if an empty cell cycle time slot

is needed, e.g. for microprocessor request or for cell insertion from the microprocessor

add buffer, or in case of queue or buffer overflow of the statistical demultiplexing buffer.

A PHY overflow leads only indirectly to a backpressure when the corresponding queue

of the statistical multiplexing buffer overflows.

ALP Throughput

Nominally the ALP can cope with an UTOPIA frequency of up to F_UTOPIA=51.84 MHz.

However the average net cell rate over UTOPIA interface should be significantly lower

due to the limits imposed by the time needed for internal data processing at the chosen

ALP core frequency F_CORE. The maximal allowed net UTOPIA throughput is given by:

B_UTMAX= F_CORE* 53 *8 / 32 bit/s

{ATM cell: 53 * 8 bit}

{internal clock cycles per ATM cell: 32}

For F_CORE= 51.84 MHz we get B_UTMAX= 686.88 Mbit/s.

However with this throughput no empty cell time slots in the ALP core will occur which

are necessary for microprocessor access to external RAMs, insertion of cells from the

add buffer as well as the refresh of policing data. The latter one reduces the maximum

allowed net throughput by about 1%, while the time needed for completing

microprocessor requests is inversely proportional to the frequency of empty cell time

slots. In order to be able to read out e.g. the billing counters of 16384 connections within

a time interval smaller then 0.5 seconds, the maximal allowed net throughput has to be

reduced by a further 3%.

3.2

External RAM Interfaces

The ALP chip involves three RAM interfaces, CONNRAMUP and POLURAM for the

upstream and CONNRAMDO for the downstream part. The RAM interfaces support

access to the external synchronous SRAMs using bidirectional 32 bit data bus. The MSB

of the data bus is used as parity signal. Depending on the maximum number of

connections

supported

two

RAM

types

(1M SSRAM (32kx32bit)

or

2M SSRAM (64kx32bit) can be configured. Parity protected SSRAMs allow secure data

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Interface Description

storage. Together with the fast access these two features allow to use the external

RAMs.

SYSCLK

RAMADR(17:0)

RDTAU(31:0)

RADSCU(1:0)

RADVU

RCEU(1:0)

RGWU

ROEU

RDATAD(31:0)

RADSCD(1:0)

RADVD

RCED(1:0)

RGWD

ROED

POLDATA(31:0)

POLADSC(2:0)

POLADV

POLCE(2:0)

POLGW

POLOE

Figure 19 RAM Interface signals for Policing and Connection specific data for up-

stream and downstream direction

CONNRAMUP

CONNRAMUP is used to store:

– Traffic counters.

– Parts of the internal header (namely HK bits).

– Control flags for OAM and internal pointers.

The connection data for one LCI requires 8 x 32bit words in the upstream connection

RAM, so the whole CONNRAMUP has a capacity of 4Mbit for 16k connections (two

64kx32bit SSRAM) or 2 Mbit for 8k connections (one 64kx32bit SSRAMS).

The CONNRAMUP can be omitted if no OAM and Traffic Measurement is needed.

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Interface Description

POLURAM

The POLURAM is used to store:

– State variables and constant parameters of the policing algorithm.

– Control flags for UPC/NPC configuration.

The policing data for one LCI requires 11 x 32bit words in the policing RAM, so the whole

POLURAM has a capacity of 6Mbit for 16k connections (three 64kx32bit SSRAM) or 3

Mbit for 8k connections (three 32kx32bit SSRAMS).

The POLURAM can be omitted if no UPC/NPC is required.

CONNRAMDO

The CONNRAMDO is used to store:

– Traffic Counters.

– The external header (i.e PN, VPI and VCI).

– For Multicast light the pointer to the next entry of the linked list.

– Control flags and internal pointers.

– Additional PN for UDF1 used by IWE8.

The connection data for one LCI requires 7 x 32bit words in the downstream connection

RAM, so the whole CONNRAMUP has a capacity of 4Mbit for 16k connections (two

64kx32bit SSRAM) or 2 Mbit for 8k connections (one 64kx32bit SSRAMS).

3.3

Microprocessor and Control Interface

MPDATA(15:0)

MPADR(7:0)

MPWR

i386EX

MPRD

ALP

MPCS

MPINT

MPRDY

MPDREQ

Figure 20 Microprocessor interface

The ALP chip has an asynchronous microprocessor interface. The interface consists of

an 16 bit wide common data bus with 8 address lines as required for interfacing 80x86

processors. Byte wise access is not supported. The asynchronous bus access is working

with a handshake mechanism for data flow control. During the inactive state the data bus

is switched to high impedance, it becomes active only when Chip Select is active

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Interface Description

.

Table 2

Microprocessor interface signals

Description

Signal

MPDATA(15:0) bidirectional. common data bus between the microprocessor and the

ALP. Its signals will be tristated when MPCS or MPRDY is high.

MPADR(7:0)

MPWR

Address bus for the interface.

Write signal for the interface (active low).

MPRD

Read signal for the interface (active low).

MPCS

Chip select signal used to address the ALP (active low).

Interrupt Request (active low). This pin is an open drain output.

MPINT

MPDREQ

DMA request signal indicating that data is to be read out from the

DMA buffer (active low). After the falling edge of the last possible read

access (which empties the receive buffer), the MPDREQ pin

becomes inactive within 60ns to avoid an additional read access of

the microprocessor.

MPRDY

Ready output signal for microprocessor write and read access (active

high). This pin is put low by the ALP immediately after the falling edge

of the microprocessor read or write signals MPRD/MPWR and

remains inactive until the ALP has put or get the required data via the

bus MPDATA(15:0). During the first clock period after the low-high

change it is driven high by the ATM device. Afterwards it is held high

by a pull-up. During the inactive time of MPRDY the microprocessor

performs wait states.

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Interface Description

3.4

Test/Boundary Scan Interface

TRST

TCK

ALP

TMS

OUTTRI

TDI

Figure 21 Test/Boundary Scan interface

The test/boundary scan pins TRST, TDI, TCK, TMS, OUTTRI, and TDO are required for

board test purposes. The boundary scan is conformal to IEEE 1149.1a (JTAG) serial test

bus protocol and the specification /7/. The ID code of the ALP can be read out from the

boundary scan identity code register. The ID code register contains information about

manufacturer, ATM device number and version number.

Table 3

Boundary Scan interface

TRST

TDI

Asynchronous Reset for the Test-Access-Port-Controller

Test Data Input with internal pull-up resistor

Test clock with internal pull-up resistor

TCK

TMS

Test Mode Select input with internal pull-up resistor

All outputs of ALP except TDO in tristate mode (low active)

Test Data Output

OUTTRI

TDO

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Interface Description

3.5

Clock And Reset Interface

ALP

SYSCLK

RESET

UTPHYCLK

UTATMCLK

Figure 22 Clock and reset interface

ATM device System Clock (SYSCLK):

The ATM device system (core) clock range is 25 MHz up to 51.84 MHz.

Reset Input Signal (RESET):

The RESET signal is fed in via a LVTTL-compatible input. With low level (GND) it causes

an asynchronous reset of the internal circuit. The reset must be asserted for a minimum

of four clock cycles. After the reset is accepted the outputs are hold in inactive state and

all bidirectional I/Os are switched to tristate until RESET is released. At the low to high

transition on the RESET line follows an internal synchronous reset.

UTOPIA clocks (UTPHYCLK, UTATMCLK):

Two UTOPIA clock inputs (one for the PHY- and one for the ATM side), independent

from each other and from SYSCLK, must be provided. The frequency of the UTOPIA

clocks must be lower than or equal to SYSCLK.

ARC clock (ARCCLK):

It is derived from SYSCLK by dividing frequency by a factor of two.

ARC Reset Output Signal (ARCRES):

It is a LVCMOS low active output. It is asserted by ALP for four SYSCLK periods after

the rising edge of RESET.

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Interface Description

3.6

ARC Interface

ARCCLK

ARCCS

ARCWE

ARCOE

ARCRES

ARCADR(3:0)

ARCDAT(16:0)

Figure 23 ARC interface

For the address reduction of the 32 bit input address consisting of concatenated PN/VPI/

VCI values down to the 14 bit LCI up to two parallel cascaded ARC chips are supported.

From the ALP’s perspective they behave like a single chip.

In NNI mode the sum of the length of PN (up to 6 bit), VPI (12bit) and VCI (16bit) exceed

32bit, which can be maximally processed by ARC. In this case only the (16 - (number of

PN bits)) least significant VPI bits are mapped into the input address.

During the connection setup the ARCs are initialized by SW, i.e. the input addresses

(PN/VPI/VCI) of valid connections are stored at the addresses of the corresponding

LCIs. At cell arrival an inverse operation is performed: The PN/VPI/VCI value of the cell

is passed to the ARCs, which search for an corresponding entry and return its LCI.

In some important cases (e.g. the ALP is configurated as an intermediate point of a

virtual path, or F4-OAM cells are received at a virtual path terminating point) pure PN/

VPI translation takes place and the VCI part is ignored.

Table 4

ARC interface signals

ARCDAT(16:0)

ARCADR(3:0)

ARCRESET

ARCCS

Bi directional data bus, MSB is odd parity

Address bus

Reset (low active)

Chip Select (low active)

ARCCLK

ARC clock, 12.5 MHz to 25.92 MHz (half of the ALP

core frequency given by SYSCLK)

ARCWE

ARCOE

Write enable (low active)

Output enable (low active)

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Electrical Characteristics

4

Electrical Characteristics

Absolute Maximum Ratings

4.1

Parameter

Symbol

Limit Values

− 65 to 125

Unit

°C

V

Storage temperature

Voltage on any pin with respect to ground

Input voltage

T_stg

V_S

V_in

I

− 0.4 to V_DD+ 0.4

-0.5 to VCC+0.5

-20 to +20

V

Input / output current

Continuous output current

Power dissipation

mA

W

-25 to +25

P

expected 2.5

Note: Stresses above those listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

4.2

Operating Conditions

Parameter

Symbol

VCC

GND

TA

Limit Values

3.135 to 3.465

0

Unit

V

Supply voltage

Digital ground

V

Ambient temperature under bias

Junction temperature

-0 to 70

°C

TJ

max. 100

4.3

DC Characteristics

tbd.

4.4

AC Characteristics

tbd.

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Package Outlines

5

Package Outlines

BGA-456

(Ball Grid Array)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

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References

6

References

1. UTOPIA Level 1 Specification Version 2.01, March 21, 1994, ATM Forum

2. UTOPIA Level 2 Specification Version 1.0, June 1995, ATM Forum

3. IEEE 1596.3 Standard for Low-Voltage Differential Signals for SCI, Draft 1.3, Nov. 95

4. JTAG

5. ‘ATM Networks: Concepts, Protocols, Applications’, Händel, Schröder, Huber, Addi-

son-Wesley, 1994, ISBN 0-201-42274-3

6. ITU-T Recommendation I.610 „B-ISDN Operation and Maintenance Principles and

Functions“, 11/95

7. UNI 3.1, Specification September 1994, ATM Forum

8. ITU-T Recommendation I.371 „Traffic Control and Congestion Control in B-ISDN“, 11/

95

9. Bellcore TA-NWT 1248

10.Bellcore TA-NWT 1110

6.1

Acronyms

• ABM = PXB 4330 ATM Buffer Manager

• AIS = Alarm Indication Signal (OAM function)

• ALP = PXB 4350 ATM Layer Processor

• AOP = PXB 4340 ATM OAM Processor

• ARC = Address Reduction Circuit

• ASF = Atm Switching Fabric

• ASM = PXB 4310 Atm Switching Matrix

• BGA = Ball Grid Array

• BIP-16 = Bit Interleaved Parity, 16 bit

• BLS = Block Size

• BR = Backward Reporting (PM function)

• byte = octet = 8 bit

• CC = Continuity Check (OAM function)

• CLP = Cell Loss Priority of standardized ATM cell

• CDV = Cell Delay Variation

• CRC-10 = Cyclic Redundancy Check 10

• DMA = Direct Memory Access

• double word = 32 bit

• EDC = Error Detection Code

• FM = Forward Monitoring (PM cell type)

• GCRA = Generic Cell Rate Algorithm

• GFC = Generic Flow Control

• HK = HouseKeeping bits of UDF1 field in UTOPIA cell format

• HT = Header Translation

• I/O = Input / Output

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References

• ITU-T = International Telecommunications Union - Telecommunications standardiza-

tion sector

• IWE8 = PXB 4220 InterWorking Element for 8 channels

• LB = Loopback (OAM function)

• LCI = Local Connection Identifier

• LIC = Line Interface Card or Line Interface Circuit

• LPS = Line Protection Switching

• LSB = Least Significant Bit

• LVDS = Low Voltage Differential Signaling

• MBS = Maximum Burst Size

• MSB = Most Significant Bit

• NNI = Network Network Interface

• NPC = Network Parameter Control

• octet = byte = 8 bit

• OAM = Operation And Maintenance

• PCR = Peak Cell Rate

• PHY = Physical line port

• PM = Performance Monitoring (OAM function)

• PTI = Payload Type Indication field of standardized ATM cell

• RDI = Remote Defect Indication (OAM function)

• RM = Resource Management

• SCR = Sustainable Cell Rate

• SLIF = Switch Link InterFace

• SSRAM = Synchronous Static RAM

• STM-4 = Synchronous Transfer Mode, 4 is equivalent to 622MBit/s

• SW = Software

• tbd = to be defined

• TM = Traffic Management

• UDF1,2 = User Defined Field 1 or 2

• UNI = User Network Interface

• UPC = User Parameter Control

• UTOPIA = Universal Test and OPeration Interface for Atm

• VC- = Virtual Channel specific

• VCC = Virtual Channel Connection

• VCI = Virtual Channel Identifier of standardized ATM cell

• VP- = Virtual Path specific

• VPC = Virtual Path Connection

• VPI = Virtual Path Identifier of standardized ATM cell

• VSA = Virtual Scheduling Algorithm

• Word = 16 bit

Semiconductor Group

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04.97

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INFINEON	PXB4219	IWE8互通元素为8个E1 / T1线路[ IWE8 Interworking Element for 8 E1/T1 Lines ]	290 页
INFINEON	PXB4219E	互通元素为8个E1 / T1线路[ Interworking Element for 8 E1/T1 Lines ]	290 页
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INFINEON	PXB4221	IWE8互通元素为8个E1 / T1线路[ IWE8 Interworking Element for 8 E1/T1 Lines ]	290 页
INFINEON	PXB4221E	互通元素为8个E1 / T1线路[ Interworking Element for 8 E1/T1 Lines ]	290 页