WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA 70°C, VCC = VCCQ = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
IDD0*
DDR333@
CL = 2.5
Units
Operating one bank active-
precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
720
mA
Operating one bank active-
read-precharge current;
IDD1*
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address businputs are SWITCHING; Data pattern is same as IDD4W
=
920
mA
Precharge power-down
current;
IDD2P**
IDD2F**
IDD3P**
IDD3N**
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
24
mA
mA
mA
mA
Precharge standby current;
Active power-down current;
Active standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
240
280
440
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH,
CS - is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
Operating burst write current;
IDD4R*
IDD4W*
IDD5**
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W
1280
1280
1360
mA
mA
mA
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK
=
tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Burst auto refresh current;
Self refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD6**
IDD7*
CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
24
mA
mA
Operating bank interleave
read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-
1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for
detailed timing conditions
2240
Note: These specifications apply to modules built with Samsung components only.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
July 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
