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QT100A-ISMG

型号：

QT100A-ISMG

品牌：

ATMEL[ ATMEL ]

页数：

18 页

PDF大小：

344 K

下载PDF手册
Features  
• Number of Keys:  
– One  
• Technology:  
– Patented spread-spectrum charge-transfer  
• Key outline sizes:  
– 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and  
shapes possible  
• Electrode design:  
– Solid or ring electrode shapes  
• PCB Layers required:  
QTouch™  
Charge Transfer  
IC  
– One  
• Electrode materials:  
– Etched copper, silver, carbon, Indium Tin Oxide (ITO)  
• Electrode substrates:  
– PCB, FPCB, plastic films, glass  
AT42QT100A  
• Panel materials:  
– Plastic, glass, composites, painted surfaces (low particle density metallic paints  
possible)  
• Panel thickness:  
– Up to 50 mm glass, 20 mm plastic (electrode size and Cs dependent)  
• Key sensitivity:  
– Settable via capacitor (Cs)  
• Interface:  
– Digital output, active high  
• Moisture tolerance:  
– Good  
• Power:  
– 2V – 5.5V; 6.5 µA at 2.0V typical  
• Package:  
– 6-pin WSON RoHS compliant  
– 10-pin MSOP RoHS compliant (available to special order with 50K MOQ)  
• Signal processing:  
– Self-calibration, auto drift compensation, noise filtering  
• Applications:  
– Control panels, consumer appliances, toys, lighting controls, mechanical switch  
or button  
• Patents:  
– QTouch™ (patented charge-transfer method)  
9531A–AT42–02/09  
1. Pinout and Schematic  
1.1  
Pinout Configuration  
SNSK  
SNS  
1
2
3
4
5
10  
9
OUT  
1
6
5
OUT  
N/C  
QT100A  
Vss  
2
N/C  
QT100A  
8
SYNC  
7
N/C  
Vss  
N/C  
Vdd  
3
4
SNSK  
6
6-WSON Package  
10-MSOP Package  
1.2  
Pin Descriptions  
Table 1-1.  
Pin Listing  
6-Pin  
10-Pin  
Name  
SNSK  
SNS  
N/C  
WSON  
MSOP  
Type  
I/O  
I/O  
O
Comments  
Sense pin  
Sense pin  
Unused  
Notes  
3
4
–
–
2
5
1
2
3
4
5
6
Cs + Key  
Cs  
Leave open – do not connect  
Leave open – do not connect  
Ground  
N/C  
O
Unused  
Vss  
P
Supply ground  
Power  
Vdd  
P
+2.0 ~ +5.0V  
6-pin package – internally connected to SYNC pin  
10-pin package – always connect pin to Sync  
N/C  
–
6
7
8
I
I
Unused  
6-pin package – pin is either Sync/Slow/Fast Mode,  
depending on logic level applied (see Section 3.1 on  
page 5)  
SYNC  
Sync and Mode Input  
N/C  
–
1
9
O
O
Unused  
Leave open – do not connect  
–
OUT  
10  
Output state  
I
Input only  
I/O Input and output  
O
P
Output only, push-pull  
Ground or power  
2
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
1.3  
Schematic  
Figure 1-1. Basic Circuit Configuration for 6-pin WSON Package  
2 ~ 5V  
SENSE  
ELECTRODE  
QT100A, 6-WSON Pkg.  
*Cb  
VDD  
Rs  
3
SNSK  
Cs  
4
OUT  
SNS  
Cx  
SYNC  
VSS  
*Note: Bypass capacitor Cb should be tightly wired  
between Vdd and Vss  
2. Overview of the QT100A  
2.1  
Introduction  
The QT100A charge-transfer (QT™) touch sensor is a self-contained digital IC capable of  
detecting near-proximity or touch. It will project a touch or proximity field through any dielectric  
like glass, plastic, stone, ceramic, and even most kinds of wood. It can also turn small metal-  
bearing objects into intrinsic sensors, making them responsive to proximity or touch. This  
capability, coupled with its ability to self-calibrate, can lead to entirely new product concepts.  
The QT100A is designed specifically for human interfaces, like control panels, appliances, toys,  
lighting controls, or anywhere a mechanical switch or button may be found. It includes all  
hardware and signal processing functions necessary to provide stable sensing under a wide  
variety of changing conditions. Only a single low cost, noncritical capacitor is required for  
operation.  
The QT100A can also project a proximity field to several centimeters with the proper electrode  
and circuit design.  
Two package types are offered, one of which can directly replace the QT100’s SOT-23-6  
package but with a reduced thickness.  
These devices are intended to replace the QT100.  
Refer to the following application note for more information on migrating from QT100:  
• QTAN0028 – Sensitivity Differences When Migrating from QT100 to QT100A  
3
9531A–AT42–02/09  
2.1.1  
WSON Package Differences with QT100  
A 6-pin WSON package version is available which uses the same basic PCB footprint as the  
QT100’s SOT-23-6 package. The 6-WSON package has a reduced package thickness.  
In converting an existing design from the QT100 to the QT100A, it should be noted that the 6-  
WSON package has a bottom “center pad” which must be either grounded (connected to Vss) or  
isolated. This center pad is wide enough that it can possibly touch the copper pads of the  
QT100’s SOT-23-6 footprint, potentially creating a short circuit between two or more pads. In  
order to prevent this, the solder mask layer of the PCB should be widened slightly, or, the copper  
PCB pads narrowed slightly in size.  
Refer to the following application note for assistance with this conversion process:  
• QTAN0027 – PCB Design Considerations when Changing from 6-pin SOT23 to 6-pin WSON  
Atmel® Products  
A 10-pin MSOP package version is also available to special order with 50K MOQ.  
2.1.2  
Electrical Differences With QT100  
In order to compensate for the fact that the QT100A silicon is 30 percent more sensitive to  
capacitive changes than the QT100, the detection threshold has been increased by 30 percent  
in the QT100A to compensate. The net effect is that the QT100A is behaviorally identical to the  
QT100 (apart from no recalibration timeout), and no change in the value of Cs is required to  
achieve the same sensitivity as the QT100.  
2.2  
Basic Operation  
Figure 1-1 on page 3 shows a basic circuit using the 6-pin WSON package.  
The QT100A employs bursts of charge-transfer cycles to acquire its signal. Burst mode permits  
power consumption in the microamp range, dramatically reduces RF emissions, lowers  
susceptibility to EMI, and yet permits excellent response time. Internally the signals are digitally  
processed to reject impulse noise, using a “consensus” filter which requires four consecutive  
confirmations of a detection before the output is activated.  
The QT switches and charge measurement hardware functions are all internal to the QT100A.  
2.3  
Electrode Drive  
For optimum noise immunity, the electrode should only be connected to SNSK.  
In all cases the rule Cs>>Cx must be observed for proper operation; a typical load capacitance  
(Cx) ranges from 5-20 pF while Cs is usually about 2-50 nF.  
Increasing amounts of Cx destroy gain, therefore it is important to limit the amount of stray  
capacitance on both SNS terminals. This can be done, for example, by minimizing trace lengths  
and widths and keeping these traces away from power or ground traces or copper pours.  
The traces and any components associated with SNS and SNSK will become touch sensitive  
and should be treated with caution to limit the touch area to the desired location.  
A series resistor, Rs, should be placed in line with SNSK to the electrode to suppress ESD and  
EMC effects.  
4
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
2.4  
Sensitivity  
2.4.1  
Introduction  
The sensitivity on the QT100A is a function of things like the value of Cs, electrode size and  
capacitance, electrode shape and orientation, the composition and aspect of the object to be  
sensed, the thickness and composition of any overlaying panel material, and the degree of  
ground coupling of both sensor and object.  
2.4.2  
Increasing Sensitivity  
In some cases it may be desirable to increase sensitivity; for example, when using the sensor  
with very thick panels having a low dielectric constant. Sensitivity can often be increased by  
using a larger electrode or reducing panel thickness. Increasing electrode size can have  
diminishing returns, as high values of Cx will reduce sensor gain.  
The value of Cs also has a dramatic effect on sensitivity, and this can be increased in value with  
the trade-off of slower response time and more power. Increasing the electrode’s surface area  
will not substantially increase touch sensitivity if its diameter is already much larger in surface  
area than the object being detected. Panel material can also be changed to one having a higher  
dielectric constant, which will better help to propagate the field.  
Ground planes around and under the electrode and its SNSK trace will cause high Cx loading  
and destroy gain. The possible signal-to-noise ratio benefits of ground area are more than  
negated by the decreased gain from the circuit, and so ground areas around electrodes are  
discouraged. Metal areas near the electrode will reduce the field strength and increase Cx  
loading and should be avoided, if possible. Keep ground away from the electrodes and traces.  
2.4.3  
Decreasing Sensitivity  
In some cases the QT100A may be too sensitive. In this case gain can be easily lowered by  
decreasing Cs.  
3. Operation Specifics  
3.1  
Run Modes  
3.1.1  
Introduction  
The QT100A has three running modes which depend on the logic level applied to the SYNC pin.  
3.1.2  
Fast Mode (SYNC = 1)  
The QT100A runs in Fast mode if the SYNC pin is permanently high. In this mode the QT100A  
runs at maximum speed at the expense of increased current consumption. Fast mode is useful  
when speed of response is the prime design requirement. The delay between bursts in Fast  
mode is approximately 1 ms, as shown in Figure 3-1.  
5
9531A–AT42–02/09  
Figure 3-1. Fast Mode Bursts (SYNC Held High)  
SNSK  
QT100A1  
~1ms  
SYNC  
3.1.3  
Low Power Mode (SYNC = 0)  
The QT100A runs in Low Power (LP) mode if the SYNC pin is held low. In this mode it sleeps for  
approximately 85 ms at the end of each burst, saving power but slowing response. On detecting  
a possible key touch, it temporarily switches to Fast mode until either the key touch is confirmed  
or found to be spurious (via the detect integration process). It then returns to LP mode after the  
key touch is resolved, as shown in Figure 3-2.  
Figure 3-2. Low Power Mode (SYNC Held Low)  
fast detect  
integrator  
~85ms  
SNSK  
QT100A1  
sleep  
sleep  
sleep  
SYNC  
OUT  
3.1.4  
Sync Mode  
It is possible to synchronize the device to an external clock source by placing an appropriate  
waveform on the SYNC pin. Sync mode can synchronize multiple QT100A devices to each other  
to prevent cross-interference, or it can be used to enhance noise immunity from low frequency  
sources such as 50Hz or 60Hz mains signals.  
The Sync pin is sampled at the end of each burst. If the device is in Fast mode and the Sync pin  
is sampled high, then the device continues to operate in Fast mode (Figure 3-1 on page 6). If  
SYNC is sampled low, then the device goes to sleep. From then on, it will operate in Sync mode  
(Figure 3-2 on page 6). Therefore, to guarantee entry into Sync mode the low period of the  
SYNC signal should be longer than the burst length (Figure 3-3).  
6
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
Figure 3-3. Sync Mode (Triggered by Negative Edges on SYNC)  
SNSK  
sleep  
sleep  
sleep  
Revert to Fast Mode  
QT100A1  
SYNC  
slow mode sleep period  
SNSK  
QT100A1  
sleep  
sleep  
sleep  
Revert to Slow Mode  
slow mode sleep period  
SYNC  
However, once Sync mode has been entered, if the SYNC signal consists of a series of short  
pulses (>10 µs) then a burst will only occur on the falling edge of each pulse (Figure 3-4).  
Figure 3-4. Sync Mode (Short Pulses)  
SNSK  
QT100A1  
>10us  
>10us  
>10us  
SYNC  
In Sync mode, the device will sleep after each measurement burst (just as in LP mode) but will  
be awakened by the falling edge of the SYNC signal, resulting in a new measurement burst. If  
Sync remains unchanged for a period longer than the LP mode sleep period (about 85 ms), the  
device will resume operation in either Fast or LP mode depending on the level of the SYNC pin  
(Figure 3-3).  
There is no detect integrator (DI) in Sync mode (each touch is a detection) but the Max  
On-duration will depend on the time between SYNC pulses; see Section 3.3 on page 7 and  
Section 3.4 on page 8. Recalibration timeout is a fixed number of measurements so will vary  
with the SYNC period.  
3.2  
3.3  
Threshold  
The internal signal threshold level is fixed at 13 counts of change with respect to the internal  
reference level, which in turn adjusts itself slowly in accordance with the drift compensation  
mechanism.  
The QT100A employs a hysteresis dropout of two counts of the delta between the reference and  
threshold levels.  
Max On-duration  
If an object or material obstructs the sense pad the signal may rise enough to create a detection,  
preventing further operation. To prevent this, the sensor includes a timer which monitors  
detections. If a detection exceeds the timer setting the sensor performs a full recalibration. This  
is known as the Max On-duration feature and is set to ~80s (at 3V). This will vary slightly with Cs  
and if Sync mode is used. As the internal timebase for Max On-duration is determined by the  
burst rate, the use of Sync can cause dramatic changes in this parameter depending on the  
Sync pulse spacing.  
7
9531A–AT42–02/09  
3.4  
Detect Integrator  
It is desirable to suppress detections generated by electrical noise or from quick brushes with an  
object. To accomplish this, the QT100A incorporates a detect integration (DI) counter that  
increments with each detection until a limit is reached, after which the output is activated. If no  
detection is sensed prior to the final count, the counter is reset immediately to zero. In the  
QT100A, the required count is four. In LP mode the device will switch to Fast mode temporarily  
in order to resolve the detection more quickly; after a touch is either confirmed or denied the  
device will revert back to normal LP mode operation automatically.  
The DI can also be viewed as a “consensus filter” that requires four successive detections to  
create an output.  
3.5  
3.6  
Forced Sensor Recalibration  
The QT100A has no recalibration pin; a forced recalibration is accomplished when the device is  
powered up or after the recalibration timeout. However, supply drain is low so it is a simple  
matter to treat the entire IC as a controllable load; driving the QT100A's Vdd pin directly from  
another logic gate or a microcontroller port will serve as both power and “forced recalibration”.  
The source resistance of most CMOS gates and microcontrollers is low enough to provide direct  
power without problem.  
Drift Compensation  
Signal drift can occur because of changes in Cx and Cs over time. It is crucial that drift be  
compensated for, otherwise false detections, nondetections, and sensitivity shifts will follow.  
Drift compensation (Figure 3-5) is performed by making the reference level track the raw signal  
at a slow rate, but only while there is no detection in effect. The rate of adjustment must be  
performed slowly, otherwise legitimate detections could be ignored. The QT100A drift  
compensates using a slew-rate limited change to the reference level; the threshold and  
hysteresis values are slaved to this reference.  
Figure 3-5. Drift Compensation  
Signal  
Hysteresis  
Threshold  
Reference  
Output  
Once an object is sensed, the drift compensation mechanism ceases since the signal is  
legitimately high, and therefore should not cause the reference level to change.  
8
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
The QT100A’s drift compensation is asymmetric; the reference level drift-compensates in one  
direction faster than it does in the other. Specifically, it compensates faster for decreasing  
signals than for increasing signals. Increasing signals should not be compensated for quickly,  
since an approaching finger could be compensated for partially or entirely before even  
approaching the sense electrode. However, an obstruction over the sense pad, for which the  
sensor has already made full allowance, could suddenly be removed leaving the sensor with an  
artificially elevated reference level and thus become insensitive to touch. In this latter case, the  
sensor will compensate for the object's removal very quickly, usually in only a few seconds.  
With large values of Cs and small values of Cx, drift compensation will appear to operate more  
slowly than with the converse. Note that the positive and negative drift compensation rates are  
different.  
3.7  
3.8  
Response Time  
The QT100A's response time is highly dependent on run mode and burst length, which in turn is  
dependent on Cs and Cx. With increasing Cs, response time slows, while increasing levels of Cx  
reduce response time. The response time will also be a lot slower in LP or Sync mode due to a  
longer time between burst measurements.  
Spread Spectrum  
The QT100A modulates its internal oscillator by 7.5 percent during the measurement burst.  
This spreads the generated noise over a wider band reducing emission levels. This also reduces  
susceptibility since there is no longer a single fundamental burst frequency.  
3.9  
Output Features  
3.9.1  
Output  
The output of the QT100A is active-high upon detection. The output will remain active-high for  
the duration of the detection, or until the Max On-duration expires, whichever occurs first. If a  
Max On-duration timeout occurs first, the sensor performs a full recalibration and the output  
becomes inactive (low) until the next detection.  
3.9.2  
HeartBeat™ Output  
The QT100A output has a HeartBeat “health” indicator superimposed on it in both LP and Sync  
modes. This operates by taking the output pin into a three-state mode for 15 µs, once before  
every QT burst. This output state can be used to determine that the sensor is operating properly,  
or it can be ignored, using one of several simple methods.  
The HeartBeat indicator can be sampled by using a pull-up resistor on the OUT pin (Figure 3-6  
on page 10), and feeding the resulting positive-going pulse into a counter, flip flop, one-shot, or  
other circuit. The pulses will only be visible when the chip is not detecting a touch.  
9
9531A–AT42–02/09  
Figure 3-6. Obtaining HeartBeat Pulses with a Pull-up Resistor (6-pin WSON Package)  
VDD  
5
VDD  
Ro  
1
3
4
6
SNSK  
OUT  
HeartBeat™ Pulses  
SNS  
SYNC  
VSS  
2
If the sensor is wired to a microcontroller as shown in Figure 3-7, the microcontroller can  
reconfigure the load resistor to either Vss or Vdd depending on the output state of the QT100A,  
so that the pulses are evident in either state.  
Figure 3-7. Using a Microcontroller to Obtain HeartBeat Pulses in Either Output State (6-pin  
WSON Package)  
1
3
Port_M.x  
Port_M.y  
OUT  
SNSK  
SNS  
R0  
4
6
Microcontroller  
SYNC  
Electromechanical devices like relays will usually ignore the short HeartBeat pulse. The pulse  
also has too low a duty cycle to visibly affect LEDs. It can be filtered completely if desired, by  
adding an RC filter to the output, or if interfacing directly and only to a high-impedance CMOS  
input, by doing nothing or at most adding a small noncritical capacitor from OUT to Vss.  
3.9.3  
Output Drive  
The OUT pin is active high and can sink or source up to 2 mA. When a large value of Cs  
(>20 nF) is used the OUT current should be limited to <1 mA to prevent gain-shifting side  
effects, which happen when the load current creates voltage drops on the die and bonding  
wires; these small shifts can materially influence the signal level to cause detection instability.  
10  
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
4. Circuit Guidelines  
4.1  
More Information  
Refer to Application Note QTAN0002, Secrets of a Successful QTouch™ Design, and the Touch  
Sensors Design Guide (both downloadable from the Touch Technology area of Atmel’s website)  
for more information on construction and design methods.  
4.2  
Sample Capacitor  
Cs is the charge sensing sample capacitor. The required Cs value depends on the thickness of  
the panel and its dielectric constant. Thicker panels require larger values of Cs. Typical values  
are 2 nF to 50 nF depending on the sensitivity required; larger values of Cs demand higher  
stability and better dielectric to ensure reliable sensing.  
The Cs capacitor should be a stable type, such as X7R ceramic or PPS film. For more consistent  
sensing from unit to unit, 5 percent tolerance capacitors are recommended. X7R ceramic types  
can be obtained in 5 percent tolerance at little or no extra cost. In applications where high  
sensitivity (long burst length) is required the use of PPS capacitors is recommended.  
4.3  
Power Supply and PCB Layout  
See Section 5.2 on page 12 for the power supply range. At 3V current drain averages less than  
500 µA in Fast mode.  
If the power supply is shared with another electronic system, care should be taken to ensure that  
the supply is free of digital spikes, sags, and surges which can adversely affect the QT100A.  
The QT100A will track slow changes in Vdd, but it can be badly affected by rapid voltage  
fluctuations. It is highly recommended that a separate voltage regulator be used just for the  
QT100A to isolate it from power supply shifts caused by other components.  
If desired, the supply can be regulated using a Low Dropout (LDO) regulator, although such  
regulators often have poor transient line and load stability. Refer to Application Note QTAN0002,  
Secrets of a Successful QTouch™ Design, and the Touch Sensors Design Guide for further  
information on power supply considerations.  
Parts placement: The chip should be placed to minimize the SNSK trace length to reduce low  
frequency pickup, and to reduce stray Cx which degrades gain. The Cs and Rs resistors (see  
Figure 1-1 on page 3) should be placed as close to the body of the chip as possible so that the  
trace between Rs and the SNSK pin is very short, thereby reducing the antenna-like ability of  
this trace to pick up high frequency signals and feed them directly into the chip. A ground plane  
can be used under the chip and the associated discrete components, but the trace from the Rs  
resistor and the electrode should not run near ground, to reduce loading. For best EMC  
performance the circuit should be made entirely with SMT components.  
Electrode trace routing: Keep the electrode trace (and the electrode itself) away from other  
signal, power, and ground traces including over or next to ground planes. Adjacent switching  
signals can induce noise onto the sensing signal; any adjacent trace or ground plane next to, or  
under, the electrode trace will cause an increase in Cx load and desensitize the device. Refer to  
the Touch Sensors Design Guide for further information.  
Important Note: for proper operation a 100 nF (0.1 µF) ceramic bypass capacitor must be  
used directly between Vdd and Vss, to prevent latch-up if there are substantial Vdd  
transients; for example, during an ESD event. The bypass capacitor should be placed  
very close to the Vss and Vdd pins.  
11  
9531A–AT42–02/09  
5. Specifications  
5.1  
Absolute Maximum Specifications  
Operating temperature  
-40°C to +85°C  
-55°C to +125°C  
0 to +6.0V  
Storage temperature  
VDD  
Max continuous pin current, any control or drive pin  
Short circuit duration to VSS, any pin  
Short circuit duration to VDD, any pin  
Voltage forced onto any pin  
20 mA  
Infinite  
Infinite  
-0.6V to (VDD + 0.6) Volts  
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at these or other conditions beyond those  
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification  
conditions for extended periods may affect device reliability  
5.2  
Recommended Operating Conditions  
VDD  
Short-term supply ripple + noise  
+2.0 to 5.5V  
20 mV  
Long-term supply stability  
Cs value  
100 mV  
2 to 50 nF  
5 to 50 pF  
Cx value  
5.3  
AC Specifications  
VDD = 3.0V, Cs = 10 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted  
Parameter  
TRC  
Description  
Recalibration time  
Min  
Typ  
250  
2
Max  
Units  
ms  
Notes  
Cs, Cx dependent  
TPC  
Charge duration  
Transfer duration  
µs  
7.5% spread spectrum variation  
7.5% spread spectrum variation  
TPT  
2
µs  
Time between end of burst and  
start of the next (Fast mode)  
TG1  
TG2  
1
ms  
ms  
Time between end of burst and  
start of the next (LP mode)  
85  
20  
Increases with decreasing VDD  
VDD, Cs and Cx dependent  
TBL  
TR  
Burst length  
ms  
ms  
µs  
Response time  
HeartBeat pulse width  
100  
THB  
15  
12  
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
5.4  
Signal Processing  
Vdd = 3.0V, Cs = 10 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted  
Description  
Min  
Typ  
13  
3
Max  
Units  
counts  
Notes  
Threshold differential  
Hysteresis  
See Note 1  
See Note 1  
counts  
Consensus filter length  
Max on-duration  
4
samples  
seconds  
80  
Note 1: Threshold and hysteresis differ from the QT100 in order to maintain the same sensitivity levels; see Section 2.1.2  
on page 4.  
5.5  
DC Specifications  
Vdd = 3.0V, Cs = 10 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted  
Parameter  
Description  
Min  
Typ  
Max  
Units  
Notes  
IDD  
Supply current, Fast mode  
600  
µA  
3V  
6.5  
17  
45  
2V  
3V  
5V  
Iddl  
Supply current, LP Mode  
12  
µA  
VDDS  
VIL  
Supply turn-on slope  
Low input logic level  
High input logic level  
Low output voltage  
100  
2.2  
V/s  
V
Required for proper start-up  
SYNC pin  
0.8  
0.6  
VHL  
VOL  
VOH  
IIL  
V
SYNC pin  
V
OUT, 4 mA sink  
OUT, 1 mA source  
High output voltage  
Input leakage current  
Load capacitance range  
Acquisition resolution  
VDD-0.7  
0
V
1
100  
14  
µA  
pF  
bits  
CX  
AR  
9
13  
9531A–AT42–02/09  
5.6  
Mechanical Dimensions  
5.6.1  
6-pin WSON  
14  
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
5.6.2  
10-pin MSOP  
(available to special order with 50K MOQ)  
15  
9531A–AT42–02/09  
5.7  
Marking  
5.7.1  
6-pin WSON  
Pin 1 ID  
Abbreviation of  
Part number:  
QT100A  
QRG 1R7  
run nr.  
QT100A-ISG  
Code revision 1.7,  
released  
Variable text  
5.7.2  
10-pin MSOP  
Abbreviation of  
Part number:  
QT100A  
DATECODE  
QT100A-ISMG  
Datecode  
(variable)  
Pin 1 ID  
5.8  
Part Number  
Part Number  
QT100A-ISG  
QT100A-ISMG  
Description  
6-pin WSON RoHS compliant IC  
10-pin MSOP RoHS compliant IC (available to special order with 50K MOQ)  
5.9  
Moisture Sensitivity Level (MSL)  
MSL Rating  
Peak Body Temperature  
Specifications  
MSL3  
260oC  
IPC/JEDEC J-STD-020  
16  
AT42QT100A  
9531A–AT42–02/09  
AT42QT100A  
Revision History  
Revision No.  
History  
Initial release for chip revision 1.7.  
Revision A – February 2009  
17  
9531A–AT42–02/09  
Headquarters  
International  
Atmel Corporation  
2325 Orchard Parkway  
San Jose, CA 95131  
USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 487-2600  
Atmel Asia  
Atmel Europe  
Le Krebs  
Atmel Japan  
9F, Tonetsu Shinkawa Bldg.  
1-24-8 Shinkawa  
Chuo-ku, Tokyo 104-0033  
Japan  
Tel: (81) 3-3523-3551  
Fax: (81) 3-3523-7581  
Unit 01-05 & 16, 19/F  
BEA Tower, Millennium City 5  
418 Kwun Tong Road  
Kwun Tong  
Kowloon  
Hong Kong  
8, Rue Jean-Pierre Timbaud  
BP 309  
78054 Saint-Quentin-en-  
Yvelines Cedex  
France  
Tel: (852) 2245-6100  
Fax: (852) 2722-1369  
Tel: (33) 1-30-60-70-00  
Fax: (33) 1-30-60-71-11  
Touch Technology Division  
1 Mitchell Point  
Ensign Way  
Hamble  
Southampton  
Hampshire SO31 4RF  
United Kingdom  
Tel: (44) 23-8056-5600  
Fax: (44) 23-8045-3939  
Product Contact  
Web Site  
Technical Support  
Sales Contact  
www.atmel.com  
touch@atmel.com  
www.atmel.com/contacts  
Literature Requests  
www.atmel.com/literature  
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any  
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND  
CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR  
STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS  
FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL,  
PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR  
LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY  
OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the  
right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information  
contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are  
not intended, authorized, or warranted for use as components in applications intended to support or sustain life.  
© 2008–2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, and others are registered trademarks, QT™,  
QTouch™, HeartBeat™ and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be registered  
trademarks or trademarks of others.  
9531A–AT42–02/09  
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